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23rd RSP 2012: Tampere, Finland
- Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, RSP 2012, Tampere, Finland, October 11-12, 2012. IEEE 2012, ISBN 978-1-4673-2786-2
Keynote
- Nikil D. Dutt
:
Keynote speach.
Application
- Alexandra Aguiar, Carlos Moratelli
Hardware-assisted virtualization targeting MIPS-based SoCs. 2-8 - Yan Ghidini, Thais Webber
Buffer depth and traffic influence on 3D NoCs performance. 9-15 - BaekGyu Kim
A model-based I/O interface synthesis framework for the cross-platform software modeling. 16-22 - Virginie Fresse, Zhiwei Ge, Junyan Tan, Frédéric Rousseau:
Case study: Deployment of the 2D NoC on 3D for the generation of large emulation platforms. 23-29 - Carlos A. Petry, Eduardo Wächter
A spectrum of MPSoC models for design space exploration and its use. 30-35 - Nico Adler, Martin Hillenbrand, Klaus D. Müller-Glaser, Eduard Metzker, Clemens Reichmann:
Graphically notated fault modeling and safety analysis in the context of electric and electronic architecture development and functional safety. 36-42
Performance evaluation
- Ihsen Alouani
Parity-based mono-Copy Cache for low power consumption and high reliability. 44-48 - Dukyoung Yun, Youngmin Yi, Sungchan Kim, Soonhoi Ha:
A cycle-level parallel simulation technique exploiting both space and time parallelism. 50-56 - Marcelo Guedes, Rafael Auler, Edson Borin, Rodolfo Azevedo
An ArchC approach for automatic energy consumption characterization of processors. 57-63 - Sofiane Lagraa, Alexandre Termier, Frédéric Pétrot:
Automatic congestion detection in MPSoC programs using data mining on simulation traces. 64-70 - Qingshan Tang, Habib Mehrez, Matthieu Tuna:
Design for prototyping of a parameterizable cluster-based Multi-Core System-on-Chip on a multi-FPGA board. 71-77
Model-Based Techniques
- Olivier Bouissou, Samuel Mimram, Alexandre Chapoutot
HySon: Set-based simulation of hybrid systems. 79-85 - Frédéric Mallet
Automatic generation of observers from MARTE/CCSL. 86-92 - Christian Fotsing, Annie Geniet:
Integrating semantic properties within a Petri net based scheduling tool. 93-99 - Tobias Schwalb, Tobias Gädeke, Johannes Schmid, Klaus D. Müller-Glaser:
Seamless model-based design and deployment of wireless networked systems. 100-106 - Gilberto Ochoa-Ruiz
Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT. 107-113
Reconfigurable Systems
- Ian Gray, Neil C. Audsley:
Challenges in software development for multicore System-on-Chip development. 115-121 - Hai H. Nguyen, Mikael Guillemot, Yvon Savaria, Yves Blaquière:
A new approach for pin detection for an electronic system prototyping reconfigurable platform. 122-127 - Konstantin Nasartschuk, Rainer Herpers
Visualization support for FPGA architecture exploration. 128-134 - Diego Puschini, Julien Mottin, Nicolas Palix
Integrated architecture exploration workflow: A NoC-based case study. 135-141
System Synthesis
- Purushotham Murugappa, Jean-Noel Bazin, Amer Baghdadi
FPGA prototyping and performance evaluation of multi-standard Turbo/LDPC Encoding and Decoding. 143-148 - Anup Das
Fault-aware task re-mapping for throughput constrained multimedia applications on NoC-based MPSoCs. 149-155 - Nuno Roma
System-level prototyping framework for heterogeneous multi-core architecture applied to biological sequence analysis. 156-162 - Sungjin Lee, Jisung Park
FlashBench: A workbench for a rapid development of flash-based storage devices. 163-169 - Jiashu Li, Anup Das
A design flow for partially reconfigurable heterogeneous multi-processor platforms. 170-176 - Philipp Mahr, Christophe Bobda:
Reducing communication costs on Dynamic Networks-on-Chip through runtime relocation of tasks. 177-182
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