default search action
PARELEC 2006: Bialystok, Poland
- Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 13-17 September 2006, Bialystok, Poland. IEEE Computer Society 2006, ISBN 0-7695-2554-7
Invited Papers
- Alexey L. Lastovetsky
:
Scientific Programming for Heterogeneous Systems - Bridging the Gap between Algorithms and Applications. 3-8 - Pawel Gepner
Multi-Core Processors: New Way to Achieve High System Performance. 9-13 - Dan Grigoras:
Challenges to the Design of Mobile Middleware Systems. 14-19 - Carsten Trinitis:
Automatic High Voltage Apparatus Optimization: Making it More Engineer-Friendly. 20-30
Parallel System Architecture
- Bernhard Fechner
A Fault-Tolerant Dynamic Fetch Policy for SMT Processors in Multi-Bus Environments. 31-36 - D. Doreen Hephzibah Miriam, T. Srinivasan, R. Deepa:
An Efficient SRA Based Isomorphic Task Allocation Scheme for k - ary n - cube Massively Parallel Processors. 37-42 - Marcin Gorawski, Michal Gorawski
Balanced Spatio-Temporal Data Warehouse with R-MVB, STCAT and BITMAP Indexes. 43-48 - Dajin Wang:
An Algorithm to Embed Hamiltonian Cycles in Crossed Cubes. 49-54 - Christian Sauer, Matthias Gries
Application-Driven Development of Concurrent Packet Processing Platforms. 55-61 - Tomasz Madajczak, Henryk Krawczyk:
Integrating SHECS-Based Critical Sections with Hardware SMP Scheduler in TLP-CMPs. 62-67 - Faezeh Montazeri, Mehdi Salmani Jelodar, S. Najmeh Fakhraie, Seid Mehdi Fakhraie:
Evolutionary Multiprocessor Task Scheduling. 68-76
Parallel System Modeling
- Marek S. Tudruj
Fast Matrix Multiplication in Dynamic SMP Clusters with Communication on the Fly in Systems on Chip Technology. 77-82 - Adam Smyk
Open MP Extension for Multithreaded Computing with Dynamic SMP Processor Clusters with Communication on the Fly. 83-88 - Jan Müller:
Generalised Resource Model for Parallel Instruction Scheduling. 89-94 - Lukasz Masko, Gregory Mounie, Denis Trystram, Marek S. Tudruj
Program Graph Structuring for Execution in Dynamic SMP Clusters Using Moldable Tasks. 95-100 - Abdellah Yousfi
The Centisecond Two Levels Hidden Semi Markov Model (CTLHSMM). 101-104 - Adrian Kosowski, Lukasz Kuszner
Energy Optimisation in Resilient Self-Stabilizing Processes. 105-110
Grids
- Christian Kauhaus, Dietmar Fey:
Building Mini-Grid Environments with Virtual Private Networks: A Pragmatic Approach. 111-115 - Daniel Lamch, Roman Wyrzykowski
Specification, Analysis and Testing of Grid Environments Using Abstract State Machines. 116-120 - Adam Kozakiewicz, Andrzej Karbowski
A Two-Level Approach to Building a Campus Grid. 121-126 - Jirí Jaros
Complexity of Collective Communications on NoCs. 127-133 - Florin Pop, Ciprian Dobre
A Simulation Model for Grid Scheduling Analysis and Optimization. 133-138 - T. Srinivasan, N. Dhanasekar, M. Nivedita, R. Dhivyakrishnan, A. A. Azeezunnisa:
Scalable and Parallel Aggregated Bit Vector Packet Classification Using Prefix Computation Model. 139-144 - Stefan Dydel, Krzysztof Benedyczak, Piotr Bala
Enabling Reconfigurable Hardware Accelerators for the Grid. 145-152
Automatic Parellelization
- Hritam Dutta, Frank Hannig
Hierarchical Partitioning for Piecewise Linear Algorithms. 153-160 - K. Ashwin Kumar, Aasish Kumar Pappu, K. Sarath Kumar, Sudip Sanyal:
Hybrid Approach for Parallelization of Sequential Code with Function Level and Block Level Parallelization. 161-166 - Rainer Schaffer, Renate Merker, Francky Catthoor:
Derivation of Packing Instructions for Exploiting Sub-Word Parallelism. 167-172 - Sebastian Siegel, Rainer Schaffer, Renate Merker:
Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels. 173-180
Reconfigurable Computing
- Alexander A. Petrovsky, Sergei L. Shkredov:
Automatic Generation of Split-Radix 2-4 Parallel-Pipeline FFT Processors: Hardware Reconfiguration and Core Optimizations. 181-186 - Torsten Mehlan, Jochen Strunk, Torsten Hoefler, Frank Mietke, Wolfgang Rehm:
IRS - A Portable Interface for Reconfigurable Systems. 187-191 - Sarma Nedunuri, John Y. Cheung, Prakasa Nedunuri:
Design of Low Memory Usage Discrete Wavelet Transform on FPGA Using Novel Diagonal Scan. 192-197 - A. Pedram, Mohammad Reza Jamali
Reconfigurable Parallel Hardware for Computing Local Linear Neuro-Fuzzy Model. 198-201 - Eryk Laskowski
Efficient Parallel Embedded Computing through Look-Ahead Configured Dynamic Inter-Processor Connections. 202-207 - Oleg Maslennikow, Anatoli Sergyienko
Mapping DSP Algorithms into FPGA. 208-213 - Björn Griese, Boris Kettelhoit, Mario Porrmann
Evaluation of On-Chip Interfaces for Dynamically Reconfigurable Coprocessors. 214-219 - Jacek Pierzchlewski, Pawel Sniatala, Blazej Nowakowski, Andrzej Rybarczyk, Wojciech Wencel:
FPGA Chip as a System Master for Hardware Aided Parallel Computing. 220-226
Performance Monitoring, Analysis Tools and Methods
- Torsten Hoefler, Carsten Viertel, Torsten Mehlan, Frank Mietke, Wolfgang Rehm:
Assessing Single-Message and Multi-Node Communication Performance of InfiniBand. 227-232 - Janusz Borkowski, Damian Kopanski, Marek S. Tudruj
Parallel Irregular Computations Control Based on Global Predicate Monitoring. 233-238 - Farshad Safaei, Ahmad Khonsari
Performance Modeling of Fault-Tolerant Circuit-Switched Communication Networks. 239-244 - Ahmed Yassin Al-Dubai, Imed Romdhani:
A Performance Study of Path Based Multicast Communication Algorithms. 245-250 - Risto Honkanen:
Nearly-All-Optical Routing in Sparse Optical Tori. 251-256 - Valérie Fiolet, Eryk Laskowski
Optimizing Distributed Data Mining Applications Based on Object Clustering Methods. 257-262 - (Withdrawn) Communication Generation for Irregular Parallel Applications. 263-270
Parallel Numerics
- Kirill V. Pavsky
Stochastic Analysis of Solving Complex Problem on Distributed Computer. 271-274 - Wojciech Bozejko
A Fast Parallel Dynasearch Algorithm for Some Scheduling Problems. 275-280 - S. Viswanadha Raju, A. Vinaya Babu, M. Mrudula:
Backend Engine for Parallel String Matching Using Boolean Matrix. 281-283 - Przemyslaw Stpiczynski, Joanna Potiopa:
Piecewise Cubic Interpolation on Distributed Memory Parallel Computers and Clusters of Workstations. 284-289 - Suri Pushpa, Prasad Vinod, Carsten Maple:
Creating a Forest of Binary Search Trees for a Multiprocessor System. 290-295 - Jaroslaw Forenc
Time Domain Decomposition in Parallel Analysis of Transient States. 295-300 - Andrzej Rybarczyk, Michal Szulc, Jaroslaw Wencel:
The CCM Based Implementation of the Parallel Variant of BiCG Algorithm Suitable for Massively Parallel Computing. 301-308
Modeling and Optimization
- Grzegorz M. Wójcik
Pattern Separation in the Model of Mammalian Visual System. 309-312 - Joanna Kolodziej
HGSNash Strategy as the Decision-Making Method for Water Resource Systems with External Disagreement of Interests. 313-318 - Wojciech Kwedlo
A Parallel Differential Evolution Algorithm A Parallel Differential Evolution Algorithm. 319-324 - Karol Banczyk, Tomasz Boinski, Henryk Krawczyk:
Parallelisation of Genetic Algorithms for Solving University Timetabling Problems. 325-330 - Jan Kwiatkowski, Marcin Pawlik, Urszula Markowska-Kaczmar
Performance Evaluation of Different Kohenen Network Parallelization Techniques. 331-336 - Amin Farmahini Farahani, Mehdi Kamal, Mehdi Salmani Jelodar:
Parallel-Genetic-Algorithm-Based HW/SW Partitioning. 337-342 - R. Deepa, T. Srinivasan, D. Doreen Hephzibah Miriam:
An Efficient Task Scheduling Technique in Heterogeneous Systems Using Self-Adaptive Selection-Based Genetic Algorithm. 343-348 - Zbigniew J. Czech:
Speeding Up Sequential Simulated Annealing by Parallelization. 349-356
Image and Signal Processing
- Yunsong Wu, Graham M. Megson:
Parallel Linear Hashtable Motion Estimation Algorithm for Parallel Video Processing. 357-362 - A. Rodríguez, A. González, Manuel P. Malumbres
Hierarchical Parallelization of an H.264/AVC Video Encoder. 363-368 - Marcus Komann, Dietmar Fey:
Marching Pixels - Using Organic Computing Principles in Embedded Parallel Hardware. 369-373 - Michael Schmidt
A Space-Time Multiplex Architecture for 3D Stacked Embedded Vision Systems. 374-379 - Grzegorz Pastuszak
Parallel Symbol Architectures for H.264/AVC Binary Coder Based on Arithmetic Coding. 380-385 - Awni Itradat, M. Omair Ahmad, Ali M. Shatnawi
A Delay-Optimal Static Scheduling of DSP Applications Mapped onto Multiprocessor Architectures. 386-391 - G. Rubin, K. Bielawski, J. Baszun:
A Hardware Conceptual Prototyping of the Genetic Algorithm to Adaptive IIR Filtering. 392-395 - Rafal Kapela
The Neighboring Pixel Representation for Efficient Binary Image Processing Operations. 396-404
Applications of Parallel Computing
- Qi Huang, Kaiyu Qin
A Software Architecture Based on Multi-Agent and Grid Computing for Electric Power System Applications. 405-410 - Qi Huang, Jianbo Yi, Shi Jing, Ke Huang:
Development of an MPI for Power System Distributed Parallel Computing in Wide Area Network with P2P Technology. 411-416 - Rajesh K. Bawa, V. Rathish Kumar, Tanu Gupta:
Parallel Mesh Division Algorithm For General Linear Two Point Boundary Value Problems. 417-420 - Adam Smyk
Parallel FDTD Computations Optimized by Program Macro Data Flow Graph Redeployment. 421-426 - Leszek Kasprzyk
Using a Parallel Virtual Machine to Optimize Lighting Systems. 427-432 - Qi Huang, Xiaoping Chen, Bingfeng Wang, Ronghai Cai, Kaiyu Qin
The Concept of Computing on Chip (CoC) for Electric Power System Application. 433-437 - Luis García, Coromoto León, Gara Miranda
Two-Dimensional Cutting Stock Problem: Shared Memory Parallelizations. 438-443 - Carmen B. Navarrete, Susana Holgado, Eloy Anguiano:
MPI and Non-MPI Simulations for Epitaxial Surface Growth. 444-447 - Mariusz Pelc
Computer Cluster as a Tool in the Continuous Exact State Reconstruction. 448-460 - Pawel B. Myszkowski:
The Change of State Variables in Global Linearization of Non-Linear State Equation. 454-460 - Robert Piotr Bycul, Pawel B. Myszkowski:
A Computer Aided Global Linearization of a Non-Linear Electric circuit. 461-465 - Wojciech Walendziuk
The Use of the Dynamic Space Decomposition Algorithm of a Computational Area in Heterogeneous Cluster Computations. 466-469 - Boguslaw Butrylo
Distributed Optimization of Temperature Field for Reliable Construction of Electronic Circuits. 470-476
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-15 19:19 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: