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Hritam Dutta
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2010 – 2019
- 2019
- [j4]Richard Membarth
, Hritam Dutta, Frank Hannig
Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards. Trans. High Perform. Embed. Archit. Compil. 5: 1-20 (2019) - 2011
- [b1]Hritam Dutta:
Synthesis and exploration of loop accelerators for systems-on-a-chip. University of Erlangen-Nuremberg, 2011, pp. 1-221 - 2010
- [c18]Hritam Dutta, Frank Hannig
Modeling and synthesis of communication subsystems for loop accelerator pipelines. ASAP 2010: 125-132
2000 – 2009
- 2009
- [j3]Hritam Dutta, Dmitrij Kissler, Frank Hannig
A holistic approach for tightly coupled reconfigurable parallel processors. Microprocess. Microsystems 33(1): 53-62 (2009) - [c17]Frank Hannig
Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning. ARCS 2009: 16-27 - [c16]Hritam Dutta, Frank Hannig
Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis. ARCS 2009: 233-245 - [c15]Hritam Dutta, Jiali Zhai, Frank Hannig
Impact of Loop Tiling on the Controller Logic of Acceleration Engines. ASAP 2009: 161-168 - [c14]Richard Membarth, Philipp Kutzer, Hritam Dutta, Frank Hannig
Acceleration of Multiresolution Imaging Algorithms: A Comparative Study. ASAP 2009: 211-214 - [c13]Joachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, Jürgen Teich:
Model-based synthesis and optimization of static multi-rate image processing algorithms. DATE 2009: 135-140 - [c12]Richard Membarth, Frank Hannig
Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors. SAMOS 2009: 277-288 - 2008
- [c11]Frank Hannig
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. ARC 2008: 284-289 - [c10]Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig
Coarse-grained reconfiguration. FPL 2008: 349 - 2007
- [j2]Hritam Dutta, Frank Hannig
Efficient control generation for mapping nested loop programs onto processor arrays. J. Syst. Archit. 53(5-6): 300-309 (2007) - [c9]Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet:
A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. ERSA 2007: 14-24 - [c8]Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier:
Massively Parallel Processor Architectures: A Co-design Approach. ReCoSoC 2007: 61-68 - 2006
- [j1]Frank Hannig, Hritam Dutta, Jürgen Teich:
Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology. Int. J. Embed. Syst. 2(1/2): 114-127 (2006) - [c7]Hritam Dutta, Frank Hannig
Controller Synthesis for Mapping Partitioned Programs on Array Architectures. ARCS 2006: 176-190 - [c6]Hritam Dutta, Frank Hannig
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. ASAP 2006: 331-340 - [c5]Hritam Dutta, Frank Hannig
Hierarchical Partitioning for Piecewise Linear Algorithms. PARELEC 2006: 153-160 - 2005
- [c4]Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Ménard, Olivier Sentieys:
Co-Design of Massively Parallel Embedded Processor Architectures. ReCoSoC 2005: 27-34 - [c3]Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich:
Automatic FIR Filter Generation for FPGAs. SAMOS 2005: 51-61 - 2004
- [c2]Frank Hannig, Hritam Dutta, Jürgen Teich:
Regular mapping for coarse-grained reconfigurable architectures. ICASSP (5) 2004: 57-60 - [c1]Frank Hannig, Hritam Dutta, Jürgen Teich:
Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology. IPDPS 2004
Coauthor Index
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