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SoC 2010: Tampere, Finland
- 2010 International Symposium on System on Chip, SoC 2010, Tampere, September 29-30, 2010. IEEE 2010, ISBN 978-1-4244-8279-5
- Usha Sandeep Mehta
, Niranjan M. Devashrayee
Hamming Distance Based 2-D Reordering with Power Efficient Don't Care Bit Filling: Optimizing the test data compression method. 1-7 - Guang Sun, Yong Li, Yuanyuan Zhang, Li Su, Depeng Jin, Lieguang Zeng:
Energy-aware run-time mapping for homogeneous NoC. 8-11 - Pallavi Reddy, Fabien Clermidy, Rasheed Al Khayat, Amer Baghdadi
Power consumption analysis and energy efficient optimization for turbo decoder implementation. 12-17 - Subayal Khan, Eila Ovaska
From Y-chart to seamless integration of application design and performance simulation. 18-25 - Roberto Airoldi, Fabio Garzia, Omer Anjum, Jari Nurmi
Homogeneous MPSoC as baseband signal processing engine for OFDM systems. 26-30 - Tomi Aarnio, Claudio Brunelli, Timo Viitanen
Efficient floating-point texture decompression. 31-34 - Alexander Klimm, Matthias Haas, Oliver Sander, Jürgen Becker:
A flexible integrated cryptoprocessor for authentication protocols based on hyperelliptic curve cryptography. 35-42 - Alessandro Strano, Carles Hernández
Process variation and layout mismatch tolerant design of source synchronous links for GALS networks-on-chip. 43-48 - Chris Jackson, Simon J. Hollis:
Skip-links: A dynamically reconfiguring topology for energy-efficient NoCs. 49-54 - Sebastian Höppner, Dennis Walter, Holger Eisenreich, René Schüffny:
Efficient compensation of delay variations in high-speed network-on-chip data links. 55-58 - Claudio Brunelli, Roberto Airoldi, Jari Nurmi
Implementation and benchmarking of FFT algorithms on multicore platforms. 59-62 - Piia Saastamoinen, Jari Nurmi
Parameterized decompression hardware for a program memory compression system. 63-67 - Sanna Määttä, Leandro Soares Indrusiak
A case study of hierarchically heterogeneous application modelling using UML and Ptolemy II. 68-71 - Rainer Findenig, Wolfgang Ecker:
State chart refinement validation from approximately timed to cycle callable models. 72-75 - Nguyen Anh Vu Doan, Frédéric Robert, Yves De Smet, Dragomir Milojevic
MCDA-based methodology for efficient 3D-design space exploration and decision. 76-83 - Leonel Tedesco
A message-level monitoring protocol for QoS flows in NoCs. 84-88 - Tiago Dias
H.264/AVC framework for multi-core embedded video encoders. 89-92 - Muhammad Nadeem, Stephan Wong, Georgi Kuzmanov, Ahsan Shabbir, Muhammad Faisal Nadeem, Fakhar Anjam:
Low-power, high-throughput deblocking filter for H.264/AVC. 93-98 - Vladimír Guzma, Teemu Pitkänen, Jarmo Takala
Reducing instruction memory energy consumption by using Instruction Buffer and after scheduling analysis. 99-102 - Timon D. ter Braak, S. T. Burgess, H. Hurskainen, Hans G. Kerkhoff, Bart Vermeulen, Xiao Zhang:
On-line dependability enhancement of multiprocessor SoCs by resource management. 103-110 - Amirali Ghofrani, Fatemeh Javaheri, Saeed Safari
Automatic selection of efficient observability points in combinational gate level circuits using particle swarm optimization. 111-114 - Adolf Samir Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser:
Correct and energy-efficient design of SoCs: The H.264 encoder case study. 115-120 - Thomas Coenen, Jochen Schleifer, Oliver Weiß, Tobias G. Noll:
Interconnect routing of embedded FPGAs using standard VLSI routing tools. 121-124 - Joonas Tyystjärvi, Tero Säntti, Juha Plosila
Heap access optimizations for a hardware-accelerated Java virtual machine. 125-128 - Spencer S. Kellis
Hybrid on-chip clocking for sensor nodes. 129-132 - Lasse Määttä, Jukka Suhonen, Teemu Laukkarinen, Timo D. Hämäläinen, Marko Hännikäinen:
Program image dissemination protocol for low-energy multihop wireless sensor networks. 133-138 - Sandeep Pande, Fearghal Morgan, Seamus Cawley, Brian McGinley
EMBRACE-SysC for analysis of NoC-based Spiking Neural Network architectures. 139-145 - Kris Heyrman, Peter Veelaert:
Useful-state encoding: Network control with minimal redundancy. 146-149 - Ingo Rust, Tobias G. Noll:
A digit-set-interleaved radix-8 division/square root kernel for double-precision floating point. 150-153 - Waqar Hussain, Fabio Garzia, Jari Nurmi
Exploiting control management to accelerate Radix-4 FFT on a reconfigurable platform. 154-157 - Zulfiqar Ali, Ali Arshad, Umair Razzaq, Sawaira Sana, Abdul Haseeb Ahmed, Abdullah M. Harris:
Design and implementation of an OS-CFAR processor based on a new rank order filtering algorithm. 158-162 - Diandian Zhang, Han Zhang, Jerónimo Castrillón, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Bart Vanthournout:
Optimized communication architecture of MPSoCs with a hardware scheduler: A system view. 163-168 - Matthias Korb, Tobias G. Noll:
LDPC decoder area, timing, and energy models for early quantitative hardware cost estimates. 169-172 - Andreas Genser, Christian Bachmann
Power emulation based DVFS efficiency investigations for embedded systems. 173-178 - Samarjit Chakraborty
Multiprocessor system and software design for distributed control applications. 179
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