default search action
41st ISCA 2014: Minneapolis, MN, USA
- ACM/IEEE 41st International Symposium on Computer Architecture, ISCA 2014, Minneapolis, MN, USA, June 14-18, 2014. IEEE Computer Society 2014, ISBN 978-1-4799-4396-8
Session 1: Machines and Prototypes
- Brian Towles, J. P. Grossman, Brian Greskamp, David E. Shaw:
Unifying on-chip and inter-node switching within the Anton 2 network. 1-12 - Andrew Putnam
, Adrian M. Caulfield, Eric S. Chung, Derek Chiou, Kypros Constantinides, John Demme, Hadi Esmaeilzadeh, Jeremy Fowers, Gopi Prashanth Gopal, Jan Gray, Michael Haselman, Scott Hauck, Stephen Heil, Amir Hormati, Joo-Young Kim, Sitaram Lanka, James R. Larus, Eric Peterson, Simon Pope, Aaron Smith, Jason Thong, Phillip Yi Xiao, Doug Burger:
A reconfigurable fabric for accelerating large-scale datacenter services. 13-24 - Bhavya K. Daya, Chia-Hsin Owen Chen, Suvinay Subramanian
SCORPIO: A 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering. 25-36
Session 2A: Resilience
- Gaurang Upasani, Xavier Vera, Antonio González
Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery. 37-48 - Long Chen, Zhao Zhang:
MemGuard: A low cost and energy efficient design to support and enhance memory system reliability. 49-60 - Siva Kumar Sastry Hari, Radha Venkatagiri, Sarita V. Adve, Helia Naeimi:
GangES: Gang error simulation for hardware resiliency evaluation. 61-72 - Jack Wadden, Alexander Lyashevsky, Sudhanva Gurumurthi, Vilas Sridharan, Kevin Skadron
Real-world design and evaluation of compiler-managed GPU redundant multithreading. 73-84
Session 2B: Design Space Exploration
- Tianshi Chen, Qi Guo, Ke Tang, Olivier Temam, Zhiwei Xu, Zhi-Hua Zhou, Yunji Chen
ArchRanker: A ranking approach to design space exploration. 85-96 - Yakun Sophia Shao, Brandon Reagen, Gu-Yeon Wei, David M. Brooks:
Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures. 97-108 - Mario Badr, Natalie D. Enright Jerger
SynFull: Synthetic traffic models capturing cache coherent behaviour. 109-120 - Ashish Venkat, Dean M. Tullsen
Harnessing ISA diversity: Design of a heterogeneous-ISA chip multiprocessor. 121-132
Session 3A: Caches
- Andreas Sembrant, Erik Hagersten, David Black-Schaffer:
Navigating the cache hierarchy with a single lookup. 133-144 - Angelos Arelakis, Per Stenström:
SC2: A statistical compression cache scheme. 145-156 - Vivek Seshadri, Abhishek Bhowmick, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry:
The Dirty-Block Index. 157-168 - Lei Liu, Yong Li, Zehan Cui, Yungang Bao, Mingyu Chen, Chengyong Wu:
Going vertical in memory management: Handling multiplicity by multi-policy. 169-180
Session 3B: GPUs and Parallelism
- Marc S. Orr, Bradford M. Beckmann, Steven K. Reinhardt, David A. Wood:
Fine-grain task aggregation and coordination on GPUs. 181-192 - Ivan Tanasic, Isaac Gelado, Javier Cabezas, Alex Ramírez, Nacho Navarro, Mateo Valero
Enabling preemptive multiprogramming on GPUs. 193-204 - Dani Voitsechov, Yoav Etsion:
Single-graph multiple flows: Energy efficient design alternative for GPGPUs. 205-216 - Simone Campanoni, Kevin Brownell, Svilen Kanev, Timothy M. Jones
HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs. 217-228
Session 4: Emerging Technologies
- James E. Smith:
Efficient digital neurons for large scale cortical architectures. 229-240 - Karthik Swaminathan, Huichu Liu, Jack Sampson, Vijaykrishnan Narayanan:
An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs. 241-252 - Rangharajan Venkatesan, Shankar Ganesh Ramasubramanian, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan
STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies. 253-264
Session SA: NVRAM
- Steven Pelley, Peter M. Chen, Thomas F. Wenisch:
Memory persistency. 265-276 - Morteza Hoseinzadeh
Reducing access latency of MLC PCMs through line striping. 277-288 - Myoungsoo Jung, Wonil Choi, Shekhar Srikantaiah, Joonhyuk Yoo, Mahmut T. Kandemir:
HIOS: A host interface I/O scheduler for Solid State Disks. 289-300 - David Lo, Liqun Cheng, Rama Govindaraju, Luiz André Barroso, Christos Kozyrakis:
Towards energy proportionality for large-scale latency-critical workloads. 301-312 - Yanpei Liu, Stark C. Draper
SleepScale: Runtime joint speed scaling and sleep states management for power efficient data centers. 313-324 - Ming Liu, Tao Li:
Optimizing virtual machine consolidation performance on NUMA server architecture for cloud workloads. 325-336
Session 6A: DRAM
- Seongil O, Young Hoon Son, Nam Sung Kim, Jung Ho Ahn
Row-buffer decoupling: A case for low-latency DRAM microarchitecture. 337-348 - Tao Zhang, Ke Chen, Cong Xu, Guangyu Sun, Tao Wang, Yuan Xie:
Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation. 349-360 - Yoongu Kim, Ross Daly, Jeremie S. Kim, Chris Fallin, Ji-Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu:
Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors. 361-372
Session 6B: Circuits and Architecture
- Runjie Zhang, Ke Wang, Brett H. Meyer, Mircea R. Stan
Architecture implications of pads as a scarce resource. 373-384 - Shaoming Chen, Yue Hu, Ying Zhang, Lu Peng, Jesse Ardonne, Samuel Irving, Ashok Srivastava:
Increasing off-chip bandwidth in multi-core processors with switchable pins. 385-396 - Lei Jiang, Bo Zhao, Jun Yang, Youtao Zhang:
A low power and reliable charge pump design for Phase Change Memories. 397-408
Session 7A: Coherence and Replay
- Gwendolyn Voskuilen, T. N. Vijaykumar:
Fractal++: Closing the performance gap between fractal and conventional coherence. 409-420 - Xuehai Qian, Benjamín Sahelices
OmniOrder: Directory-based conflict serialization of transactions. 421-432 - Xuehai Qian, Benjamín Sahelices
Pacifier: Record and replay for relaxed-consistency multiprocessors with distributed directory protocol. 433-444 - Nima Honarmand, Josep Torrellas:
Replay debugging: Leveraging record and replay for program debugging. 445-456
Session 7B: Security/OOO Processors
- Jonathan Woodruff
The CHERI capability model: Revisiting RISC in an age of risk. 457-468 - Lluís Vilanova
CODOMs: Protecting software with Code-centric memory Domains. 469-480 - Arthur Perais
EOLE: Paving the way for an effective implementation of value prediction. 481-492 - Kenneth Czechowski, Victor W. Lee, Ed Grochowski, Ronny Ronen, Ronak Singhal, Richard W. Vuduc
Improving the energy efficiency of Big Cores. 493-504
Session 8: Accelerators
- Renée St. Amant, Amir Yazdanbakhsh
General-purpose code acceleration with limited-precision analog computation. 505-516 - Advait Madhavan, Timothy Sherwood
Race Logic: A hardware acceleration for dynamic programming algorithms. 517-528 - José-María Arnau, Joan-Manuel Parcerisa
Eliminating redundant fragment shader executions on a mobile GPU via hardware memoization. 529-540 - Yuhao Zhu, Vijay Janapa Reddi:
WebCore: Architectural support for mobile Web browsing. 541-552
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-14 20:48 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: