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ITC 2019: Washington, DC, USA
- IEEE International Test Conference, ITC 2019, Washington, DC, USA, November 9-15, 2019. IEEE 2019, ISBN 978-1-7281-4823-6
- Chuanhe Jay Shan, Ahmed Wahba, Li-C. Wang, Nik Sumikawa:
Deploying A Machine Learning Solution As A Surrogate. 1-10 - Anteneh Gebregiorgis, Mehdi Baradaran Tahoori:
Testing of Neuromorphic Circuits: Structural vs Functional. 1-10 - Domenic Forte
, Swarup Bhunia
IEEE International Symposium on Hardware Oriented Security and Trust (HOST): Past, Present, and Future. 1-4 - Ahmed M. Y. Ibrahim
DARS: An EDA Framework for Reliability and Functional Safety Management of System-on-Chips. 1-10 - Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Amr Abuellil, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran:
Breaking Analog Locking Techniques via Satisfiability Modulo Theories. 1-10 - Natalia Lylina, Ahmed Atteya, Pascal Raiola, Matthias Sauer, Bernd Becker
Security Compliance Analysis of Reconfigurable Scan Networks. 1-9 - Christos Papameletis, Vivek Chickermane, Brian Foutz, Sarthak Singhal, Krishna Chakravadhanula:
Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications. 1-6 - Wei Chu, Shi-Yu Huang:
Overall Strategy for Online Clock System Checking Supporting Heterogeneous Integration. 1-10 - Said Hamdioui, Moritz Fieback
Testing Computation-in-Memory Architectures Based on Emerging Memories. 1-10 - Sreeja Chowdhury, Fatemeh Ganji, Troy Bryant, Nima Maghari, Domenic Forte
Recycled Analog and Mixed Signal Chip Detection at Zero Cost Using LDO Degradation. 1-10 - Yu-Teng Nien
Methodology of Generating Timing-Slack-Based Cell-Aware Tests. 1-10 - Tao Chen, Degang Chen:
Built-in self-test and self-calibration for analog and mixed signal circuits. 1-8 - Huawei Li, Xiaowei Li
China Test Conference (CTC) - Extending the Global Test Forum to China. 1-4 - Wim Dobbelaere, Frederik Colle, Anthony Coyette, Ronny Vanhooren, Nektar Xama
Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs. 1-4 - Irith Pomeranz:
Iterative Test Generation for Gate-Exhaustive Faults to Cover the Sites of Undetectable Target Faults. 1-7 - Gerhard Schrom, Michael J. Hill
Efficiency Measurement Method for Fully Integrated Voltage Regulators used in 4th and 5th Generation Intel® Core™ Microprocessors. 1-6 - Kosuke Ikeda, Keith Schaub, Ira Leventhal, Yiorgos Makris
Subtle Anomaly Detection of Microscopic Probes using Deep learning based Image Completion. 1-3 - Nidish Vashistha, M. Tanjidur Rahman
Is Backside the New Backdoor in Modern SoCs?: Invited Paper. 1-10 - Magdy Abadir, Sohrab Aftabjahani:
An Overview of the International Microprocessor/ SoC Test, Security and Validation (MTV)Workshop. 1-2 - Andrea Floridia, Davide Piumatti, Annachiara Ruospo
A Decentralized Scheduler for On-line Self-test Routines in Multi-core Automotive System-on-Chips. 1-10 - Danielle Duvalsaint, Xiaoxiao Jin, Benjamin Niewenhuis, R. D. (Shawn) Blanton:
Characterization of Locked Combinational Circuits via ATPG. 1-10 - Zeye Liu, Qicheng Huang, Chenlei Fang, R. D. (Shawn) Blanton:
Improving Test Chip Design Efficiency via Machine Learning. 1-10 - Fangzhou Wang, Sandeep Gupta:
Multi-cell characterization: Developing robust cells and abstraction for Rapid Single Flux Quantum (RSFQ) Logic. 1-10 - Nilanjan Mukherjee, Jerzy Tyszer, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki:
Test Time and Area Optimized BrST Scheme for Automotive ICs. 1-10 - Moritz Fieback
Device-Aware Test: A New Test Approach Towards DPPB Level. 1-10 - Erik Larsson
IEEE Std. P1687.1: Translator and Protocol. 1-10 - Apik Zorian, Basim Shanyour, Milir Vaseekar:
Machine Learning-Based DFT Recommendation System for ATPG QOR. 1-7 - Zoran Stamenkovic
International Symposium on Design and Diagnostics of Electronic Circuits and Systems. 1-4 - Kiyotaka Ichiyama, Takashi Kusaka, Masahiro Ishida:
A Jitter Injection Module for Production Test of 52-Gbps PAM4 Signal Interfaces. 1-8 - Samvel K. Shoukourian, Yuri Shoukourian
Armenia: Communicating to World Community in Electronic Test and Design. 1-3 - Zhanwei Zhong, Haodong Zhu, Peiran Zhang, Tony Jun Huang, Krishnendu Chakrabarty
Structural Test and Functional Test for Digital Acoustofluidic Biochips. 1-10 - Stephen Sunter:
Efficient Analog Defect Simulation. 1-10 - Toshiyuki Omuro, Shigeo Nakamura Surname, Takashi Kimura, Kiyokawa Omuro:
A New Test Method for the Large Current Magnetic Sensors. 1-7 - Stefan Holst, Eric Schneider, Michael A. Kochte, Xiaoqing Wen, Hans-Joachim Wunderlich:
Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses. 1-10 - Szilárd Enyedi
IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR). 1-4 - Adam Duncan, Fahim Rahman, Andrew Lukefahr, Farimah Farahmandi, Mark M. Tehranipoor:
FPGA Bitstream Security: A Day in the Life. 1-10 - Arjun Chaudhuri, Mengyun Liu, Krishnendu Chakrabarty
Fault-Tolerant Neuromorphic Computing Systems. 1-10 - Chen He
Advanced Burn-In - An Optimized Product Stress and Test Flow for Automotive Microcontrollers. 1-6 - Stephan Eggersglüß, Said Hamdioui, Artur Jutman, Maria K. Michael, Jaan Raik, Matteo Sonza Reorda
IEEE European Test Symposium (ETS). 1-4 - Zheng Xu, Jacob Abraham:
Safety Design of a Convolutional Neural Network Accelerator with Error Localization and Correction. 1-10 - Atieh Lotfi, Saurabh Hukerikar, Keshav Balasubramanian, Paul Racunas, Nirmal R. Saxena, Richard Bramley, Yanxiang Huang:
Resiliency of automotive object detection networks on GPU architectures. 1-9 - Michiko Inoue, Xiaowei Li
Asian Test Symposium - Past, Present and Future -. 1-4 - Stephan Eggersglüß:
Towards Complete Fault Coverage by Test Point Insertion using Optimization-SAT Techniques. 1-8 - Tal Kogan, Yehonatan Abotbol:
Virtual Memory Structures Facilitating Memory BIST Insertion In Complex SoCs. 1-3 - Sujay Pandey, Sanya Gupta, Madhu Sudhan L., Suriya Natarajan, Arani Sinha, Abhijit Chatterjee:
Characterization of Library Cells for Open-circuit Defect Exposure: A Systematic Methodology. 1-10 - Jingchi Yang, David C. Keezer
A Framework for Design of Self-Repairing Digital Systems. 1-10 - Kelly Ockunzzi, Richard Grupp, Brion Keller, Mark Taylor, Sreekanth Pai, Greeshma Jayakumar:
Applications of Hierarchical Test. 1-6 - Teresa McLaurin, Rob Knoth:
The Challenges of Implementing an MBIST Interface: A Practical Application. 1-6 - Gabriele Boschi, Donato Luongo, Duccio Lazzarotti, Hanna Shaheen, Hayk T. Grigoryan, Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian:
Memory FIT Rate Mitigation Technique for Automotive SoCs. 1-6 - Mohammad Urf Maaz, Alexander Sprenger
A Hybrid Space Compactor for Adaptive X-Handling. 1-8 - Fei Su, Prashant Goteti, Min Zhang:
On Freedom from Interference in Mixed-Criticality Systems: A Causal Learning Approach. 1-10 - Irith Pomeranz:
Compaction of a Functional Broadside Test Set through the Compaction of a Functional Test Sequence without Sequential Fault Simulation. 1-7 - Jisuk Kim, Jinyub Lee, Sungjoo Yoo:
Machine Learning-Based Automatic Generation of eFuse Configuration in NAND Flash Chip. 1-9 - Luis D. Rojas, Kevin Hess, Christina Carter-Brown:
Effectively Using Machine Learning to Expedite System Level Test Failure Debug. 1-6 - Zhan Gao, Santosh Malagi, Min-Chun Hu, Joe Swenton, Rogier Baert, Jos Huisken
Application of Cell-Aware Test on an Advanced 3nm CMOS Technology Library. 1-6 - Magdy Abadir, Sohrab Aftabjahani:
An Overview of the International Verification and Security Workshop (IVSW). 1-2 - Andrew Yi-Ann Huang, Katherine Shu-Min Li, Cheng-Yen Tsai, Ken Chau-Cheung Cheng
TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning. 1-6 - Tung-Che Liang, Krishnendu Chakrabarty
Programmable Daisychaining of Microelectrodes for IP Protection in MEDA Biochips. 1-10 - Yervant Zorian, Vladimir Hahanov
17th IEEE East-West Design and Test Symposium. 1-4 - Gaurav Rajavendra Reddy, Mohammad-Mahdi Bidmeshki, Yiorgos Makris
VIPER: A Versatile and Intuitive Pattern GenERator for Early Design Space Exploration. 1-7 - Nusrat Farzana, Fahim Rahman, Mark M. Tehranipoor, Farimah Farahmandi:
SoC Security Verification using Property Checking. 1-10 - Seyed Nima Mozaffari, Bonita Bhaskaran, Kaushik Narayanun, Ayub Abdollahian, Vinod Pagalone, Shantanu Sarangi, Jonathon E. Colburn
An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test. 1-10 - Mengyun Liu, Xin Li, Krishnendu Chakrabarty
Knowledge Transfer in Board-Level Functional Fault Identification using Domain Adaptation. 1-10 - Adit D. Singh:
An Adaptive Approach to Minimize System Level Tests Targeting Low Voltage DVFS Failures. 1-10 - Hao Chen, Mincent Lee, Liang-Yen Chen, Min-Jer Wang:
High Quality Test Methodology for Highly Reliable Devices. 1-6 - Innocent Okwudili Agbo, Mottaqiallah Taouil, Said Hamdioui:
Reliability Modeling and Mitigation for Embedded Memories. 1-10 - Zhanwei Zhong, Krishnendu Chakrabarty
Fault Recovery in Micro-Electrode-Dot-Array Digital Microfluidic Biochips Using an IJTAG NetworkBehaviors. 1-10 - Kuen-Jong Lee, Shi-Yu Huang, Huawei Li, Tomoo Inoue, Yervant Zorian:
International Test Conference in Asia (ITC-Asia) - Bridging ITC and Test Community in Asia. 1-4 - Cheng-Hsien Shen, Aaron C.-W. Liang, Charles C.-H. Hsu, Charles H.-P. Wen
FAE: Autoencoder-Based Failure Binning of RTL Designs for Verification and Debugging. 1-10 - Arjun Chaudhuri, Bonan Yan, Yiran Chen, Krishnendu Chakrabarty
Hardware Fault Tolerance for Binary RRAM Crossbars. 1-10 - Yi He
Time-Slicing Soft Error Resilience in Microprocessors for Reliable and Energy-Efficient Execution. 1-10 - Aleksa Damljanovic, Artur Jutman, Michele Portolan
Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL. 1-8
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