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ITC 2015: Anaheim, CA, USA
- 2015 IEEE International Test Conference, ITC 2015, Anaheim, CA, USA, October 6-8, 2015. IEEE 2015, ISBN 978-1-4673-6578-9
- Karim Arabi:
Brain-inspired computing. 7 - Andrew B. Kahng:
Modeling the future of semiconductors (and test!). 8 - William R. Bottoms:
Can we ensure reliability in the era of heterogeneous integration? 9 - R. D. (Shawn) Blanton, Benjamin Niewenhuis, Zeye (Dexter) Liu:
Design reflection for optimal test-chip implementation. 1-10 - Zipeng Li, Sandeep Kumar Goel, Frank Lee, Krishnendu Chakrabarty
:
Efficient observation-point insertion for diagnosability enhancement in digital circuits. 1-10 - Sarmad Tanwir, Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan:
Information-theoretic and statistical methods of failure log selection for improved diagnosis. 1-10 - Xijiang Lin, Sudhakar M. Reddy:
On generating high quality tests based on cell functions. 1-9 - Cesar Acero, Derek Feltham, Friedrich Hapke, Elham K. Moghaddam, Nilanjan Mukherjee, Vidya Neerkundar, Marek Patyra, Janusz Rajski, Jerzy Tyszer, Justyna Zawada:
Embedded deterministic test points for compact cell-aware tests. 1-8 - Takahiro J. Yamaguchi, Katsuhiko Degawa, Masayuki Kawabata, Masahiro Ishida, Koichiro Uekusa, Mani Soma:
A new method for measuring alias-free aperture jitter in an ADC output. 1-6 - Haralampos-G. D. Stratigopoulos, Manuel J. Barragán, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal:
Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times. 1-7 - Yu Liu, Georgios Volanis, Ke Huang, Yiorgos Makris
Concurrent hardware Trojan detection in wireless cryptographic ICs. 1-8 - Nicole Fern, Shrikant Kulkarni, Kwang-Ting (Tim) Cheng
Hardware Trojans hidden in RTL don't cares - Automated insertion and prevention methodologies. 1-8 - Abhishek Basak, Fengchao Zhang, Swarup Bhunia
PiRA: IC authentication utilizing intrinsic variations in pin resistance. 1-8 - Sergej Deutsch, Krishnendu Chakrabarty
Contactless pre-bond TSV fault diagnosis using duty-cycle detectors and ring oscillators. 1-10 - Rashid Rashidzadeh, Esrafil Jedari, Tareq Muhammad Supon, Vladimir Mashkovtsev:
A DLL-based test solution for through silicon via (TSV) in 3D-stacked ICs. 1-9 - Fan Lin, Chun-Kai Hsu, Kwang-Ting Cheng
AdaTest: An efficient statistical test framework for test escape screening. 1-8 - Hideo Okawara:
eRNA: Refining of reconstructed digital waveform. 1-10 - Stephen McGinty, Daniel Hadad, Chris Nappi, Brian Caquelin:
Developing a modern platform for test engineering - Introducing the origen semiconductor developer's kit. 1-10 - Masahiro Ishida, Kiyotaka Ichiyama:
An ATE system for testing 2.4-GHz RF digital communication devices with QAM signal interfaces. 1-9 - Stephen K. Sunter, Jean-Francois Cote, Jeff Rearick:
Streaming fast access to ADCs and DACs for mixed-signal ATPG. 1-8 - Sebastian Siatkowski, Chia-Ling Chang, Li-C. Wang
Generalization of an outlier model into a "global" perspective. 1-10 - David Lin, Eshan Singh, Clark W. Barrett
A structured approach to post-silicon validation and debug using symbolic quick error detection. 1-10 - Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jedrzej Solecki, Jerzy Tyszer:
A deterministic BIST scheme based on EDT-compressed test patterns. 1-8 - Bruce Querbach, Tan Peter Yanyang, Lovelace Van, David Blankenbeckler, Rahul Khanna, Sudeep Puligundla, Patrick Chiang:
Platform IO and system memory test using L3 cache based test (CBT) and parallel execution of CPGC Intel BIST engine. 1-10 - Xue Ming, Koelz Johann, Lee Chow York, Lee Kwan Wee, Shi Zhi Min:
Electrical package defect testing for volume production. 1-9 - An-Jim Long, David Tsai, Kent Lien, Steve Hsu:
Tolerance analysis of fixture fabrication, from drilling holes to pointing accuracy. 1-4 - Adrian I. Voinea, Stefan Kampfer:
Rapid prototyping and test before silicon of integrated pressure sensors. 1-9 - Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho
A general testing method for digital microfluidic biochips under physical constraints. 1-8 - Shoichi Iizuka, Yutaka Masuda, Masanori Hashimoto
Stochastic timing error rate estimation under process and temporal variations. 1-10 - Li Jiang, Pu Pang, Naifeng Jing, Sung Kyu Lim
On diagnosable and tunable 3D clock network design for lifetime reliability enhancement. 1-10 - Meng-Ting Tsai, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng:
Monitoring the delay of long interconnects via distributed TDC. 1-9 - Tassanee Payakapan, Senwen Kan, Ken Pham, Kathy Yang, Jean-Francois Cote, Martin Keim, Jennifer Dworak:
A case study: Leverage IEEE 1687 based method to automate modeling, verification, and test access for embedded instruments in a server processor. 1-10 - Rene Krenz-Baath, Farrokh Ghani Zadegan
Access time minimization in IEEE 1687 networks. 1-10 - Hao-Yu Yang, Rei-Fu Huang, Chin-Lung Su, Kuan-Hong Lin, Hang-Kaung Shu, Chi-Wei Peng, Mango Chia-Tso Chao:
Testing methods for quaternary content addressable memory using charge-sharing sensing scheme. 1-10 - Mojtaba Ebrahimi, Mehdi Baradaran Tahoori:
Stepped parity: A low-cost multiple bit upset detection technique. 1-8 - Kelly A. Ockunzzi, Michael R. Ouellette, Kevin W. Gorman:
Optimizing delay tests at the memory boundary. 1-9 - Erik Jan Marinissen
Automated testing of bare die-to-die stacks. 1-10 - Kevin Tiernan, Snehamay Sinha, Lily Pang, Robert Williams, Ken Delling:
How many probes is enough? A low cost method for probe card depopulation with low risk. 1-5 - Jae Woong Jeong, Jennifer Kitchen, Sule Ozev:
A self-compensating built-in self-test solution for RF phased array mismatch. 1-9 - Yichuan Lu, Kiruba S. Subramani, He Huang, Nathan Kupp, Ke Huang, Yiorgos Makris
A comparative study of one-shot statistical calibration methods for analog / RF ICs. 1-10 - Sriram Karunagaran, Karuna P. Sahoo, Masahiro Fujita:
Hardware in loop testing of an insulin pump. 1-8 - Song Yao, Xiaoming Chen, Jie Zhang, Qiaoyi Liu, Jia Wang, Qiang Xu
FASTrust: Feature analysis for third-party IP trust verification. 1-10 - Jerry Backer, David Hély
Secure design-for-debug for Systems-on-Chip. 1-8 - Nektarios Georgios Tsoutsos, Michail Maniatakos
Extending residue-based fault tolerance to encrypted computation. 1-10 - Fotios Vartziotis
Test-access-mechanism optimization for multi-Vdd SoCs. 1-10 - Sergej Deutsch, Krishnendu Chakrabarty
Test and debug solutions for 3D-stacked integrated circuits. 1-10 - Fabian Oboril, Mehdi Baradaran Tahoori:
Cross-layer approaches for an aging-aware design of nanoscale microprocessors: Dissertation summary: IEEE TTTC E.J. McCluskey doctoral thesis award competition finalist. 1-10 - Li Jiang, Qiang Xu
Yield and reliability enhancement for 3D ICs: Dissertation summary: IEEE TTTC E.J. McCluskey doctoral thesis award competition finalist. 1-11
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