default search action
ERSA 2005: Las Vegas, Nevada, USA
- Toomas P. Plaks:
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2005, Las Vegas, Nevada, USA, June 27-30, 2005. CSREA Press 2005, ISBN 1-932415-74-2
IMCSE'05 Keynote
- Robert P. Colwell:
Where Intel's Microprocessor Architecture is Going. ERSA 2005: 3-6
ERSA'05 Keynote
- Donald W. Bouldin:
Enabling Killer Applications of Reconfigurable Systems: ERSA Keynote and Introduction. ERSA 2005: 7-16
Invited Talks
- Gerard J. M. Smit, Gerard K. Rauwerda:
Reconfigurable Architectures for Adaptable Mobile Systems. ERSA 2005: 17-25 - Steven A. Guccione:
Microprocessors: The New LUT. ERSA 2005: 26-25 - Charlé R. Rupp:
Reconfigurable Instruction Set Computing for Embedded Processing. ERSA 2005: 36 - Dror E. Maydan:
Configurable Processors and the Evolution of System-on-Chip Design. ERSA 2005: 37 - Chris Sullivan:
What's the Future of C-Based Programmable SoC design? ERSA 2005: 38-40
Energy-Efficient Reconfigurable Mobile Systems
- Jing Ma, Xinming Huang:
A SoPC Architecture of MIMO Sphere Decoder for Mobile Communications. ERSA 2005: 41-47 - Kimmo U. Järvinen, Matti Tommiska, Jorma Skyttä:
A Compact MD5 and SHA-1 Co-Implementation Utilizing Algorithm Similarities. ERSA 2005: 48-54 - Jingzhao Ou, Viktor K. Prasanna:
Rapid Arithmetic Level Simulation Based Energy Estimation for Hardware/Software Co-Design Using FPGAs. ERSA 2005: 55-61 - Gerard K. Rauwerda, Gerard J. M. Smit, Werner Brugger:
Implementing an Adaptive Viterbi Algorithm in Coarse-Grained Reconfigurable Hardware. ERSA 2005: 62-70
Operating System Approaches for Reconfigurable Hardware
- Fei Wang, Jack S. N. Jean, Shuxia Sun:
Aspect Ratio Effects on Reconfigurable Computing. ERSA 2005: 71-77 - Frank Hannig, Jürgen Teich:
Output Serialization for FPGA-based and Coarse-grained Processor Arrays. ERSA 2005: 78-84 - Stefan Ihmor, Florian Dittmann:
Optimizing Interface Implementation Costs Using Runtime Reconfigurable Systems. ERSA 2005: 85-91 - Jan van der Veen, Sándor P. Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich:
Defragmenting the Module Layout of a Partially Reconfigurable Device. ERSA 2005: 92-104
Reconfigurable Supercomputing
- Brandon Thurmon, James M. McCollum, Gregory D. Peterson, Chris D. Cox, Nagiza F. Samatova, Gary S. Sayler, Michael L. Simpson:
Accelerating Exact Stochastic Simulation Using Reconfigurable Computing. ERSA 2005: 105-111 - Sanjay V. Rajopadhye, Kolin Paul:
A 1.5-D Architecture for Back-Propagation Training. ERSA 2005: 112-118 - Ronald Scrofano, Ling Zhuo, Viktor K. Prasanna:
Area-Efficient Evaluation of a Class of Arithmetic Expressions Using Deeply Pipelined Floating-Point Cores. ERSA 2005: 119-128 - Chen Chang, John Wawrzynek, Pierre-Yves Droz, Robert W. Brodersen:
The Design And Application Of A High-End Reconfigurable Computing System. ERSA 2005: 129-136 - Ronald Scrofano, Gokul Govindu, Viktor K. Prasanna:
A Library of Parameterizable Floating-Point Cores for FPGAs and Their Application to Scientific Computing. ERSA 2005: 137-148
Reconfigurable System-on-Chip & HW/SW Codesign
- Wayne Luk, Sherif Yusuf, Morris Sloman, Geoffrey Brown, Emil C. Lupu, Naranker Dulay:
A Combined Hardware-Software Architecture for Network Flow. ERSA 2005: 149-155 - Xuejun Liang, Jeffrey S. Vetter, Melissa C. Smith, Arthur S. Bland:
Balancing FPGA Resource Utilities. ERSA 2005: 156-162 - Sungjoon Jung, Tag Gon Kim:
An Operation and Interconnection Sharing Algorithm for Partially Reconfigurable Architectures. ERSA 2005: 163-174
Runtime Resource Management
- Ryan A. DeVille, Ian A. Troxel, Alan D. George:
Performance Monitoring for Run-time Management of Reconfigurable Devices. ERSA 2005: 175-181 - Zexin Pan, Juanjo Noguera, B. Earl Wells:
Improved Microarchitecture Support for Dynamic Task Scheduling on Reconfigurable Architectures. ERSA 2005: 182-188 - Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo:
Flexible Core Reallocation for Virtex II Structures. ERSA 2005: 189-195 - Abdel Ejnioui, Ronald F. DeMara:
Area Reclamation Strategies and Metrics for SRAM-Based Reconfigurable Devices. ERSA 2005: 196-202 - Shaoyu Liu, Gregory D. Peterson, Seong G. Kong:
A Hardware Implementation of a Dynamically Adjustable Block-based Neural Network. ERSA 2005: 203-210
Adaptive Architectures & Applications
- Antonio Gentile, Salvatore Segreto, Filippo Sorbello, Giorgio Vassallo, Salvatore Vitabile, Vincenzo Vullo:
CliffoSor, an Innovative FPGA-based Architecture for Geometric Algebra. ERSA 2005: 211-217 - Wim J. C. Melis, Kieron Turkington, Alexander Whitton, Wayne Luk, Peter Y. K. Cheung, Paul Metzgen:
Cell Based Motion Estimators for Reconfigurable Platforms. ERSA 2005: 218-224 - Nobuo Nakai, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe:
Reconfigurable 1-Bit Processor Array with Reduced Wirng Area. ERSA 2005: 225-234
Discussion, Short Papers
- Otsebele E. Nare, Charles T. Johnson-Bey:
A Reconfigurable Antialiasing Filter Design Using Multi-Abstraction Design Exploration Approach. ERSA 2005: 235-238 - Wenrui Gong, Yan Meng, Gang Wang, Ryan Kastner, Timothy Sherwood:
Data Partitioning and Optimizations for Reconfigurable Architectures. ERSA 2005: 239-242 - Kenneth B. Kent, Zhao Yong, Jacqueline E. Rice, Troy Ronda:
Instance-Specific Versus Parameter-Specific Circuit Generation. ERSA 2005: 243-246 - Ali Akoglu, Sethuraman Panchanathan:
Application Specific Reconfigurable Architecture Design. ERSA 2005: 247-250 - Heng Tan, Ronald F. DeMara:
A Device-Controlled Dynamic Configuration Framework Supporting Heterogeneous Resource Management. ERSA 2005: 251-254 - Janak Porwal, Sachin B. Patkar:
Algorithms For Scheduling Of Data Transfer Across FPGAs In A Grid. ERSA 2005: 255-260
Poster Papers
- Youngsoo Kim, Dongsoo Kim, Daesun Park, Sungjo Kim:
A Non-LIinear Function Generator Using BRM. ERSA 2005: 261-262 - Caaliph Andriamisaina, Catherine Dezan, Christophe Jégo, Bernard Pottier:
Abstract Synthesis of Turbo Decoder Elements onto Reconfigurable Circuit. ERSA 2005: 263-266
Late Papers
- Chuan He, Wei Zhao, Mi Lu:
FPGA-Based High-Order Finite Difference Algorithm for 2D Acoustic Wave Propagation Problems. ERSA 2005: 267-273 - Zain-ul-Abdin, Bertil Svensson:
Compiling Stream-Language Applications to a Reconfigurable Array Processor. ERSA 2005: 274-275 - Yuanqing Guo, Cornelis Hoede, Gerard J. M. Smit:
A Multi-Pattern Scheduling Algorithm. ERSA 2005: 276-
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-15 19:20 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: