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15th DDECS 2012: Tallinn, Estonia
- Jaan Raik, Viera Stopjaková, Heinrich Theodor Vierhaus, Witold A. Pleskacz, Raimund Ubar, Helena Kruus, Maksim Jenihhin:
IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2012, Tallinn, Estonia, April 18-20, 2012. IEEE 2012, ISBN 978-1-4673-1187-8
Keynote Talks
- Matteo Sonza Reorda
:
On-line test of embedded systems: Which role for functional test? 1 - Said Hamdioui:
TSV based 3D stacked ICs: Opportunities and challenges. 2 - Andrzej Pfitzner:
Vertical Slit Transistor based Integrated Circuits (VeSTICs). 3
Embedded Tutorials
- Uwe Knöchel:
3D integration: Opportunities, design challenges and approaches. 4 - Eckhard Grass, Milos Krstic, Xin Fan, Steffen Zeidler:
Asynchronous circuit design: From basics to practical applications. 5 - Georg Hofferek:
Automated synthesis and design-error repair of systems. 6 - Erik Larsson, Konstantin Sibin:
Fault management in an IEEE P1687 (IJTAG) environment. 7
Poster Session I
- Vladimir Petrovic, Marko Ilic, Günter Schoof, Zoran Stamenkovic
Design methodology for fault tolerant ASICs. 8-11 - Hagen Sämrow, Claas Cornelius, Philipp Gorski, Andreas Tockhorn, Dirk Timmermann
Selective redundancy to improve reliability and to slow down delay degradation due to gate oxide breakdown. 12-15 - Arkadiusz Bukowiec, Marian Adamski:
Synthesis of Petri nets into FPGA with operation flexible memories. 16-21 - Martin Rozkovec
An evaluation of the application dependent FPGA test method. 22-25 - Krzysztof Marcinek
AGATE - towards designing a low-power chip multithreading processor for mobile software defined radio systems. 26-29 - Petr Fiser, Jan Schmidt:
Improving the iterative power of resynthesis. 30-33 - Richard Ruzicka, Václav Simek
NAND/NOR gate polymorphism in low temperature environment. 34-37 - Lukás Nagy
Current sensing completion detection in dual-rail asynchronous systems. 38-41 - M. H. Haghbayan, Saeed Safari
Power constraint testing for multi-clock domain SoCs using concurrent hybrid BIST. 42-45 - Abdelmajid Bouajila, Abdallah Lakhtel, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf:
A low-overhead monitoring ring interconnect for MPSoC parameter optimization. 46-49
Processor Architectures
- Alexander Wold, Dirk Koch, Jim Tørresen:
Design techniques for increasing performance and resource utilization of reconfigurable soft CPUs. 50-55 - George Kornaros
An automated infrastructure for real-time monitoring of multi-core Systems-on-Chip. 56-61 - Jaroslav Sykora, Lukas Kohout, Roman Bartosinski, Leos Kafka, Martin Danek
The architecture and the technology characterization of an FPGA-based customizable Application-Specific Vector Processor. 62-67
Analog and RF Desing
- Krzysztof Siwiec
LC-VCO design automation tool for nanometer CMOS technology. 68-73 - Mohamed Atef
A gigabit fully integrated plastic optical fiber receiver for a RC-LED source. 74-78 - Hsuan-Ling Kao
A low phase noise Ka-band voltage controlled oscillator using 0.15 µm GaAs pHEMT technology. 79-82
NoC Simulation and Test
- Haoyuan Ying, Ashok Jaiswal, Mohamed A. Abd El-Ghany
A simulation framework for 3-dimension Networks-on-chip with different vertical channel density configurations. 83-88 - Liang Guang, Ethiopia Nigussie, Juha Plosila
HLS-DoNoC: High-level simulator for dynamically organizational NoCs. 89-94 - Jaan Raik
Low-area boundary BIST architecture for mesh-like network-on-chip. 95-100
Analog, RF Design and Test
- Péter Földesy, Domonkos Gergelyi, Csaba Fuzy, Gergely Károlyi:
Test and configuration architecture of a sub-THz CMOS detector array. 101-104 - Ralph Görgen, Jan-Hendrik Oetjens, Wolfgang Nebel:
Automatic integration of hardware descriptions into system-level models. 105-110 - Maksim Gorev, Vadim Pesonen, Peeter Ellervee
Multisine signal generation method for a bioimpedance measurement device. 111-114
Fault Tolerance
- Varadan Savulimedu Veeravalli, Andreas Steininger
Radiation-tolerant combinational gates - an implementation based comparison. 115-120 - Josef Strnadel
Monitoring-driven HW/SW interrupt overload prevention for embedded real-time systems. 121-126 - Vladimir Pasca, Saif-Ur Rehman, Lorena Anghel
Efficient link-level error resilience in 3D NoCs. 127-132
Security
- Hans G. Kerkhoff, Yong Zhao:
The design of dependable flexible multi-sensory System-on-Chips for security applications. 133-138 - Armin Krieg
System side-channel leakage emulation for HW/SW security coverification of MPSoCs. 139-144 - Knut Wold, Slobodan Petrovic:
Security properties of oscillator rings in true random number generators. 145-150
Short Papers I
- Tomas Napravnik, Vlastimil Kote, Vladimir Molata, Jiri Jakovenko
Differential evolutionary optimization algorithm applied to ESD MOSFET model fitting problem. 155-158 - Xuelian Liu, Aamir Zia, Mitchell R. LeRoy, Srikumar Raman, Ryan Clarke, Russell P. Kraft, John F. McDonald:
A three-dimensional DRAM using floating body cell in FDSOI devices. 159-162 - Ahmed A. El Badry, Mohamed A. Abd El-Ghany
CDMA technique for Network-on-Chip. 163-166
Short Papers II
- Gábor Gyepes, Daniel Arbet
Application of IDDT test towards increasing SRAM reliability in nanometer technologies. 167-170 - Jakub Korczyc, Andrzej Krasniewski
Evaluation of susceptibility of FPGA-based circuits to fault injection attacks based on clock glitching. 171-174 - Matej Hlatký, Valter Martinek, Elena Gramatová:
D&T Presenter - electronic interactive system for design and test education. 175-178 - Rouhollah Feghhi, Sasan Naseh:
A 1V, low power, high-gain, 3 - 11 GHz double-balanced CMOS sub-harmonic mixer. 179-182
Poster Session II
- Martin Kohlík, Hana Kubátová:
Reduction of complex safety models based on Markov chains. 183-186 - Emad Samuel Malki Ebeid
Generation of SystemC/TLM code from UML/MARTE sequence diagrams for verification. 187-190 - Xiang Zheng, Ming Liu, Hong Chen, Huamin Cao, Cong Wang, Zhiqiang Gao:
A 512 kb SRAM in 65nm CMOS with divided bitline and novel two-stage sensing technique. 191-192 - Daniel Arbet
OBIST strategy versus parametric test - Efficiency in covering catastrophic faults in active analog filters. 193-194 - Martin Pospisilik, Milan Adamek:
Optimised Power Supply Unit Design. 195-196 - Jan Pospisil, Martin Novotný
Lightweight cipher resistivity against brute-force attack: Analysis of PRESENT. 197-198 - Dominik Macko
VHDLVisualizer: HDL model visualization with simulation-based verification. 199-200 - Martin Gag, Tim Wegner, Ansgar Waschki, Dirk Timmermann
Temperature and on-chip crosstalk measurement using ring oscillators in FPGA. 201-204 - Martin Wirnshofer, Leonhard Heiß, Anil Narayan Kakade, Nasim Pour Aryan, Georg Georgakos, Doris Schmitt-Landsiedel:
Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit. 205-208 - Parisa Kabiri, Zainalabedin Navabi:
Effective RT-level software-based self-testing of embedded processor cores. 209-212
ASIC/FPGA Design
- Liberis Voudouris, Spiridon Nikolaidis
High speed FPGA implementation of hough transform for real-time applications. 213-218 - Ronald Spilka, Gerald Hilber, Andreas Rauchenecker, Dominik Gruber, Michael Sams, Timm Ostermann:
Generation of non-overlapping clock signals without using a feedback loop. 219-223 - Taskin Koçak, Preeti Patil:
Design and implementation of high-performance high-valency ling adders. 224-229
Test Generation and Fault Detection
- Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler
A new SAT-based ATPG for generating highly compacted test sets. 230-235 - Raimund Ubar
Multiple stuck-at-fault detection theorem. 236-241 - Roland Dobai, Marcel Baláz:
Genetic method for compressed skewed-load delay test generation. 242-247
Poster Session III
- Chih-Ping Cheng, Jen-Chieh Liu, Kuo-Hsing Cheng:
Auto-calibration techniques in built-in jitter measurement circuit. 248-249 - Jacek Gradzki:
Low power balun Design for 1.575 GHz in 90 nm CMOS rechnology. 250-253 - Gürkan Uygur, Sebastian Sattler:
Digital-driven formal analog verification for asynchronously feed-backed circuitries. 254-257 - Thilo Vörtler, Steffen Rülke, Petra Hofstedt:
Bounded model checking of Contiki applications. 258-261 - Efi Arvaniti, Yiorgos Tsiatouhas
Low power scan by partitioning and scan hold. 262-265 - Hamid Mushtaq, Zaid Al-Ars, Koen Bertels:
A user-level library for fault tolerance on shared memory multicore systems. 266-269 - Yi-Hsiang Juan, Ching-Hsing Luo, Hong-Yi Huang:
A low voltage sigma delta modulator for temperature sensor. 270-273 - Saber Izadpanah Tous
Developing a new phase noise estimation technique based on time varying model. 274-277 - Pavol Korcek, Martin Zádník:
Lightweight benchmarking of platforms for network traffic processing. 278-283 - Ilias Pappas, Stilianos Siskos, Alkis A. Hatzopoulos
A new analog output buffer for data driver of active matrix displays using low-temperature polycrystalline silicon thin-film transistors. 284-287
On-line Test and Self-Repair
- Tobias Koal, Markus Ulbricht, Heinrich Theodor Vierhaus:
Combining on-line fault detection and logic self repair. 288-293 - Ping-Liang Lai, Der-Chen Huang:
Online self-checking and correction for crosstalk-induced timing errors on VLSI interconnects. 294-299 - Martin Chloupek, Ondrej Novák, Jiri Jenícek:
On test time reduction using pattern overlapping, broadcasting and on-chip decompression. 300-305
Test and Reliability of Microprocessors
- Paolo Bernardi
A SBST strategy to test microprocessors' Branch Target Buffer. 306-311 - Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus:
An adaptive self-test routine for in-field diagnosis of permanent faults in simple RISC cores. 312-317 - Ali Azarpeyvand
CIVA: Custom instruction vulnerability analysis framework. 318-323
Design Verification
- Mehdi Dehbashi, Görschwin Fey
Automated debugging from pre-silicon to post-silicon. 324-329 - Giuseppe Di Guglielmo, Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli
On the use of assertions for embedded-software dynamic verification. 330-335 - Martin Straka, Lukas Miculka, Jan Kastil
Test platform for fault tolerant systems design properties verification. 336-341
Reliability Challenges in Nano-Scale Technology
- Behzad Mesgarzadeh, Ingemar Söderquist, Atila Alvandpour:
Reliability challenges in avionics due to silicon aging. 342-347 - Seyab Khan, Said Hamdioui, Halil Kukner, Praveen Raghavan, Francky Catthoor:
BTI impact on logical gates in nano-scale CMOS technology. 348-353 - Arthur Ceratti, Thiago Copetti, Letícia Maria Bolzani Poehls, Fabian Vargas:
On-chip aging sensor to monitor NBTI effect in nano-scale SRAM. 354-359
Physical Design
- Vladimir M. Milovanovic, Horst Zimmermann
Complementary edge alignment and digital output signal speed-up CMOS positive feedback latches. 360-365 - Ahmed Naif M. Alahmadi
Reconfigurable time interval measurement circuit incorporating a programmable gain time difference amplifier. 366-371
Industrial Papers
- Andreas Mauderer, Marvin Freier, Jan-Hendrik Oetjens, Wolfgang Rosenstiel:
Efficient digital design for automotive mixed-signal ASICs using simulink. 372-377 - Gordon Russell, Frank P. Burns, Alex Yakovlev
VARMA - VARiability modelling and analysis tool. 378-383
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