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Richard Ruzicka
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2020 – today
- 2023
- [c35]Richard Ruzicka, Václav Simek, Jan Nevoral:
Polymorphic RTL Computational Elements. DSD 2023: 523-530 - 2022
- [c34]Richard Ruzicka, Václav Simek:
Technology Mapping for PAIG Optimised Polymorphic Circuits. DSD 2022: 801-808 - 2020
- [c33]Adam Crha, Václav Simek, Richard Ruzicka:
KL-cuts influence on optimization of polymorphic circuits based on PAIG rewriting. DDECS 2020: 1-6 - [c32]Jan Nevoral, Václav Simek, Richard Ruzicka:
Power Consumption Analysis of New Generation of Polymorphic Gates. DDECS 2020: 1-6
2010 – 2019
- 2019
- [c31]Jan Nevoral, Václav Simek, Richard Ruzicka:
PoLibSi: Path Towards Intrinsically Reconfigurable Components. DSD 2019: 328-334 - [c30]Adam Crha, Václav Simek, Richard Ruzicka:
PAIG Rewriting: The Way to Scalable Multifunctional Digital Circuits Synthesis. DSD 2019: 335-342 - 2018
- [c29]Jan Nevoral, Richard Ruzicka, Václav Simek:
From Ambipolarity to Multifunctionality: Novel Library of Polymorphic Gates Using Double-Gate FETs. DSD 2018: 657-664 - [c28]Adam Crha, Václav Simek, Richard Ruzicka:
Towards novel format for representation of polymorphic circuits. DTIS 2018: 1-2 - [c27]Jan Nevoral, Richard Ruzicka, Václav Simek:
CMOS Gates with Second Function. ISVLSI 2018: 82-87 - [c26]Jan Nevoral, Richard Ruzicka:
Efficient Implementation of Bi-Functional RTL Components - Case Study. NGCAS 2018: 25-28 - 2017
- [c25]Adam Crha, Richard Ruzicka, Václav Simek:
Synthesis tool for design of complex polymorphic circuits. DTIS 2017: 1-6 - [c24]Jan Nevoral, Václav Simek, Richard Ruzicka:
Compact library of efficient polymorphic gates based on ambipolar transistors. DTIS 2017: 1-6 - 2016
- [c23]Richard Ruzicka, Radek Tesar:
Lets move polymorphism downwards: On the multifunctional logic based on ambipolar behaviour of semiconductor devices. DTIS 2016: 1-5 - [c22]Václav Simek, Radek Tesar, Richard Ruzicka, Adam Crha:
Modelling and physical implementation of ambipolar components based on organic materials. ICM 2016: 341-344 - [c21]Jan Nevoral, Richard Ruzicka, Vojtech Mrazek:
Evolutionary design of polymorphic gates using ambipolar transistors. SSCI 2016: 1-8 - 2015
- [c20]Václav Simek, Richard Ruzicka, Adam Crha:
Toward efficient synthesis method of multifunctional logic circuits. ICM 2015: 21-24 - [c19]Adam Crha, Richard Ruzicka, Václav Simek:
Synthesis Methodology of Polymorphic Circuits Using Polymorphic NAND/NOR Gates. UKSim 2015: 612-617 - 2014
- [c18]Václav Simek, Richard Ruzicka, Adam Crha, Radek Tesar:
Implementation of a Cellular Automaton with Globally Switchable Rules. ACRI 2014: 378-387 - [c17]Václav Simek, Richard Ruzicka:
Reconfigurable Platform with Polymorphic Digital Gates and Partial Reconfiguration Feature. EMS 2014: 501-506 - [c16]Radek Tesar, Richard Ruzicka, Václav Simek:
Resistant Gates for Polymorphic Electronics. EMS 2014: 513-518 - 2013
- [j1]Lukás Sekanina, Richard Ruzicka, Zdenek Vasícek, Václav Simek, Petr Hanácek:
Implementing A Unique Chip Id On A Reconfigurable Polymorphic Circuit. Inf. Technol. Control. 42(1): 7-14 (2013) - [e1]Lukás Sekanina, Görschwin Fey, Jaan Raik, Snorre Aunet, Richard Ruzicka:
16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013. IEEE Computer Society 2013, ISBN 978-1-4673-6135-4 [contents] - 2012
- [c15]Richard Ruzicka, Václav Simek:
NAND/NOR gate polymorphism in low temperature environment. DDECS 2012: 34-37 - 2011
- [c14]Richard Ruzicka, Václav Simek, Lukás Sekanina:
Behavior of CMOS polymorphic circuits in high temperature environment. DDECS 2011: 447-452 - [c13]Richard Ruzicka, Václav Simek:
Chip Temperature Selfregulation for Digital Circuits Using Polymorphic Electronics Principles. DSD 2011: 205-212 - 2010
- [c12]Václav Simek, Richard Ruzicka, Lukás Sekanina:
On analysis of fabricated polymorphic circuits. DDECS 2010: 281-284 - [c11]Richard Ruzicka:
Gracefully Degrading Circuit Controllers Based on Polytronics. DSD 2010: 809-812
2000 – 2009
- 2009
- [c10]Lukás Sekanina, Richard Ruzicka, Zbysek Gajda:
Polymorphic FIR Filters with Backup Mode Enabling Power Savings. AHS 2009: 43-50 - [c9]Richard Ruzicka:
Dependable Controller Design Using Polymorphic Counters. DSD 2009: 355-362 - [c8]Lukás Sekanina, Richard Ruzicka, Zdenek Vasícek, Roman Prokop, Lukás Fujcik:
REPOMO32 - New reconfigurable polymorphic integrated circuit for adaptive hardware. WEAH 2009: 39-46 - 2008
- [c7]Richard Ruzicka, Lukás Sekanina, Roman Prokop:
Physical Demonstration of Polymorphic Self-Checking Circuits. IOLTS 2008: 31-36 - 2007
- [c6]Richard Ruzicka, Josef Strnadel:
Test Controller Synthesis Constrained by Circuit Testability Analysis. DSD 2007: 626-633 - 2006
- [c5]Richard Ruzicka, Lukás Sekanina:
Evolutionary circuit design in REPOMO - reconfigurable polymorphic module. Computational Intelligence 2006: 239-244 - 2004
- [c4]Richard Ruzicka, Pavel Tupec:
Formal Approach to Synthesis of a Test Controller. ECBS 2004: 348-355 - 2003
- [c3]Richard Ruzicka:
Testable Design Verification Using Petri Nets. DSD 2003: 304-311 - [c2]Lukás Sekanina, Richard Ruzicka:
Easily Testable Image Operators: The Class of Circuits Where Evolution Beats Engineers. Evolvable Hardware 2003: 135-144 - 2000
- [c1]Zdenek Kotásek, Richard Ruzicka, Jan Hlavicka:
Formal Approach to the RTL Testability Analysis. LATW 2000: 256-261
Coauthor Index
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