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21st Asian Test Symposium 2012: Niigata, Japan
- 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012. IEEE Computer Society 2012, ISBN 978-1-4673-4555-2
- Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima, Masahiro Takakura:
An Effective At-Speed Scan Testing Approach Using Multiple-Timing Clock Waveforms. 1 - Dale Meehl, Bassilios Petrakis, Ping Zhang:
LBIST/ATPG Technologies for On-Demand Digital Logic Testing in Automotive Circuits. 2 - Nobutaka Takahashi, Toshiaki Watanabe, Takehisa Suzuki, Manabu Kimura:
Portable/Desktop Testing Solution for Engineering with Cloud. 3 - Munetoshi Fukui, Yasuhiko Nara, Junichi Fuse:
Characteristics Variability Evaluation of Actual LSI Transistors with Nanoprobing. 4 - Hideo Okawara:
F-matrix (ABCD-matrix) Circuit Simulation Built in IC Test Program. 5 - Yervant Zorian:
Addressing Test Challenges in Advanced Technology Nodes. 6 - Xiaoxin Fan, Manish Sharma, Wu-Tung Cheng, Sudhakar M. Reddy:
Diagnosis of Cell Internal Defects with Multi-cycle Test Patterns. 7-12 - Mehdi Dehbashi, Görschwin Fey
:
Automated Post-Silicon Debugging of Failing Speedpaths. 13-18 - Satoshi Jo, Takeshi Matsumoto, Masahiro Fujita:
SAT-Based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions. 19-24 - Pranab Roy, Hafizur Rahaman
A New Look Ahead Technique for Customized Testing in Digital Microfluidic Biochips. 25-30 - Sergej Deutsch, Krishnendu Chakrabarty
TSV Stress-Aware ATPG for 3D Stacked ICs. 31-36 - Spencer K. Millican, Kewal K. Saluja:
Linear Programming Formulations for Thermal-Aware Test Scheduling of 3D-Stacked Integrated Circuits. 37-42 - Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng:
Programmable Leakage Test and Binning for TSVs. 43-48 - Ilia Polian:
Session Summary I: Quantum informatics: Classical circuit synthesis, resource optimisation and benchmarking. 49 - Rodney Van Meter
Counting Gates, Moving Qubits: Evaluating the Execution Cost of Quantum Circuits. 50-54 - Simon J. Devitt
Programming a Topological Quantum Computer. 55-60 - Shigeru Yamashita:
An Optimization Problem for Topological Quantum Computation. 61-66 - Xinli Gu:
Session Summary II: Dependable VLSI for Product Reliability. 67 - Sanghyeon Baeg, Jongsun Bae, Soonyoung Lee, Chul Seung Lim, Sang Hoon Jeon, Hyeonwoo Nam:
Soft Error Issues with Scaling Technologies. 68 - Yu Hu, Xinli Gu, Xiaowei Li:
In-Field Testing of NAND Flash Storage: Why and How? 69 - Jun Qian:
A Few Design Techniques for the "Dependability" of a SOC. 70 - Erik Larsson
Accessing Embedded DfT Instruments with IEEE P1687. 71-76 - Guoliang Li, Jun Qian, Peter Li, Greg Zuo:
Multi-level EDT to Reduce Scan Channels in SoC Designs. 77-82 - Xijiang Lin, Janusz Rajski:
On Utilizing Test Cube Properties to Reduce Test Data Volume Further. 83-88 - Masayuki Arai, Yoshihiro Shimizu, Kazuhiko Iwasaki:
Note on Layout-Aware Weighted Probabilistic Bridge Fault Coverage. 89-94 - Suraj Sindia, Vishwani D. Agrawal:
Tailoring Tests for Functional Binning of Integrated Circuits. 95-100 - Dong Xiang, Kele Shen, Yangdong Deng:
A Thermal-Driven Test Application Scheme for 3-Dimensional ICs. 101-106 - Yi-Tsung Lin, Jiun-Lang Huang, Xiaoqing Wen:
A Transition Isolation Scan Cell Design for Low Shift and Capture Power. 107-112 - Hossein Sabaghian Bidgoli, Majid Namaki-Shoushtari, Zainalabedin Navabi:
A Probabilistic and Constraint Based Approach for Low Power Test Generation. 113-118 - Yoshihiro Ohkawa, Yukiya Miura:
Dual Edge Triggered Flip-Flops for Noise Blocking and Application to Signal Delay Detection. 119-124 - Joao Azevedo, Arnaud Virazel
Impact of Resistive-Bridge Defects in TAS-MRAM Architectures. 125-130 - Yuntan Fang, Huawei Li, Xiaowei Li:
SoftPCM: Enhancing Energy Efficiency and Lifetime of Phase Change Memory in Video Applications via Approximate Write. 131-136 - Sourasis Das, Ansuman Banerjee, Pallab Dasgupta:
A Generalized Theory for Formal Assertion Coverage. 137-142 - Amir Masoud Gharehbaghi
Error Model Free Automatic Design Error Correction of Complex Processors Using Formal Methods. 143-148 - Armin Krieg
Hardware-Accelerated Workload Characterization for Power Modeling and Fault Injection. 149-154 - Stefan Holst, Eric Schneider, Hans-Joachim Wunderlich:
Scan Test Power Simulation on GPGPUs. 155-160 - Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
Power Supply Noise Sensor Based on Timing Uncertainty Measurements. 161-166 - Paolo Bernardi
Peak Power Estimation: A Case Study on CPU Cores. 167-172 - Yasuo Sato, Senling Wang, Takaaki Kato, Kohei Miyase, Seiji Kajihara:
Low Power BIST for Scan-Shift and Capture Power. 173-178 - Keisuke Kato, Fumitaka Abe, Kazuyuki Wakabayashi, Chuan Gao, Takafumi Yamada, Haruo Kobayashi, Osamu Kobayashi, Kiichi Niitsu
Two-Tone Signal Generation for Communication Application ADC Testing. 179-184 - Takahiro J. Yamaguchi, Kunihiro Asada, Kiichi Niitsu
A New Procedure for Measuring High-Accuracy Probability Density Functions. 185-190 - Jose Moreira:
Design of a High Bandwidth Interposer for Performance Evaluation of ATE Test Fixtures at the DUT Socket. 191-195 - Debesh Bhatta, Nicholas Tzou, Hyun Woo Choi, Abhijit Chatterjee:
Spectral Estimation Based Acquisition of Incoherently Under-sampled Periodic Signals: Application to Bandwidth Interleaving. 196-201 - Fangming Ye, Zhaobo Zhang, Krishnendu Chakrabarty
Adaptive Board-Level Functional Fault Diagnosis Using Decision Trees. 202-207 - Fangming Ye, Zhaobo Zhang, Krishnendu Chakrabarty
Board-Level Functional Fault Diagnosis Using Learning Based on Incremental Support-Vector Machines. 208-213 - Alejandro Cook, Dominik Ull, Melanie Elm, Hans-Joachim Wunderlich, Helmut Randoll, Stefan Dohren:
Reuse of Structural Volume Test Methods for In-System Testing of Automotive ASICs. 214-219 - Xiaoqing Wen, Sudhakar M. Reddy:
Session Summary III: Power-Aware Testing: Present and Future. 220 - Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
Why and How Controlling Power Consumption during Test: A Survey. 221-226 - Wei Zhao, Mohammad Tehranipoor:
PowerMAX: Fast Power Analysis during Test. 227-232 - Prab Varma:
Current and Future Directions in Automatic Test Pattern Generation for Power Delivery Network Validation. 233-238 - Xijiang Lin:
Power Supply Droop and Its Impacts on Structural At-Speed Testing. 239-244 - Takahiro J. Yamaguchi:
Session Summary IV: Post-Silicon Measurements and Tests: Analog Test and High-Speed I/O Test II. 245 - Koji Nii, Yasumasa Tsukamoto, Yuichiro Ishii, Makoto Yabuuchi, Hidehiro Fujiwara, Kazuyoshi Okamoto:
A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues. 246-251 - Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
Impact of All-Digital PLL on SoC Testing. 252-257 - Kiichi Niitsu
Post-Silicon Jitter Measurements. 258-263 - Jose Moreira, Bernhard Roth, Callum McCowan:
An Active Test Fixture Approach for Testing 28 Gbps Applications Using a Lower Data Rate ATE System. 264-269 - Xinli Gu:
Session Summary V: Is Component Interconnection Test Enough for Board or System Test. 270 - Wu-Tung Cheng, Feng-Ming Kuo:
Embedded Tutorial Summary: Diagnosis for Accelerating Yield and Failure Analysis. 271 - Senling Wang, Yasuo Sato, Kohei Miyase, Seiji Kajihara:
A Scan-Out Power Reduction Method for Multi-cycle BIST. 272-277 - Wei-Cheng Lien
A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume. 278-283 - Y.-H. Chou, Jiun-Lang Huang, Xuan-Lun Huang:
A Built-In Characterization Technique for 1-Bit/Stage Pipelined ADC. 284-289 - Stephan Eggersglüß, Mahmut Yilmaz, Krishnendu Chakrabarty
Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization. 290-295 - Steffen Zeidler, Christoph Wolf, Milos Krstic
Functional Pattern Generation for Asynchronous Designs in a Test Processor Environment. 296-301 - Valerio Guarnieri, Franco Fummi, Krishnendu Chakrabarty
Reduced-Complexity Transition-Fault Test Generation for Non-scan Circuits through High-Level Mutant Injection. 302-307 - Shyue-Kung Lu, Tsu-Lin Li, Pony Ning:
Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs. 308-313 - Jianbo Li, Yu Huang, Wu-Tung Cheng, Chris Schuermyer, Dong Xiang, Eric Faehn, Ruth Farrugia:
A Hybrid Flow for Memory Failure Bitmap Classification. 314-319 - Jun-Hua Kuo, Ting-Shuo Hsu, Jing-Jia Liou:
Test Cost Reduction for Performance Yield Recovery by Classification of Multiple-Clock Test Data. 320-325 - Takieddine Sbiai, Kazuteru Namba:
NoC Dynamically Reconfigurable as TAM. 326-331 - Debasis Mitra, Sarmishtha Ghoshal, Hafizur Rahaman
On-Line Error Detection in Digital Microfluidic Biochips. 332-337 - Ying Zhang, Ahmed Rezine, Petru Eles, Zebo Peng:
Automatic Test Program Generation for Out-of-Order Superscalar Processors. 338-343 - Alexander Czutro, Michael E. Imhof, J. Jiang, Abdullah Mumtaz, Matthias Sauer, Bernd Becker
Variation-Aware Fault Grading. 344-349 - Islam A. K. M. Mahfuzul
On-Chip Detection of Process Shift and Process Spread for Silicon Debugging and Model-Hardware Correlation. 350-354 - Byeongju Cha, Sandeep K. Gupta:
Efficient Trojan Detection via Calibration of Process Variations. 355-361
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