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NORCHIP 2011: Lund, Sweden
- 2011 NORCHIP, Lund, Sweden, November 14-15, 2011. IEEE 2011, ISBN 978-1-4577-0514-4
- Kin Keung Lee, Håkon A. Hjortland
, Tor Sverre Lande
IR-UWB technology on next generation RFID systems. 1-4 - Reza Meraji, John B. Anderson, Henrik Sjöland
Transistor sizing for a 4-state current mode analog channel decoder in 65-nm CMOS. 1-4 - Yevgen Borokhovych, Christoph Scheytt:
10 GS/s 8-bit bipolar THA in SiGe technology. 1-4 - Olli Kursu
Charge scaling 10-bit successive approximation A/D converter with reduced input capacitance. 1-4 - Dejan Radjen, Pietro Andreani, Martin Anderson, Lars Sundström
A continuous time ΔΣ modulator with reduced clock jitter sensitivity through DSCR feedback. 1-4 - Syed Asad Alam
Implementation of narrow-band frequency-response masking for efficient narrow transition band FIR filters on FPGAs. 1-4 - Johan Löfgren, Peter Nilsson:
On hardware implementation of radix 3 and radix 5 FFT kernels for LTE systems. 1-4 - Deepak Dasalukunte, Shahid Mehmood, Viktor Öwall:
Complexity analysis of IOTA filter architectures in faster-than-Nyquist multicarrier systems. 1-4 - Yelin Wang, Daniel Sira, Troels Studsgaard Nielsen, Ole K. Jensen, Torben Larsen
On wafer X-parameter based modeling of a switching cascode power amplifier. 1-4 - Felice Francesco Tafuri, Daniel Sira, Troels Studsgaard Nielsen, Ole Kiel Jensen, Torben Larsen
Wideband limit study of a GaN power amplifier using two-tone measurements. 1-4 - David J. Willingham, Izzet Kale:
A Ternary Adiabatic Logic (TAL) implementation of a four-trit Full-Adder. 1-4 - Petter Kallstrom, Oscar Gustafsson
Magnitude scaling for increased SFDR in DDFS. 1-4 - Andrea Bevilacqua
A 2.7-6.1GHz CMOS local oscillator based on frequency multiplication by 3/2. 1-4 - Vivek Elangovan, Markus Dietl, Puneet Sareen:
Very high bandwidth semi-digital PLL with large operating frequency range. 1-6 - Daniel Sira, Torben Larsen
Modeling of cascode modulated power amplifiers. 1-4 - Amir H. Miremadi, Ahmad Ayatollahi
A low voltage low power CMOS analog multiplier. 1-4 - Johannes Uhlig, René Schüffny:
An empirical study of the stability of 4th-order Incremental-ΣΔ-ADCs. 1-4 - Muhammad Shakir, Mohammed Abdulaziz, Ping Lu, Pietro Andreani:
A mixed mode design flow for multi GHz ADPLLs. 1-4 - Timo Rahkonen
Comparison of time-varying and non-time-varying Volterra analysis for finding distortion contributions in mixers. 1-4 - Lin Zhu, Martin Liliebladh:
Comparison and IIP2 analysis of two wideband Balun-LNAs designed in 65nm CMOS. 1-4 - Ronald Spilka, Dominik Gruber, Timm Ostermann:
Use of a calibrated voltage reference to enhance the performance of switched capacitor sigma-delta ADCs over process corner. 1-6 - Luca Fanori, Pietro Andreani:
Dynamic bias schemes for class-C VCOs. 1-4 - Johanna Anteroinen, Wonjae Kim, Kari Stadius, Juha Riikonen, Harri Lipsanen
Electrical properties of CVD-graphene FETs. 1-4 - Christian Schuss, Timo Rahkonen
Adaptive photovoltaic cell simulation with maximum power point tracking simulation for accurate energy predictions. 1-4 - Mohammed Hassan, Horst Zimmermann
An 85dB dynamic range transimpedance amplifier in 40nm CMOS technology. 1-4 - Mihkel Tagel, Peeter Ellervee
Contention aware scheduling for NoC-based real-time systems. 1-4 - Mojtaba Valinataj
A fault-tolerant and hierarchical routing algorithm for NoC architectures. 1-6 - Michael Opoku Agyeman
An adaptive router architecture for heterogeneous 3D Networks-on-Chip. 1-4 - Brad R. Jackson, Carlos E. Saavedra
A divide-by-three regenerative frequency divider using a subharmonic mixer. 1-4 - Tero Koivisto, Esa Tiiliharju, Peter Virta:
Injection-locked superharmonic self-oscillating mixer. 1-4 - Thomas Canhao Xu
Explorations of optimal core and cache placements for Chip Multiprocessor. 1-6 - Nicolas Borup, Jonas Dindorp, Alberto Nannarelli
FPGA implementation of decimal processors for hardware acceleration. 1-4 - Jiajia Jiao, Yuzhuo Fu, Jiang Jiang:
Architecture-level analysis and evaluation of transient errors on NoC. 1-4 - Hossein Doroud, Mahsa Ghorbanian, Reza Sabbaghi-Nadooshan:
Square topology: A novel topology for NoCs. 1-4 - Deena M. Zamzam, Mohamed A. Abd El-Ghany
Highly reliable and power efficient NOC interconnects. 1-4 - Seyyed Hassan Khalilinezhad, Akram Reza
Yield modeling and yield-aware mapping for application specific networks-on-chip. 1-4 - Khalid Latif, Amir-Mohammad Rahmani, Tiberiu Seceleanu
A low-cost processing element recovery mechanism for fault tolerant Networks-on-Chip. 1-4 - Muhammad Abbas, Oscar Gustafsson
Computational and implementation complexity of polynomial evaluation schemes. 1-6 - Shahzad Ahmad Butt, Luciano Lavagno:
Model-based rapid prototyping of multirate digital signal processing algorithms. 1-4 - Tobias Tired, Pietro Andreani:
Single-ended low noise multiband LNA with programmable integrated matching and high isolation switches. 1-4 - Anders Nejdel, Markus Törmänen, Henrik Sjöland
A linearized 1.6-5 GHz low noise amplifier using positive feedback in 65 nm CMOS. 1-4 - Xiaodong Liu, Vijay Viswam, Stefan Back Andersson, Johan Wernehag, Imad ud Din, Pietro Andreani:
Highly linear direct conversion receiver using customized on-chip balun. 1-4 - Hemanth Prabhu, Sherine Thomas, Joachim Neves Rodrigues, Thomas Olsson, Anders Carlsson:
A GALS ASIC implementation from a CAL dataflow description. 1-4 - Andreas Thor Winther, Wei Liu, Alberto Nannarelli
Temperature dependent wire delay estimation in floorplanning. 1-4 - Gatis Valters:
Initial version of Matlab/Simulink based tool for VHDL code generation and FPGA implementation of Elementary Generalized Unitary rotation. 1-6 - Mohammed Abdulaziz, Muhammad Shakir, Ping Lu, Pietro Andreani:
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS. 1-4 - Ying Wu, Xiaodong Liu, Dawei Ye
A 0.13µm CMOS ΔΣ PLL FM transmitter. 1-4 - Ying Wu, Ping Lu, Pietro Andreani:
A digital PLL with a multi-delay coarse-fine TDC. 1-4 - Matthew J. Turnquist, Erkka Laulainen, Jani Mäkipää, Lauri Koskinen:
Measurement of a system-adaptive error-detection sequential circuit with subthreshold SCL. 1-4 - Syed Iftekhar Ali
A novel low-energy match line sensing scheme for ternary content addressable memory using charge sharing. 1-4 - Oskar Andersson
Impact of switching activity on the energy minimum voltage for 65 nm sub-VT CMOS. 1-4 - Denys I. Martynenko, Gunter Fischer, Oleksiy Klymenko:
Low power programmable frequency divider for IEEE 802.15.4a standard. 1-4
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