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NANOARCH 2011: San Diego, CA, USA
- Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011, San Diego, CA, USA, June 8-9, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-0993-7
- Jason Cong, Bingjun Xiao:
mrFPGA: A novel FPGA architecture with memristor-based reconfiguration. 1-8 - Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Fabien Clermidy, Ian O'Connor
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Ultra-fine grain FPGAs: A granularity study. 9-15 - Wei Wei, Jie Han, Fabrizio Lombardi:
A hybrid memory cell using Single-Electron transfer. 16-23 - Jaeyoon Kim, Sandip Tiwari:
Inexact computing for ultra low-power nanometer digital circuit design. 24-31 - Richard Dorrance
Scalability and design-space analysis of a 1T-1MTJ memory cell. 32-36 - Ramakrishnan Venkatasubramanian
Improving performance of NEM relay logic circuits using integrated charge-boosting flip flop. 37-44 - Vinay Saripalli, Suman Datta, Vijaykrishnan Narayanan, Jaydeep P. Kulkarni:
Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design. 45-52 - Henry Park, Richard Dorrance
Analysis of STT-RAM cell design with multiple MTJs per access. 53-58 - Yi-Chung Chen, Hai Li
3D-HIM: A 3D High-density Interleaved Memory for bipolar RRAM design. 59-64 - Santhosh Onkaraiah, Pierre-Emmanuel Gaillardon, Marina Reyboz, Fabien Clermidy, Jean-Michel Portal, Marc Bocquet, Christophe Muller
Using OxRRAM memories for improving communications of reconfigurable FPGA architectures. 65-69 - Ciprian Teodorov, Pritish Narayanan, Loïc Lagadec
Regular 2D NASIC-based architecture and design space exploration. 70-77 - Masoud Zamani, Mehdi Baradaran Tahoori:
Self-timed nano-PLA. 78-85 - K. M. Masum Habib, Alexander Khitun, Alexander A. Balandin
Graphene nanoribbon crossbar nanomesh. 86-90 - Stefano Frache, Luca Gaetano Amarù, Mariagrazia Graziano, Maurizio Zamboni
Nanofabric power analysis: Biosequence alignment case study. 91-98 - Pritish Narayanan, Jorge Kina, Pavan Panchapakeshan, Priyamvada Vijayakumar, Kyeong-Sik Shin, Mostafizur Rahman, Michael Leuchtenburg, Israel Koren, Chi On Chui, Csaba Andras Moritz:
Nanoscale Application Specific Integrated Circuits. 99-106 - Prasad Shabadi, Alexander Khitun, Kin Wong, P. Khalili Amiri
Spin wave functions nanofabric update. 107-113 - Somayyeh Koohi, Shaahin Hessabi:
Power efficient nanophotonic on-chip network for future large scale multiprocessor architectures. 114-121 - Rangharajan Venkatesan, Vinay K. Chippa, Charles Augustine, Kaushik Roy, Anand Raghunathan
Energy efficient many-core processor for recognition and mining using spin-based memory. 122-128 - Charles Augustine, Georgios Panagopoulos, Behtash Behin-Aein, Srikant Srinivasan
Low-power functionality enhanced computation architecture using spin-based devices. 129-136 - Djaafar Chabi, Weisheng Zhao, Damien Querlioz, Jacques-Olivier Klein
Robust neural logic block (NLB) based on memristor crossbar array. 137-143 - Paul M. Riechers, Richard A. Kiehl:
A scheme for computation in nanoscale dynamical systems: Gated discrete phase-shift interactions. 144-149 - Damien Querlioz, Philippe Dollfus, Olivier Bichler, Christian Gamrat:
Learning with memristive devices: How should we model their behavior? 150-156 - Youngki Yoon, Sayeef S. Salahuddin:
Performance assessment of partially unzipped carbon nanotube field-effect transistors. 157-161 - Kotb Jabeur, Nataliya Yakymets, Ian O'Connor
Ambipolar double-gate FET binary-decision- diagram (Am-BDD) for reconfigurable logic cells. 162-168 - Ilke Ercan, Mostafizur Rahman, Neal G. Anderson:
Determining fundamental heat dissipation bounds for transistor-based nanocomputing paradigms. 169-174 - Yao Wang, Sorin Cotofana
A unified aging model of NBTI and HCI degradation towards lifetime reliability management for nanoscale MOSFET circuits. 175-180 - Priyamvada Vijayakumar, Pritish Narayanan, Israel Koren, C. Mani Krishna, Csaba Andras Moritz:
Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics. 181-188 - Santosh Khasanvis, K. M. Masum Habib, Mostafizur Rahman, Pritish Narayanan, Roger K. Lake
Hybrid Graphene Nanoribbon-CMOS tunneling volatile memory fabric. 189-195 - Pavan Panchapakeshan, Pritish Narayanan, Csaba Andras Moritz:
N3ASICs: Designing nanofabrics with fine-grained CMOS integration. 196-202 - George Razvan Voicu, Marius Enachescu
Towards "zero-energy" using NEMFET-based power management for 3D hybrid stacked ICs. 203-209 - Xinmu Wang, Seetharam Narasimhan, Somnath Paul, Swarup Bhunia
NEMTronics: Symbiotic integration of nanoelectronic and nanomechanical devices for energy-efficient adaptive computing. 210-217 - Xiwei Huang, Hao Yu, Wei Zhang
NEMS based thermal management for 3D many-core system. 218-223
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