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12th NoCArc@MICRO 2019: Columbus, OH, USA
- Kun-Chih Jimmy Chen, Sergi Abadal, Salvatore Monteleone:
Proceedings of the 12th International Workshop on Network on Chip Architectures, NoCArc@MICRO 2019, Columbus, OH, USA, October 13, 2019. ACM 2019, ISBN 978-1-4503-6949-7 - Baris Taskin:
On-chip wireless interconnect paradigm. 1:1 - Reetu Das:
Compute cache for data parallel acceleration. 2:1 - Antonio Franques:
Challenges and opportunities of wireless network-on-chip for manycore architectures. 3:1 - Rose George Kunthara
, Rekha K. James, Simi Zerine Sleeba, John Jose
Asymmetric routing in 3D NoC using interleaved edge routers. 4:1-4:6 - Mengjia Yan:
Research problems and opportunities in NoC-based side channel attacks and defenses: lessons learned from cache-based side channels. 5:1 - Tushar Krishna:
A communication-centric approach for designing flexible DNN accelerators. 6:1 - Ahmad Patooghy, Maral Filvan Torkaman, Mehdi Elahi:
Your hardware is all wired up!: attacking network-on-chips via crosstalk channel. 7:1-7:6 - Martin Schoeberl
S4NOC: a minimalistic network-on-chip for real-time multicores. 8:1-8:6 - Markos Kynigos, Jose Antonio Pascual
Scalability analysis of optical Beneš networks based on thermally/electrically tuned Mach-Zehnder interferometers. 9:1-9:6 - Nidhi Anantharajaiah
Dynamic and scalable runtime block-based multicast routing for networks on chips. 10:1-10:6 - Tuhin Subhra Das, Prasun Ghosal, Navonil Chatterjee:
Virtual circuit switch based orderly delivery of packets in adaptive NoC routing. 11:1-11:6 - Minghua Tang, Maurizio Palesi:
Study on logic-based routing for 3D NOCs. 12:1-12:6
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