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PACT 2010: Vienna, Austria
- Valentina Salapura, Michael Gschwind, Jens Knoop:
19th International Conference on Parallel Architectures and Compilation Techniques, PACT 2010, Vienna, Austria, September 11-15, 2010. ACM 2010, ISBN 978-1-4503-0178-7
Keynote address I
- David A. Ferrucci:
Build Watson: an overview of DeepQA for the Jeopardy! challenge. 1-2
Keynote address II
- Keshav Pingali:
Towards a science of parallel programming. 3-4
Keynote address III
- Wen-mei W. Hwu:
Raising the level of many-core programming with compiler technology: meeting a grand challenge. 5-6
Power-aware design
- Víctor Jiménez, Francisco J. Cazorla
, Roberto Gioiosa, Mateo Valero
Power and thermal characterization of POWER6 system. 7-18 - Karthik Ganesan, Jungho Jo, William Lloyd Bircher, Dimitris Kaseridis, Zhibin Yu, Lizy K. John:
System-level max power (SYMPO): a systematic approach for escalating system-level power consumption using synthetic benchmarks. 19-28 - Jonathan A. Winter, David H. Albonesi, Christine A. Shoemaker
Scalable thread scheduling and global power management for heterogeneous many-core architectures. 29-40 - Matthew A. Watkins, David H. Albonesi:
Dynamically managed multithreaded reconfigurable architectures for chip multiprocessors. 41-52
Analysis & optimization
- Derek L. Schuff, Milind Kulkarni, Vijay S. Pai:
Accelerating multicore reuse distance analysis with sampling and parallelization. 53-64 - Nalini Vasudevan, Kedar S. Namjoshi, Stephen A. Edwards
Simple and fast biased locks. 65-74 - Hari K. Pyla, Srinidhi Varadarajan:
Avoiding deadlock avoidance. 75-86 - Yun Zhang, Jae W. Lee, Nick P. Johnson, David I. August:
DAFT: decoupled acyclic fault tolerance. 87-98
Caches & coherence I
- John H. Kelm, Matthew R. Johnson, Steven S. Lumetta, Sanjay J. Patel:
WAYPOINT: scaling coherence to thousand-core architectures. 99-110 - Daehoon Kim, Jeongseob Ahn
Subspace snooping: filtering snoops with operating system support. 111-122 - Nick Barrow-Williams, Christian Fensch, Simon W. Moore
Proximity coherence for chip multiprocessors. 123-134 - Hongzhou Zhao, Arrvindh Shriraman, Sandhya Dwarkadas
SPACE: sharing pattern-based directory coherence for multicore scalability. 135-146
Parallelization and parallel programming I
- M. Aater Suleman, Moinuddin K. Qureshi, Khubaib, Yale N. Patt:
Feedback-directed pipeline parallelism. 147-156 - Zheng Li, Olivier Certner, José Duato
Scalable hardware support for conditional parallelization. 157-168 - Jisheng Zhao, Jun Shirako, V. Krishna Nandivada
Reducing task creation and termination overhead in explicitly parallel programs. 169-180 - Ganesh S. Dasika, Ankit Sethia, Vincentius Robby, Trevor N. Mudge, Scott A. Mahlke:
MEDICS: ultra-portable processing for medical image reconstruction. 181-192
Heterogeneous platforms and frameworks
- Jaejin Lee, Jungwon Kim
An OpenCL framework for heterogeneous multicores with local memory. 193-204 - Jayanth Gummaraju, Laurent Morichetti, Michael Houston, Ben Sander, Benedict R. Gaster, Bixia Zheng:
Twin peaks: a software platform for heterogeneous computing on general-purpose and graphics processors. 205-216 - Chuntao Hong, Dehao Chen, Wenguang Chen, Weimin Zheng, Haibo Lin:
MapCG: writing parallel program portable between CPU and GPU. 217-226 - Pradip Hari, John B. P. McCabe, Jonathan Banafato, Marcus Henry, Kevin Ko, Emmanouil Koukoumidis, Ulrich Kremer, Margaret Martonosi, Li-Shiuan Peh:
Adaptive spatiotemporal node selection in dynamic networks. 227-236
Scheduling and design optimization
- Di Xu, Chenggang Wu, Pen-Chung Yew
On mitigating memory bandwidth contention through bandwidth-aware scheduling. 237-248 - Sergey Zhuravlev, Sergey Blagodurov, Alexandra Fedorova:
AKULA: a toolset for experimenting and developing thread placement algorithms on multicore systems. 249-260 - Sandeep Navada, Niket Kumar Choudhary, Eric Rotenberg:
Criticality-driven superscalar design space exploration. 261-272 - Srihari Cadambi, Abhinandan Majumdar, Michela Becchi, Srimat T. Chakradhar, Hans Peter Graf:
A programmable parallel accelerator for learning and classification. 273-284
Best papers
- Ferad Zyulkyarov
Discovering and understanding performance bottlenecks in transactional applications. 285-294 - Changhui Lin, Vijay Nagarajan, Rajiv Gupta
Efficient sequential consistency using conditional fences. 295-306 - Zheng Wang
Partitioning streaming parallelism for multi-cores: a machine learning based approach. 307-318 - Manu Awasthi, David W. Nellans, Kshitij Sudan, Rajeev Balasubramonian, Al Davis:
Handling the problems and opportunities posed by multiple on-chip memory controllers. 319-330
Languages and compilers
- Amit Kumar, Lorenzo De Carli
Design and implementation of the PLUG architecture for programmable and efficient network lookups. 331-342 - Uday Bondhugula, Oktay Günlük
A model for fusion and code motion in an automatic parallelizing compiler. 343-352 - Gregory Frederick Diamos, Andrew Kerr, Sudhakar Yalamanchili, Nathan Clark:
Ocelot: a dynamic optimization framework for bulk-synchronous applications in heterogeneous systems. 353-364 - William Thies, Saman P. Amarasinghe
An empirical characterization of stream programs and its implications for language and compiler design. 365-376
Parallelization and parallel programming II
- Georgios Tournavitis, Björn Franke
Semi-automatic extraction and exploitation of hierarchical pipeline parallelism using profiling information. 377-388 - Hans Vandierendonck
The Paralax infrastructure: automatic parallelization with a helping hand. 389-400 - Jeremiah Willcock, Torsten Hoefler, Nicholas Gerard Edmonds, Andrew Lumsdaine
AM++: a generalized active message framework. 401-410 - I-Ting Angelina Lee, Silas Boyd-Wickizer, Zhiyi Huang, Charles E. Leiserson:
Using memory mapping to support cactus stacks in work-stealing runtime systems. 411-420
Speculation
- Rania H. Mameesh, Manoj Franklin:
Speculative-aware execution: a simple and efficient technique for utilizing multi-cores to improve single-thread performance. 421-430 - Walid J. Ghandour, Haitham Akkary, Wes Masri:
The potential of using dynamic information flow analysis in data value prediction. 431-442 - Tanausú Ramírez, Alex Pajuelo
Efficient runahead threads. 443-452 - Yangchun Luo, Venkatesan Packirisamy, Wei-Chung Hsu
Energy efficient speculative threads: dynamic thread allocation in Same-ISA heterogeneous multicore systems. 453-464
Caches and coherence II
- Seth H. Pugsley, Josef B. Spjut, David W. Nellans, Rajeev Balasubramonian:
SWEL: hardware cache coherence protocols to map shared data onto shared caches. 465-476 - George Kurian, Jason E. Miller, James Psota, Jonathan Eastep, Jifeng Liu, Jürgen Michel, Lionel C. Kimerling, Anant Agarwal:
ATAC: a 1000-core cache-coherent processor with on-chip optical network. 477-488 - Samira Manabi Khan, Daniel A. Jiménez, Doug Burger, Babak Falsafi:
Using dead blocks as a virtual victim cache. 489-500
Data distribution and tiling
- Yong Li, Ahmed Abousamra
Compiler-assisted data distribution for chip multiprocessors. 501-512 - I-Jui Sung, John A. Stratton, Wen-mei W. Hwu:
Data layout transformation exploiting memory-level parallelism in structured grid many-core applications. 513-522 - Rong Chen, Haibo Chen, Binyu Zang:
Tiled-MapReduce: optimizing resource usages of data-parallel applications on multicore with tiling. 523-534
Poster session
- Ali Bakhoda, John Kim
On-chip network design considerations for compute accelerators. 535-536 - Rajesh Bordawekar, Uday Bondhugula, Ravi Rao:
Believe it or not!: mult-core CPUs can match GPU performance for a FLOP-intensive application! 537-538 - Muhammad Amber Hassaan, Martin Burtscher, Keshav Pingali:
Ordered and unordered algorithms for parallel breadth first search. 539-540 - Matthew Misler, Natalie D. Enright Jerger
Moths: mobile threads for on-chip networks. 541-542 - Santhosh Sharma Ananthramu, Deepak Majeti, Sanjeev Kumar Aggarwal, Mainak Chaudhuri:
Improving speculative loop parallelization via selective squash and speculation reuse. 543-544 - Duane Merrill, Andrew S. Grimshaw:
Revisiting sorting for GPGPU stream architectures. 545-546 - Sandya S. Mannarswamy, Ramaswamy Govindarajan:
Analyzing cache performance bottlenecks of STM applications and addressing them with compiler's help. 547-548 - Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem:
An intra-tile cache set balancing scheme. 549-550 - David Eklov, David Black-Schaffer, Erik Hagersten:
StatCC: a statistical cache contention model. 551-552 - Wenjing Ma, Gagan Agrawal:
An integer programming framework for optimizing shared memory use on GPUs. 553-554 - Rafael Ubal, Julio Sahuquillo
Exploiting subtrace-level parallelism in clustered processors. 555-556 - Sergey Blagodurov, Sergey Zhuravlev, Alexandra Fedorova, Ali Kamali:
A case for NUMA-aware contention management on multicore systems. 557-558 - Haibo Lin, Tao Liu, Huoding Li, Tong Chen, Lakshminarayanan Renganarayanan, Kevin O'Brien, Ling Shao:
DMATiler: revisiting loop tiling for direct memory access. 559-560 - Christian Bienia, Kai Li:
Scaling of the PARSEC benchmark inputs. 561-562 - Richard West, Puneet Zaroo, Carl A. Waldspurger, Xiao Zhang:
Online cache modeling for commodity multicore processors. 563-564 - Ahmed Abousamra
NoC-aware cache design for chip multiprocessors. 565-566 - Jun Lee, Sangmin Seo, Jaejin Lee:
A software-SVM-based transactional memory for multicore accelerator architectures with local memory. 567-568 - R. Manikantan, Kaushik Rajan
NUcache: a multicore cache organization based on next-use distance. 569-570 - Shantanu Gupta, Shuguang Feng, Amin Ansari, Ganesh S. Dasika, Scott A. Mahlke:
CoreGenesis: erasing core boundaries for robust and configurable performance. 571-572 - Rajkishore Barik, Jisheng Zhao, Vivek Sarkar:
Automatic vector instruction selection for dynamic compilation. 573-574 - Michael Mihn-Jong Lee, John Kim
Approximating age-based arbitration in on-chip networks. 575-576
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