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CERN Document Server 2,043 elementer funnet  1 - 10nesteslutt  gå til element: Søket tok 0.28 sekunder. 
1.
(100)
The lpGBT PLL and CDR Architecture, Performance and SEE Robustness / Biereigel, Stefan (Brandenburg Tech. U. ; Leuven U. ; CERN) ; Kulis, Szymon (CERN) ; Francisco, Rui (CERN) ; Leitao, Pedro Vicente (CERN) ; Leroux, Paul (Leuven U.) ; Moreira, Paulo (CERN) ; Prinzie, Jeffrey (Leuven U.)
We present the design, architecture and experimental results of the low jitter Clock and Data Recovery (CDR) and Phase Locked Loop (PLL) circuit in the Low-Power Gigabit Transceiver (lpGBT) ASIC. This circuit includes a low noise radiation-tolerant integrated LC-oscillator with a nominal frequency of 5.12 GHz to support a 10.24 Gbps uplink and a 2.56 Gbps downlink CDR. [...]
SISSA, 2020 - 5 p. - Published in : PoS TWEPP2019 (2020) 034 Fulltext: PDF;
In : TWEPP 2019 Topical Workshop on Electronics for Particle Physics, Santiago De Compostela, Spain, 2 - 6 Sep 2019, pp.034
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2.
(91)
A 2.56 GHz Radiation Hard Phase Locked Loop ASIC for High Speed Serial Communication Links / Prinzie, Jeffrey (Leuven U.) ; Steyaert, Michiel (Leuven U.) ; Leroux, Paul (Leuven U.) ; Moreira, Paulo (CERN)
This works presents the design and experimental study of a radiation hardened Phase Locked Loop (PLL) for high speed serial-communication links. These research results are used for the LpGBT (Low Power Gigabit Transceiver) chip which will be widely used for optical data-links between the detectors and the counting rooms in the HL LHC experiments. [...]
SISSA, 2018 - 6 p. - Published in : PoS TWEPP-17 (2017) 002 Fulltext: PDF; External link: PoS server
In : Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017, pp.002
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3.
(91)
A radiation tolerant clock generator for the CMS Endcap Timing Layer readout chip / Sun, H. (Southern Methodist U. ; Hua-Zhong Normal U.) ; Sun, Q. (Fermilab) ; Biereigel, S. (CERN ; Leuven U.) ; Francisco, R. (CERN) ; Gong, D. (Southern Methodist U.) ; Huang, G. (Hua-Zhong Normal U.) ; Huang, X. (Southern Methodist U.) ; Kulis, S. (CERN) ; Leroux, P. (Leuven U.) ; Liu, C. (Southern Methodist U.) et al.
We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low-Power Gigabit Transceiver (lpGBT) project. [...]
arXiv:2110.12625; FERMILAB-CONF-21-633-PPD.- 2022-03-23 - 6 p. - Published in : 10.1088/1748-0221/17/03/C03038 Fulltext: 2b8e809fdbeb999e8d3e2f1ac77fa465 - PDF; fermilab-conf-21-633-ppd - PDF; 2110.12625 - PDF; External link: Fermilab Accepted Manuscript
In : TWEPP 2021 Topical Workshop on Electronics for Particle Physics, Online, Online, 20 - 24 Sep 2021, pp.C03038
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4.
(44)
Source Switched Charge-Pump PLLs for High-Dose Radiation Environments / Prinzie, Jeffrey (Leuven U.) ; Biereigel, Stefan (CERN) ; Kulis, Szymon (CERN) ; Leitao, Pedro (CERN) ; Moreira, Paulo (CERN)
This article presents a radiation tolerant charge-pump phase-locked loop (PLL) with low static phase error variability suitable for high-performance clock systems in high-dose radiation environments. We investigate the use of source switching charge-pump architectures to minimize any voltage- or dose-dependent charge injection and address the limitations of enclosed layout transistors (ELTs) in the conventional drain switched charge-pump. [...]
2023 - 6 p. - Published in : IEEE Trans. Nucl. Sci. 70 (2023) 590-595
In : 2022 IEEE Nuclear and Space Radiation Effects Conference, Provo, Utah, USA, 18 - 23 Jul 2022, pp.590-595
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5.
(39)
Radiation-tolerant all-digital clock generators for HEP applications / Biereigel, S (CERN ; Geel, Cathol. High Sch. Kempen ; Brandenburg Tech. U.) ; Kulis, S (CERN) ; Mendes, E (CERN) ; Hazell, P (CERN) ; Moreira, P (CERN) ; Prinzie, J (Geel, Cathol. High Sch. Kempen)
The emergence of high-precision timing systems in High Energy Physics motivates new developments in the domain of clock generation and distribution. Particularly, when considering the challenges arising from adopting advanced deep-submicron CMOS technology nodes, all-digital PLL and clock and data recovery (CDR) architectures constitute a promising option for future high energy physics (HEP) experiments. [...]
2023 - 8 p. - Published in : JINST 18 (2023) C01060 Fulltext: PDF;
In : Topical Workshop on Electronics for Particle Physics 2022 (TWEPP 2022), Bergen, Norway, 19 - 23 Sep 2022, pp.C01060
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6.
(38)
Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS / Biereigel, Stefan (CERN ; Leuven U. ; Brandenburg Tech. U.) ; Kulis, Szymon (CERN) ; Moreira, Paulo (CERN) ; Kölpin, Alexander (Hamburg, Tech. U.) ; Leroux, Paul (Leuven U.) ; Prinzie, Jeffrey (Leuven U.)
This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to SingleEvent Effects (SEEs) up to 62.5 MeV cm$^{2}$ mg$^{−1}$ as well as tolerance to the Total Ionizing Dose (TID) exceeding 1.5 Grad. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding the use of a highly SEE sensitive circuit element. [...]
2021 - 16 p. - Published in : Electronics 10 (2021) 2741
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7.
(38)
A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit With High Speed Feed Forward Correction in 65 nm CMOS / Biereigel, Stefan (Leuven U.) ; Kulis, Szymon (CERN) ; Leitao, Pedro (CERN) ; Francisco, Rui (CERN) ; Moreira, Paulo (CERN) ; Leroux, Paul (Leuven U.) ; Prinzie, Jeffrey (Leuven U.)
A fault tolerant, radiation hardened Clock and Data Recovery (CDR) architecture is presented for high-energy physics and space applications. The CDR employs a novel soft-error tolerant Voltage Controlled Oscillator (VCO) and includes a high-speed feed-forward path, which stabilizes the CDR by compensating for an additional pole introduced in the VCO in order to harden it against ionizing particles. [...]
2019 - 9 p. - Published in : IEEE Trans. Circuits Theor. 67 (2019) 1438-1446
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8.
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Comparison of a 65 nm CMOS Ring- and LC-Oscillator Based PLL in Terms of TID and SEU Sensitivity / Prinzie, Jeffrey (Leuven U. ; CERN) ; Christiansen, Jorgen (Leuven U. ; CERN) ; Moreira, Paulo (Leuven U. ; CERN) ; Steyaert, Michiel (Leuven U. ; CERN) ; Leroux, Paul (Leuven U. ; CERN)
In this work, a comparison has been made between a low noise ring-oscillator and an LC-oscillator Phase Locked Loop (PLL). An ASIC has been developed to conduct irradiation experiments targeting high-energy physics applications. [...]
2017 - 8 p. - Published in : IEEE Trans. Nucl. Sci. 64 (2017) 245-252
In : 2016 IEEE Nuclear and Space Radiation Effects Conference, Portland, OR, 11 - 15 Jul 2016, pp.245-252
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9.
(28)
Book cover lpGBT documentation : release
12 Aug 2024. - 359 p.

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10.
(27)
Radiation-Tolerant Digitally Controlled Ring Oscillator in 65-nm CMOS / Biereigel, Stefan (CERN ; Leuven U. ; Brandenburg Tech. U.) ; Kulis, Szymon (CERN) ; Leroux, Paul (Leuven U.) ; Moreira, Paulo (CERN) ; Prinzie, Jeffrey (Leuven U.)
This article presents a radiation-tolerant digitally controlled complementary metal–oxide–semiconductor (CMOS) ring oscillator design suitable for all-digital phase-locked loop (ADPLL) implementations. To address the challenges presented by harsh radiation environments, a wide tuning range oscillator architecture is presented with superior single-event effect (SEE) tolerance. [...]
2022 - 9 p. - Published in : IEEE Trans. Nucl. Sci. 69 (2022) 17-25 Fulltext: PDF;
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