Chapter 3
Chapter 3
Chapter 3
Introduction
It provides 16 address lines so it can access 2^16 =64K bytes of memory. It generates 8 bit I/O address so it can access 2^8=256 input ports. It provides 5 hardware interrupts:TRAP, RST 5.5, RST 6.5, RST 7.5,INTR. It provides Acc ,one flag register ,6 general purpose registers and two special purpose registers(SP,PC). It provides serial lines SID ,SOD.So serial peripherals can be interfaced with 8085 directly.
The 8085 is an 8-bit general purpose microprocessor that can address 64K Byte of memory. It has 40 pins and uses +5V for power. It can run at a maximum frequency of 3 MHz.
The pins on the chip can be grouped into 6 groups:
Address Bus. Data Bus. Control and Status Signals. Power supply and frequency. Externally Initiated Signals. Serial I/O ports.
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8085 Pinout
AD0-AD7: Multiplexed Address and data lines. A8-A15: Tri-stated higher order address lines. ALE: Address latch enable is an output signal.It goes high when operation is started by processor . S0,S1: These are the status signals used to indicate type of operation. RD: Read is active low input signal used to read data from I/O device or memory. WR:Write is an active low output signal used write data on memory or an I/O device.
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The address bus has 8 signal lines A8 A15 which are unidirectional. The other 8 address bits are multiplexed (time shared) with the 8 data bits.
So, the bits AD0 AD7 are bi-directional and serve as A0 A7 and D0 D7 at the same time.
During the execution of the instruction, these lines carry the address bits during the early part, then during the late parts of the execution, they carry the 8 data bits.
In order to separate the address from the data, we can use a latch to save the value before the function of the bits changes.
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HOLD&HLDA:HOLD is an input signal .When P receives HOLD signal it completes current machine cycle and stops executing next instruction.In response to HOLD P generates HLDA that is HOLD Acknowledge signal. RESET IN:This is input signal.When RESET IN is low p restarts and starts executing from location 0000H. SID: Serial input data is input pin used to accept serial 1 bit data . X1X2 :These are clock input signals and are connected to external LC,or RC circuit.These are divide by two so if 6 MHz is connected to X1X2, the operating frequency becomes 3 MHz. VCC&VSS:Power supply VCC=+ -5Volt& VSS=-GND reference.
CLK (OUT): An output clock pin to drive the clock of the rest of the system.
To understand how the microprocessor operates and uses these different signals, we should study the process of communication between the microprocessor and memory during a memory read or write operation. Lets look at timing and the data flow of an instruction fetch operation. (Example 3.1)
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Lets assume that we are trying to fetch the instruction at memory location 2005. That means that the program counter is now set to that value.
The following is the sequence of operations:
The program counter places the address value on the address bus and the controller issues a RD signal. The memorys address decoder gets the value and determines which memory location is being accessed. The value in the memory location is placed on the data bus. The value on the data bus is read into the instruction decoder inside the microprocessor. After decoding the instruction, the control unit issues the proper control signals to perform the operation.
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Now, lets look at the exact timing of this sequence of events as that is extremely important. (figure 3.3)
At T1 , the high order 8 address bits (20H) are placed on the address lines A8 A15 and the low order bits are placed on AD7 AD0. The ALE signal goes high to indicate that AD0 AD8 are carrying an address. At exactly the same time, the IO/M signal goes low to indicate a memory operation. At the beginning of the T2 cycle, the low order 8 address bits are removed from AD7 AD0 and the controller sends the Read (RD) signal to the memory. The signal remains low (active) for two clock periods to allow for slow devices. During T2 , memory places the data from the memory location on the lines AD7 AD0 . During T3 the RD signal is Disabled (goes high). This turns off the output Tri-state buffers in the memory. That makes the AD7 AD0 lines go to high impedence mode.
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Demultiplexing AD7-AD0
From the above description, it becomes obvious that the AD7 AD0 lines are serving a dual purpose and that they need to be demultiplexed to get all the information. The high order bits of the address remain on the bus for three clock periods. However, the low order bits remain for only one clock period and they would be lost if they are not saved externally. Also, notice that the low order bits of the address disappear when they are needed most. To make sure we have the entire address for the full three clock cycles, we will use an external latch to save the value of AD7 AD0 when it is carrying the address bits. We use the ALE signal to enable this latch.
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Demultiplexing AD7-AD0
8085
A15-A8
A7- A0
D7- D0
Given that ALE operates as a pulse during T1, we will be able to latch the address. Then when ALE goes low, the address is saved and the AD7 AD0 lines can be used for their purpose as the bidirectional data lines.
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From the above discussion, we can define terms that will become handy later on:
T- State: One subdivision of an operation. A T-state lasts for one clock period.
An instructions execution length is usually measured in a number of T-states. (clock cycles).
Machine Cycle: The time required to complete one operation of accessing memory, I/O, or acknowledging an external request.
This cycle may consist of 3 to 6 T-states.
The 8085 generates a single RD signal. However, the signal needs to be used with both memory and I/O. So, it must be combined with the IO/M signal to generate different control signals for the memory and I/O.
Keeping in mind the operation of the IO/M signal we can use the following circuitry to generate the right set of signals:
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Previously we discussed the 8085 from a programmers perspective. Now, lets look at some of its features with more detail.
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The ALU
In addition to the arithmetic & logic circuits, the ALU includes the accumulator, which is part of every arithmetic & logic operation. Also, the ALU includes a temporary register used for holding data temporarily during the execution of the operation. This temporary register is not accessible by the programmer.
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Z-zero flag
Set if the result of the ALU operation is 0. Otherwise is reset. This flag is affected by operations on the accumulator as well as other registers. (DCR B).
AC-Auxiliary Carry
This flag is set when a carry is generated from bit D3 and passed to D4 . This flag is used only internally for BCD operations. (Section 10.5 describes BCD addition including the DAA instruction).
P-Parity flag
After an ALU operation if the result has an even # of 1s the p-flag is set. Otherwise it is cleared. So, the flag can be used to indicate even parity.
CY-carry flag
Discussed earlier 20
The 8085 executes several types of instructions with each requiring a different number of operations of different types. However, the operations can be grouped into a small set. The three main types are:
Memory Read and Write. I/O Read and Write. Request Acknowledge.
The first step of executing any instruction is the Opcode fetch cycle.
In this cycle, the microprocessor brings in the instructions Opcode from memory.
To differentiate this machine cycle from the very similar memory read cycle, the control & status signals are set as follows:
IO/M=0, s0 and s1 are both 1.
It is also possible for an instruction to have 6 Tstates in an opcode fetch machine cycle.
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The memory read machine cycle is exactly the same as the opcode fetch except:
It only has 3 T-states The s0 signal is set to 0 instead.
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2001H
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The first byte 3EH represents the opcode for loading a byte into the accumulator (MVI A), the second byte is the data to be loaded.
The 8085 needs to read these two bytes from memory before it can execute the instruction. Therefore, it will need at least two machine cycles.
The first machine cycle is the opcode fetch discussed earlier. The second machine cycle is the Memory Read Cycle. Figure 3.10 page 83.
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Memory interfacing
There needs to be a lot of interaction between the microprocessor and the memory for the exchange of information during program execution.
Memory has its requirements on control signals and their timing. The microprocessor has its requirements as well.
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RAM
Input Buffer WR
ROM
Address Lines
CS
Address Lines
CS
Output Buffer
RD
Output Buffer
RD
Data Lines
Date Lines
Interfacing Memory
Accessing memory can be summarized into the following three steps:
Select the chip. Identify the memory register. Enable the appropriate buffer.
Address decoding
The result of address decoding is the identification of a register for a given address.
A large part of the address bus is usually connected directly to the address inputs of the memory chip. This portion is decoded internally within the chip. What concerns us is the other part that must be decoded externally to select the chip. This can be done either using logic gates or a decoder.
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8085
A15-A8
ALE
CS
AD7-AD0
Latch
A9- A0 A7- A0
WR RD
IO/M
D7- D0
RD WR
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The 8155 is a special chip designed to work with the 8085 to demonstrate the interfacing of the 8085. the 8155 has 256 bytes of RAM, 2 programmable I/O ports and a timer. It is usually used in systems designed for use in university labs. We will now concentrate on the memory part of the 8155.
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The 8155 contains all the circuitry needed to interface to the 8085 directly.
It has 8 lines that match the AD0-AD7 of the 8085. It has 5 control lines that match the control and status lines of the 8085.
The address/data lines are demultiplexed internally inside the 8155 and the control signals needed for the memory are also generated internally.
All that is needed to interface the 8155 to the 8085 is logic to control the 8155 to determine the starting address of the memory segment.
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Testing a memory chip in an existing system is as easy as loading a byte at a specific address and then verifying that it was loaded. A few more addresses should also be checked. In case of fold back memory, one should test the different address ranges for the dont care address lines.
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