8051 Microcontroller

Objectives

Understand the 8051 Architecture

Overview
• The Intel 8051 is a very popular general purpose
microcontroller widely used for small scale
embedded systems.

• Many vendors such as Atmel, Philips, and Texas

Instruments produce MCS-51 family microcontroller
chips.

• The 8051 is an 8-bit microcontroller with

– 8 bit data bus and
– 16-bit address bus
Overview . . .
• The 16 bit address bus can
– address a 64K( 216) byte code memory space and
– a separate 64K byte of data memory space

• The 8051 has

– 4K on-chip read only code memory
– 128 bytes of internal Random Access Memory (RAM)
Overview . . .
• Besides internal RAM, the 8051 has various Special Function Registers
(SFR) such as
– the Accumulator
– the B register and
– many other control registers
– 34 8-bit general purpose registers in total

• The ALU performs one 8-bit operation at a time

• Two 16 bit /Counter timers
• 3 internal interrupts
– one serial
– 2 external interrupts
• Four 8-bit I/O ports
– 3 of them are dual purposed
– One of them used for serial port
40 pins on the 8051 chip
 P1.0 1 40 Vcc

P1.1 2 39 P0.0(AD0)

P1.2 3 38 P0.1(AD1)

P1.3 4 37 P0.2(AD2)

P1.4 5 36 P0.3(AD3)
Ext
Memory
P1.5 6 8051 35 P0.4(AD4) Address

P1.6 7 34 P0.5(AD5)

P1.7 8 33 P0.6(AD6)

RST 9 32 P0.7(AD7)

(RXD) P3.0 10 31 EA/VPP

(Serial)
Ext Memory
(TXD) P3.1 11 30 ALE/PROG Access Control

(INT0) P3.2 12 29 PSEN

interrupt
(INT1) P3.3 13 28 P2.7(A15)

(T0) P3.4 14 27 P2.6(A14)

Timer
(T1) P3.5 15 26 P2.5(A13)

(WR) P3.6 16 25 P2.4(A12)

Ex M W/R
(RD) P3.7 17 24 P2.3(A11) Ext Memory
Address

XTAL 2 18 23 P2.2(A10)
clock
XTAL 1 19 22 P2.1(A9)

GND 20 21 P2.0(A8)

Pin out Diagram of the 8051 Microcontroller

Overview . . .
• Some 8051 chips come with in-built
– UART for serial communication and
– ADC for analog to digital conversion
• The EA-External Access pin is used to control the
internal or external memory access
– signal 0 is for external memory access and
– signal 1 for internal memory access
• The PSEN-Program Store Enable is for reading
external code memory when it is low (0) and EA is
also 0
• The ALE-Address Latch Enable activates the port 0 &
port 2 to provide 16 bit external address bus to
access the external memory
• WR - signal to write external data memory
• RD - signal to read external data and code memory
System Clock and Oscillator Circuits
• The oscillator circuit usually runs around 12MHz
– the crystal generates 12M pulses in one second

• A machine cycle is minimum amount time a simplest machine

instruction must take

• An 8051 machine cycle consists of 12 crystal pulses (clock

cycle)
8051 Internal Architecture

Ex.M timer interrupt serial

R, W T1, T0 INT1, INT0 TXD.RXD

P1.0 – p1.7 (1-8) P3.0 – p3.7 (10-17)

(40)Vcc
Port 1 Port 3
(20) Vg

Data RAM
TCON,TMOD EPROM
Register B Acc T
TLO/1, THO/1
code
SCON,SBUF,IE,IP
FCON
(SFRs
Ex.M access ALT
Control Timer User data PC
(29-31) And
Control
psw

IR +1
Reset
(9)

OSC Port 2 Port 0

(18 – 19) P2.7 – P2.0(21-28) P0.7 – P0.0 (32-39)

A7 - 0
A15 - 8
A Ex.M (upto 64k)
15 - 0

Simplified 8051 block diagram

Microcontroller 8051 internal
Architecture
8051 Internal Architecture
• The CPU has many important registers
– The Program Count (PC) always holds the code memory location of
next instruction
• It fetches instructions from the code memory into the
instruction Register (IR)

• analyzes the opcode of the instruction, updates the PC to the

location of next instruction

• fetches the oprand from the data memory and

• finally performs the operation in the Arithmetic-Logic Unit

(ALU) within the CPU
 Contd.

• The B register is a register just for multiplication

and division operation which requires more register
spaces for the product of multiplication and the
quotient and the remainder for the division.
• The immediate result is stored in the accumulator
register (Acc) for next operation
• and the Program Status Word (PSW) is updated
depending on the status of the operation result
 The Port Alternate Functions
• PORT P1 (Pins 1 to 8): The port P1 is a port dedicated for general
I/O purpose. The other ports P0, P2 and P3 have dual roles in
addition to their basic I/O function.
• PORT P0 (pins 32 to 39): When the external memory access is
required then Port P0 is multiplexed for address bus and data
bus that can be used to access external memory in conjunction
with port P2. P0 acts as A0-A7 in address bus and D0-D7 for port
data. It can be used for general purpose I/O if no external
memory presents.
• PORT P2 (pins 21 to 28): Similar to P0, the port P2 can also play a
role (A8-A15) in the address bus in conjunction with PORT P0 to
access external memory.
 Contd.
• PORT P3 (Pins 10 to 17):
In addition to acting as a normal I/O port,
• P3.0 can be used for serial receive input pin(RXD)
• P3.1 can be used for serial transmit output
pin(TXD) in a serial port,
• P3.2 and P3.3 can be used as external interrupt
pins(INT0’ and INT1’),
• P3.4 and P3.5 are used for external counter input
pins(T0 and T1),
• P3.6 and P3.7 can be used as external data memory
write and read control signal pins(WR’ and RD’)read
and write pins for memory access.
 Memory and SFR

• The 8051 code(program) memory is read-only, while the data

memory is read/write accessible. The program memory( in
EPROM) can be rewritten by the special programmer circuit.
• The 8051 memory is organized in a Harvard Architecture. Both
the code memory space and data memory space begin at
location 0x00 for internal or external memory which is different
from the Princeton Architecture where code and data share
same memory space.
• The advantage of the Harvard Architecture is not only doubling
the memory capacity of the microcontroller with same number
of address lines but also increases the reliability of the
microcontroller, since there are no instructions to write to the
code memory which is read only.
Separate read instructions for external data and code memory.

Internal code
External data memory
Memory
RAM
ROM or EPROM
64k
4k or up

0xFF

SFR(direct access)
128 bytes External code memory
ROM or EPROMext
64k
0x80

0x7F

General purpose RAM

(variable data) 80 bytes

0x30
0x2F

Bit addressible RAM 16 bytes

16x8 bits

0x20
0x1F Register bank 0(R0-R7)

Register bank 1(R0-R7) 4x8=

32 bytes
Register bank 2(R0-R7)

0x00 Register bank 3(R0-R7)

Internal data memory

RAM
 Contd.

• In this model, the data memory and code memory

use separate maps by a special control line called
Program Select Enable (PSEN’).
• This line (i.e. when PSEN’ = 0) is used to indicate that
the 16 address lines are being used to address the
code memory.
• When this line is ‘1’, the 16 address lines are being
used to address the data memory.
 Contd.
• The 8051 has 256 bytes of internal addressable RAM,
although only first 128 bytes are available for general
use by the programmer.
• The first 128 bytes of RAM (from 0x00 to 0x7F) are
called the direct memory, and can be used to store
data.
• The lowest 32 bytes of RAM are reserved for 4
general register banks. The 8051 has 4 selectable
banks of 8 addressable 8-bit registers, R0 to R7.
 Contd.
• This means that there are essentially 32 available
general purpose registers, although only 8 (one bank)
can be directly accessed at a time.
• The advantage of using these register banks is time
saving on the context switch for interrupted program to
store and recover the status.
• Otherwise the push and pop stack operations are
needed to save the current state and to recover it after
the interrupt is over.
• The default bank is bank 0.
• The second 128 bytes are used to store Special
Function Registers (SFR) that C51 program can
configure and control the ports, timer, interrupts, serial
communication, and other tasks.
Special Function Registers (SFRs)
• The SFR is the upper area of addressable memory, from
address 0x80 to 0xFF. This area consists of a series of
memory-mapped ports and registers.
• All port input and output can therefore be performed by get
and set operations on SFR port name such as P3.
• Also, different status registers are mapped into the SFR for
checking the status of the 8051, and changing some
operational parameters of the 8051.
• All 8051 CPU registers, I/O ports, timers and other
architecture components are accessible in 8051 C through
SFRs
 Contd.
• There are 21 SFRs.
• In addition to I/O ports, the most frequently used SFRs
to control and configure 8051 operations are:
 TCON (Timer CONtrol)
 TMOD (Timer MODe)
 TH0/TH1 and TL0/TL1 (Timer’s high and low bytes)
 SCON (Serial port CONtrol)
 IP (Interrupt Priority)
 IE ( Interrupt Enable)
• Almost all 8051 C embedded programs include the
reg51.h.
TCON- (Timer/Counter Control Register) SFR for timer control

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(88H)

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

• TF0/TF1: Timer0/1 overflow flag is set when the timer

counter overflows, reset by program
• TR0/TR1: Timer0/1 run control bit is set to start, reset to
stop the timer0/1
• IE0/IE1: External interrupt 0/1
• IT0/IT1 External interrupt type
IE - (Interrupt Enable Register) SFR used for interrupt control

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(A8H)
EA ET2 ES ET1 EX1 ET0 EX0

• EX0/EX1 : (1/0) Enables/disables the external interrupt 0

and the external interrupt 1 on port P3.2 and P3.3
• ET0/ET1 : (1/0) Enables/disables the Timer0 and Timer1
interrupt via TF0/1
• ES : (1/0) Enables/disables the serial port interrupt for
sending and receiving data
• EA : (1/0) Enables/disables all interrupts
IP - ( Interrupt Priority Register) SFR used for IP setting
• PX0/1: External interrupt 0/1 priority level
• PT0/1/2: Timer0, Timer1, Timer2(8052) interrupt priority
level
• PS: Serial port interrupt priority level

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

PT2 PS PT1 PX1 PT0 PX0

PSW - (Program Status Word) SFR for CPU status
• P: parity check flag
• OV: ALU overflow flag
• RS0/RS1: Register bank specification mode
• 00: bank 0 (00H-07H); 01: bank1; 10: bank 2; 11: bank 3(18H-
1FH)
• F0: User defined lag
• CY: ALU carry out
• AC: ALU auxiliary carry out
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

CY AC F0 RS1 RS0 OV P
TMOD - ( Timer Mode Register) SFR(not bit addressable)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Gate C/T M1 M0 Gate C/T M1 M0

Gate Control:
• 0= Timer enabled(normal mode)
• 1 = if INT0/INT1 is high, the timer is enabled to count
the number of pulses in the external interrupt ports
(P3.2 and P3.3)
C/T - Counter/Timer Selector

• 0 = count internal clock pulse (count once per machine

cycle = oscillator clock/12)
• 1 = count external pulses on P3.4 (Timer 0) and
P3.5(Timer 1)
• Working as a “Timer”, the timer is incremented by one every
machine cycle.
• Working as a “Counter”, the counter is incremented in
response to a falling edge transition in the external input pins.
• The external input is sampled once every machine cycle. A
“high” sample followed by a low sample is counted once.
• Timer 0 and Timer 1 have four operating modes.

M1, M0 Mode Control

0 0 (Mode 0) 13 bit count mode
0 1 (Mode 1) 16 bit count mode
1 0 (Mode 2) Auto reload mode
1 1 (Mode 3) Multiple mode