Unit-1:

8086 Architecture – Main features, Pin diagram/ description

8086 microprocessor family
8086 internal architecture, Bus interfacing unit, execution
unit, interrupts and interrupt responses, 8086 system timing,
minimum mode and maximum mode configuration

1
 INTRODUCTION TO MICROPROCESSORS

Microprocessor:-
• CPU on a single chip is called as microprocessor.
• A microprocessor is multipurpose programmable, clock driven
electronic device which accepts binary data as inputs , processes it and
gives the results as outputs.

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Microprocessor Vs Microcontroller

3
Microprocessor Vs Microcontroller

4
Microprocessor & Microcontroller - Applications

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Microprocessor & Microcontroller - Applications

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Microprocessor & Microcontroller - Applications

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Microprocessor & Microcontroller - Applications

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 Microprocessor Generations Fifth Generation Pentium

Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
Third Generation 32 bit processors
During 1978 Physical memory space 224 bytes = 16 Mb
HMOS technology  Faster speed, Higher Virtual memory space 240 bytes = 1 Tb
packing density Floating point hardware
16 bit processors  40/ 48/ 64 pins Supports increased number of addressing
Easier to program modes
Dynamically relatable programs
Processor has multiply/ divide arithmetic Intel 80386
hardware
More powerful interrupt handling
capabilities Second Generation
Flexible I/O port addressing During 1973
NMOS technology  Faster speed, Higher
Intel 8086 (16 bit processor) density, Compatible with TTL
4 / 8/ 16 bit processors  40 pins
First Generation Ability to address large memory spaces
Between 1971 – 1973 and I/O ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine
4 bit processors  16 pins nesting
8 and 16 bit processors  40 pins Better interrupt handling capabilities
Due to limitations of pins, signals are 9
multiplexed Intel 8085 (8 bit processor)
 Microprocessor Functional blocks

Various conditions of the

Computational Unit;
results are stored as
performs arithmetic and Internal storage of data
status bits called flags in
logic operations
flag register

Register array or Data Bus

internal memory
ALU
Generates the
address of the
Instruction
Flag instructions to be
decoding unit
Register fetched from the
memory and send
through address
bus to the
Timing and memory
control unit PC/ IP

Control Bus Address Bus

Generates control signals for Decodes instructions; sends

internal and external operations information to the timing and
of the microprocessor control unit 10
8086 Microprocessor
Features

It is 16- bit microprocessor Addressable memory space is

organized in to two banks of 512 kb
each; Even (or lower) bank and Odd (or
higher) bank. Address line A0 is used to
It has 20 address lines and hence can select even bank and control signal
access a memory of 220 = 1 megabytes is used to access odd bank
of memory space (1MB of memory)
Uses a separate 16 bit address for I/O
mapped devices  can generate 216 =
Approximately 29, 000 transistors, 40 64 k addresses.
pin DIP, 5V supply
Operates in two modes: minimum mode
and maximum mode, decided by the
Does not have internal clock; external signal at MN and pins.
asymmetric clock source with 33%
duty cycle It has 6 byte pre-fetch queue

It address ranges from 0000h- FFFFFH

It has multiplexed data and address
bus AD0 – AD15, A16/S3 – A19/S6

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8086 Architecture

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8086 Microprocessor
Architecture – BIU

Bus Interface Unit (BIU)

BIU fetches instructions, reads data from memory and I/O ports, writes
data to memory and I/ O ports.

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8086 Architecture – EU

Execution Unit (EU)

EU executes instructions that have already been fetched by the BIU.

BIU and EU functions separately.

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8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Dedicated Adder to
generate 20 bit address

Four 16-bit segment

registers

Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

Segment Registers >> 15

8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment
Registers

8086’s 1-megabyte The 8086 can directly Programs obtain access

memory is divided address four segments to code and data in the
into segments of up (256 K bytes within the 1 segments by changing
to 64K bytes each. M byte of memory) at a the segment register
particular time. content to point to the
desired segments.

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8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment Code Segment Register

Registers
16-bit

CS contains the base or start of the current code segment;

IP contains the distance or offset from this address to the
next instruction byte to be fetched.

BIU computes the 20-bit physical address by logically

shifting the contents of CS 4-bits to the left and then
adding the 16-bit contents of IP.

That is, all instructions of a program are relative to the

contents of the CS register multiplied by 16 and then
offset is added provided by the IP.

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8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment Data Segment Register

Registers
16-bit

Points to the current data segment; operands for most

instructions are fetched from this segment.

The 16-bit contents of the Source Index (SI) or

Destination Index (DI) or a 16-bit displacement are used
as offset for computing the 20-bit physical address.

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8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment Stack Segment Register

Registers
16-bit

Points to the current stack.

The 20-bit physical stack address is calculated from the

Stack Segment (SS) and the Stack Pointer (SP) for stack
instructions such as PUSH and POP.

In based addressing mode, the 20-bit physical stack

address is calculated from the Stack segment (SS) and the
Base Pointer (BP).

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8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment Extra Segment Register

Registers
16-bit

Points to the extra segment in which data (in excess of

64K pointed to by the DS) is stored.

String instructions use the ES and DI to determine the 20-

bit physical address for the destination.

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8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment Instruction Pointer

Registers
16-bit

Always points to the next instruction to be executed

within the currently executing code segment.

So, this register contains the 16-bit offset address pointing

to the next instruction code within the 64Kb of the code
segment area.

Its content is automatically incremented as the execution

of the next instruction takes place.

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8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Instruction queue

A group of First-In-First-
Out (FIFO) in which up to
6 bytes of instruction
code are pre fetched
from the memory ahead
of time.

This is done in order to

speed up the execution
by overlapping
instruction fetch with
execution.

This mechanism is known

as pipelining.

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 8086 Microprocessor
Architecture Execution Unit (EU)

EU decodes and
executes instructions.

A decoder in the EU
control system
translates instructions.

16-bit ALU for

performing arithmetic
and logic operation

Four general purpose

registers(AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);

and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 23
DX can be used as DH and DL
8086 Microprocessor
Architecture Execution Unit (EU)

EU Accumulator Register (AX)

Registers
Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.

AL in this case contains the low order byte of the word,

and AH contains the high-order byte.

The I/O instructions use the AX or AL for inputting /

outputting 16 or 8 bit data to or from an I/O port.

Multiplication and Division instructions also use the AX or

AL.

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8086 Microprocessor
Architecture Execution Unit (EU)

EU Base Register (BX)

Registers
Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.

BL in this case contains the low-order byte of the word,

and BH contains the high-order byte.

This is the only general purpose register whose contents

can be used for addressing the 8086 memory.

All memory references utilizing this register content for

addressing use DS as the default segment register.

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8086 Microprocessor
Architecture Execution Unit (EU)

EU Counter Register (CX)

Registers
Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.

When combined, CL register contains the low order byte of

the word, and CH contains the high-order byte.

Instructions such as SHIFT, ROTATE and LOOP use the

contents of CX as a counter.

Example:

The instruction LOOP START automatically decrements

CX by 1 without affecting flags and will check if [CX] =
0.

If it is zero, 8086 executes the next instruction;

otherwise the 8086 branches to the label START.

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8086 Microprocessor
Architecture Execution Unit (EU)

EU Data Register (DX)

Registers
Consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX.

When combined, DL register contains the low order byte of

the word, and DH contains the high-order byte.

Used to hold the high 16-bit result (data) in 16 X 16

multiplication or the high 16-bit dividend (data) before a
32 16 division and the 16-bit reminder after division.

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8086 Microprocessor
Architecture Execution Unit (EU)

EU Stack Pointer (SP) and Base Pointer (BP)

Registers
SP and BP are used to access data in the stack segment.

SP is used as an offset from the current SS during

execution of instructions that involve the stack segment in
the external memory.

SP contents are automatically updated (incremented/

decremented) due to execution of a POP or PUSH
instruction.

BP contains an offset address in the current SS, which is

used by instructions utilizing the based addressing mode.

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8086 Microprocessor
Architecture Execution Unit (EU)

EU Source Index (SI) and Destination Index (DI)

Registers
Used in indexed addressing.

Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.

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8086 Microprocessor
Architecture Execution Unit (EU)

EU Source Index (SI) and Destination Index (DI)

Registers
Used in indexed addressing.

Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.

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 8086 Microprocessor
Architecture Execution Unit (EU)
Auxiliary Carry Flag
Carry Flag
Flag Register This is set, if there is a carry from the
This flag is set, when there is
lowest nibble, i.e, bit three during
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Trap Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction

Direction Flag Interrupt Flag

This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
towards the lowest address, i.e., auto incrementing mode. 31
8086 Microprocessor
Architecture

8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

into 4 groups OF DF IF TF SF ZF AF PF CF

Sl.No. Type Register width Name of register

1 General purpose register 16 bit AX, BX, CX, DX

8 bit AL, AH, BL, BH, CL, CH, DL, DH

2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag (PSW) 16 bit Flag register

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8086 Microprocessor
Architecture Registers and Special Functions

Register Name of the Register Special Function

AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic

operations

AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic

operations

BX Base register Used to hold base value in base addressing mode

to access memory data

CX Count Register Used to hold the count value in SHIFT, ROTATE

and LOOP instructions

DX Data Register Used to hold data for multiplication and division

operations

SP Stack Pointer Used to hold the offset address of top stack

memory

BP Base Pointer Used to hold the base value in base addressing

using SS register to access data from stack
memory

SI Source Index Used to hold index value of source operand (data)

for string instructions

DI Data Index Used to hold the index value of destination

operand (data) for string operations 33
Memory Segmentation in 8086

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 Memory Segmentation in 8086

Segmentation is the process in which the main memory of the computer is divided into
different segments and each segment has its own base address. It is basically used to
enhance the speed of execution of the computer system, so that processor is able to
fetch and execute the data from the memory easily and fast.

Types Of Segmentation –
Overlapping Segment – A segment starts at a particular address and its maximum
size can go up to 64kilobytes. But if another segment starts along this 64kilobytes
location of the first segment, then the two are said to be Overlapping Segment.
Non-Overlapped Segment – A segment starts at a particular address and its
maximum size can go up to 64kilobytes. But if another segment starts before this
64kilobytes location of the first segment, then the two segments are said to be Non-
Overlapped Segment.

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 Memory Segmentation in 8086

Advantages of the Segmentation The main advantages of segmentation are as

follows:

•It provides a powerful memory management mechanism.

•Data related or stack related operations can be performed in

different segments.

•Code related operation can be done in separate code segments.

•It allows to processes to easily share data.

•It allows to extend the address ability of the processor, i.e.

segmentation allows the use of 16 bit registers to give an addressing
capability of 1 Megabytes. Without segmentation, it would require 20
bit registers.

•It is possible to enhance the memory size of code data or stack segments beyond 64
KB by allotting more than one segment for each area. 36
37
Dis advantages of the Segmentation:

Although there is I MB of memory is available – the segments can access only 4*64KB
= 256 KB at a time

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39
Example1

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Example2

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42
43
 Physical Address calculation of 8086

Physical address (PA) , Base Address

(BA), Offset Address (OA)

PA = 20bit Address
BA = 16 bit address , It is the starting
address of segment

OA = 16 bit address, It is the distance

or displacement from the start of the
segment

PA is calculated as

PA = (BA * 10H ) + OA

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45
46
Pins and signals
48
8086 Microprocessor
Pins and Signals Common signals

AD0-AD15 (Bidirectional)

Address/Data bus

Low order address bus; these are

multiplexed with data.

When AD lines are used to transmit

memory address the symbol A is used
instead of AD, for example A0-A15.

When data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

multiplexed with status signals

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8086 Microprocessor
Pins and Signals Common signals

BHE (Active Low)/S7 (Output)

Bus High Enable/Status

It is used to enable data onto the most

significant half of data bus, D8-D15. 8-bit
device connected to upper half of the
data bus use BHE (Active Low) signal. It
is multiplexed with status signal S7.

MN/ MX

MINIMUM / MAXIMUM

This pin signal indicates what mode the

processor is to operate in.

RD (Read) (Active Low)

The signal is used for read operation.

It is an output signal.
It is active when low.
50
8086 Microprocessor
Pins and Signals Common signals

TEST

input is tested by the ‘WAIT’ instruction.

8086 will enter a wait state after

execution of the WAIT instruction and
will resume execution only when the is
made low by an active hardware.

This is used to synchronize an external

activity to the processor internal
operation.

READY

This is the acknowledgement from the

slow device or memory that they have
completed the data transfer.

The signal made available by the devices

is synchronized by the 8284A clock
generator to provide ready input to the
8086.

The signal is active high. 51

8086 Microprocessor
Pins and Signals Common signals

RESET (Input)

Causes the processor to immediately

terminate its present activity.

The signal must be active HIGH for at

least four clock cycles.

CLK

The clock input provides the basic timing

for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.

INTR Interrupt Request

This is a triggered input. This is sampled

during the last clock cycles of each
instruction to determine the availability
of the request. If any interrupt request is
pending, the processor enters the
interrupt acknowledge cycle.

This signal is active high and internally

synchronized. 52
8086 Microprocessor
Pins and Signals Min/ Max Pins

The 8086 microprocessor can work in two

modes of operations : Minimum mode and
Maximum mode.

In the minimum mode of operation the

microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.

In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.

Minimum or maximum mode operations

are decided by the pin MN/ MX(Active
low).

When this pin is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.

53
8086 Microprocessor
Pins and Signals Minimum mode signals

Pins 24 -31

For minimum mode operation, the MN/ is tied to

VCC (logic high)

8086 itself generates all the bus control signals

DT/ (Data Transmit/ Receive) Output signal from the

processor to control the direction of data flow
through the data transceivers

(Data Enable) Output signal from the processor

used as out put enable for the transceivers

ALE (Address Latch Enable) Used to demultiplex the

address and data lines using external latches

M/ Used to differentiate memory access and I/O

access. For memory reference instructions, it is
high. For IN and OUT instructions, it is low.

Write control signal; asserted low Whenever

processor writes data to memory or I/O port

(Interrupt Acknowledge) When the interrupt

request is accepted by the processor, the output is
low on this line.
54
8086 Microprocessor
Pins and Signals Minimum mode signals

Pins 24 -31

For minimum mode operation, the MN/ is tied to

VCC (logic high)

8086 itself generates all the bus control signals

HOLD Input signal to the processor form the bus masters

as a request to grant the control of the bus.

Usually used by the DMA controller to get the

control of the bus.

HLDA (Hold Acknowledge) Acknowledge signal by the

processor to the bus master requesting the control
of the bus through HOLD.

The acknowledge is asserted high, when the

processor accepts HOLD.

55
8086 Microprocessor
Pins and Signals Maximum mode signals

During maximum mode operation, the MN/ is

grounded (logic low)

Pins 24 -31 are reassigned

,, Status signals; used by the 8086 bus controller to

generate bus timing and control signals. These are
decoded as shown.

56
8086 Microprocessor
Pins and Signals Maximum mode signals

During maximum mode operation, the MN/ is

grounded (logic low)

Pins 24 -31 are reassigned

, (Queue Status) The processor provides the status

of queue in these lines.

The queue status can be used by external device to

track the internal status of the queue in 8086.

The output on QS0 and QS1 can be interpreted as

shown in the table.

57
8086 Microprocessor
Pins and Signals Maximum mode signals

During maximum mode operation, the MN/ is

grounded (logic low)

Pins 24 -31 are reassigned

, (Bus Request/ Bus Grant) These requests are used

by other local bus masters to force the processor
to release the local bus at the end of the
processor’s current bus cycle.

These pins are bidirectional.

The request on will have higher priority than

An output signal activated by the LOCK prefix

instruction.

Remains active until the completion of the

instruction prefixed by LOCK.

The 8086 output low on the pin while executing an

instruction prefixed by LOCK to prevent other bus
masters from gaining control of the system bus.

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8086 Microprocessor
Memory organization in 8086

Memory IC’s : Byte oriented

8086 : 16-bit

Word : Stored by two

consecutive memory locations;
for LSB and MSB

Address of word : Address of LSB

Bank 0 : A0 = 0  Even
addressed memory bank

Bank 1 : = 0  Odd
addressed memory bank

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8086 Microprocessor
Memory organization in 8086

Operation A0 Data Lines Used

1 Read/ Write byte at an even address 1 0 D7 – D 0

2 Read/ Write byte at an odd address 0 1 D15 – D8

3 Read/ Write word at an even address 0 0 D15 – D0

4 Read/ Write word at an odd address 0 1 D15 – D0 in first operation

byte from odd bank is
transferred
1 0 D7 – D0 in first operation
byte from odd bank is 60
transferred
Memory organization in 8086

61
Memory organization in 8086

62
 8086 System configuration
in
Minimum mode and Maximum mode

63
8086 Minimum mode configuration:
8086 System configuration in Minimum mode

65
Minimum Mode 8086 System

1. In a minimum mode 8086 system, the microprocessor 8086 is operated in

minimum mode by strapping its MN/MX pin to logic 1.
2. In this mode, all the control signals are given out by the microprocessor chip itself.
There is a single microprocessor in the minimum mode system.
3. The remaining components in the system are latches, transreceivers, clock
generator, memory and I/O devices. Some type of chip selection logic may be
required for selecting memory or I/O devices, depending upon the address map of
the system.
4. Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They
are used for separating the valid address from the multiplexed address/data
signals and are controlled by the ALE signal generated by 8086.
5. Transreceivers are the bidirectional buffers and sometimes they are called as data
amplifiers. They are required to separate the valid data from the time multiplexed
address/data signals.
6. They are controlled by two signals namely, DEN and DT/R.
7. The DEN signal indicates the direction of data, i.e. from or to the processor. The
system contains memory for the monitor and users program storage.
66
8086 System configuration in Maximum mode

67
Maximum Mode 8086 System

1. In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.
2. In this mode, the processor derives the status signal S2, S1, S0. Another chip called
bus controller derives the control signal using this status information.
3. In the maximum mode, there may be more than one microprocessor in the system
configuration.
4. The components in the system are same as in the minimum mode system.
5. The basic function of the bus controller chip IC8288, is to derive control signals like
RD and WR (for memory and I/O devices), DEN, DT/R, ALE etc. using the information
by the processor on the status lines.
6. The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 are
driven by CPU.
7. It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and
AIOWC. The AEN, IOB and CEN pins are specially useful for multiprocessor systems.

68
 TIMING DIAGRAMS FOR 8086 IN MINIMUM MODE

BUS CYCLE AND TIME STATES

A bus cycle or machine cycle defines the sequence of events when the MPU
communicates with an external device, which starts with an address being output
on the system bus followed by a read or write data transfer.

Types of bus cycles:

1. Memory Read Bus Cycle
2. Memory Write Bus Cycle
3. Input/output Read Bus Cycle
4. Input/output Write Bus Cycle

One cycle of clock is called a state or t-state. The bus cycle of the 8086
microprocessor consists of at least four clock periods. These four time states are
called T1, T2, T3 and T4. This group of states is called a MACHINE CYCLE.

The total time required to fetch and execute an instruction is called an instruction
cycle. An instruction cycle consists of one or more machine cycle

69
Read timing diagram in Minimum Mode

70
Read timing diagram in Minimum Mode

71
 Write operation with Wait state (Tw)

Note: Wait state Tw is always included between T3 and T4 states

72
memory read cycle of the 8086

73
The following figure shows a memory read cycle of the 8086:

 During period T1: The 8086 outputs the 20-bit address of the memory location to be
accessed on its multiplexed address/data bus. BHE is also output along with the address
during T1. At the same time a pulse is also produced at ALE. The trailing edge or the high
level of this pulse is used to latch the address in external circuitry. Signal M/IO is set to logic 1
and signal DT/R is set to the 0 logic level and both are maintained throughout all four periods
of the bus cycle.

 Beginning with period T2: Status bits S3 through S6 are output on the upper four address
bus lines. This status information is maintained through periods T3 and T4.
On the other hand, address/data bus lines AD0 through AD7 are put in the high-Z state during
T2. Late in period T2, RD is switched to logic 0. This indicates to the memory subsystem that
a read cycle is in progress. DEN is switched to logic 0 to enable external circuitry to allow the
data to move from memory onto the microprocessor's data bus.

 During period T3: The memory must provide valid data during T3 and maintain it until
after the processor terminates the read operation. The data read by the 8086 microprocessor
can be carried over all 16 data bus lines.

 During T4: The 8086 switches RD to the inactive 1 logic level to terminate the read
operation. DEN returns to its inactive logic level late during T4 to disable the external
circuitry.
74
TIMING DIAGRAMS FOR 8086 IN MAXIMUM MODE

75
WRITE CYCLE IN MAXIMUM MODE

76
WRITE CYCLE IN MAXIMUM MODE

77
 Maximum Mode 8086 System

Maximum Mode 8086 System

1. In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.
2. In this mode, the processor derives the status signal S2, S1, S0. Another chip called
bus controller derives the control signal using this status information.
3. In the maximum mode, there may be more than one microprocessor in the system
configuration.
4. The components in the system are same as in the minimum mode system.
5. The basic function of the bus controller chip IC8288, is to derive control signals like
RD and WR (for memory and I/O devices), DEN, DT/R, ALE etc. using the information
by the processor on the status lines.
6. The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 are
driven by CPU.
7. It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and
AIOWC. The AEN, IOB and CEN pins are specially useful for multiprocessor systems.

78
 Interrupt, ISR, IVT

• Interrupt :
An INTERRUPT is a condition that causes the microprocessor to temporarily
work on a different task and then return to its previous task. Interrupt is an
event or signal that request to attention of CPU.

• Interrupt is the method of creating a temporary halt during program

execution and allows peripheral devices to access the microprocessor.

79
80
• Whenever an interrupt occurs the processor completes the
execution of the current instruction and starts the execution of an
Interrupt Service Routine (ISR) or Interrupt Handler.
• ISR is a program that tells the processor what to do when the
interrupt occurs.
• After the execution of ISR, control returns back to the main routine
where it was interrupted.

81
Interrupts are useful when interfacing I/O devices with low data-transfer rates,
like a keyboard or a mouse, in which case polling the device wastes valuable
processing time

Below time line shows typing on a keyboard, a printer removing data from memory,
and a program executing. The keyboard interrupt service procedure, called by the
keyboard interrupt, and the printer interrupt service procedure each take little time
to execute

83
Types of Interrupts
In general there are two types of Interrupts:
 Internal (or) Software Interrupts are triggered by a software instruction and
operate similarly to a jump or branch instruction.
 External (or) Hardware Interrupts are caused by an external hardware
module.

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 Software Interrupts

• Software Interrupts are the internal interrupts that are triggered by a

software instruction and operate similarly to a jump or branch instruction.

• These software interrupts are initiated when an “INT n” Instruction is

executed. Where n is indicates the specified type number.

• There are 256 software interrupts supported by 8086.

• Hence the value n ranges from 0 - 255 (00h - FFh)
• Out of 256, the first 5 interrupts (INT 00 h– INT 04h) are predefined
interrupts of 8086
• The next 27 interrupts (INT 05h – INT 1Fh) are reserved by INTEL
• The remaining 224 interrupts (INT 20h – INT FFh) are available to user

• The 8086 will push the flag register on the stack, reset TF and IF, and push
the CS and IP values of the next instruction on the stack.

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Divide-By-Zero Interrupt-Type 0:
The 8086 will automatically do a type 0 interrupt if the result of a DIV
operation or an IDIV operation is too large to fit in the destination
register. For a type 0 interrupt, the 8086 pushes the flag register on the
stack, resets IF and TF and pushes the return addresses on the stack.

Single Step Interrupt-Type 1:

The use of single step execution feature is found in some of the
monitor & debugger programs. When we tell a system to single step, it
will execute one instruction and stop. We can then examine the
contents of registers and memory locations.

In other words, when in single step mode a system will stop after it
executes each instruction and wait for further direction from user. The
8086 trap flag and type 1 interrupt response make it quite easy to
implement a single step feature direction.

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• Non-maskable Interrupt-Type 2:
The 8086 will automatically do a type 2 interrupt response when it
receives a low to high transition on its NMI pin. When it does a type
2 interrupt, the 8086 will push the flags on the stack, reset TF and
IF, and push the CS value and the IP value for the next instruction
on the stack. It will then get the CS value for the start of the type 2
interrupt service procedure from address 0000AH and the IP value
for the start of the procedure from address 00008H.

Breakpoint Interrupt-Type 3:
The type 3 interrupt is produced by execution of the INT3
instruction. The main use of the type 3 interrupt is to implement a
breakpoint function in a system. Whenever we insert a breakpoint,
the system executes the instructions up to the breakpoint and then
goes to the breakpoint procedure.

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Overflow Interrupt-Type4:
The 8086 overflow flag will be set if the signed result of an
arithmetic operation on two signed numbers is too large to
be represented in the destination register or memory
location.

Example: If we add the 8 bit signed number 01101100 and

the 8 bit signed number 010111101, the result will be
10111101. This would be the correct result if we were
adding unsigned binary numbers, but it is not the correct
signed result.

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8086 Interrupt Response

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• It decrements stack pointer by 2 and pushes the flag register on the
stack..
• It disables the INTR interrupt input by clearing the interrupt flag in
the flag
• It resets the trap flag in the flag register.
• It decrements stack pointer by 2 and pushes the current code
segment register contents on the stack.
• It decrements stack pointer by 2 and pushes the current instruction
pointer contents on the stack.
• It does an indirect far jump at the start of the procedure by loading
the CS and IP values for the start of the interrupt service routine (ISR).
• An IRET instruction at the end of the interrupt service procedure
returns execution to the main program.

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 Interrupt, ISR, IVT

• Interrupt :
An INTERRUPT is a condition that causes the microprocessor to temporarily
work on a different task and then return to its previous task. Interrupt is an
event or signal that request to attention of CPU.

• Interrupt is the method of creating a temporary halt during program

execution and allows peripheral devices to access the microprocessor.

Interrupt Service Routines (ISR): Whenever an Interrupt occurs the CPU has to
executes a set of specific instructions. So the program that is required for these
tasks is called the Interrupt Service Routines(ISR). Each Interrupt should have a
corresponding ISR

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Interrupt Vector Table: Whenever the processor receives an
Interrupt, the corresponding ISR has to be executed. IVT
contains the starting address of 256 ISRs, these consists of
Base address and Offset address. The first 1KB (ie., from
00000h – 003FFFh)out of 1MB of 8086 is reserved for IVT.

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Hex to Decimal Conversion Program in
Microprocessor 8086

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Palindrome Program in Microprocessor 8086

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Character Replace Program in Microprocessor 8086

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Time Display using DOS Function Program in Microprocessor 8086

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THANK YOU

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