MODULE_5

Linear IC based circuits.

1
 Linear IC based circuits.
Contents:
Op-Amp Circuits:

5.1:DAC – Digital to Analog Converters

• 5.1.1 Weighted resistor and
• 5.1.2 R-2R ladder,

5.2: ADC- Analog to Digital Converters

5.2.1 Successive approximation type,
5.3 Small Signal half wave rectifier, 2
 Contents
5.4: Active Filters,
5.4.1 First and second order low-pass and
5.4.3 Highpass Butterworth filters,
5.4.4 Band-pass filters,
5.4.5 Band reject filters.

5.5: 555 Timer and its applications:

5.5.1 Monostable and
5.5.2 a stable Multivibrators.
3
Text Book_2:
8.11(8.11.1a, 8.11.1b), 8.11.2a, 8.12.2,
7.2, 7.3, 7.4, 7.5, 7.6, 7.8, 7.9,
9.4.1, 9.4.1(a), 9.4.3, 9.4.3(a).

Text Books:

2. Op-Amps and Linear Integrated Circuits,

Ramakant A Gayakwad, 4th Edition. Pearson
Education, 2000.
ISBN: 8120320581
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6
7
 DAC –
WEIGHTED RESISTOR AND
R-2R LADDER:

i) DAC - WEIGHTED RESISTOR:

8
i) DAC Converter with binary Weighted resistors:

Fig: D/A converter with binary weighted resistors 9

A D/A converter using binary-weighted resistors
is shown in the figure
 In the circuit, the op-amp is connected in the
inverting mode.
 The op-amp can also be connected in the non-
inverting mode.
 Since the number of binary input is four, the
convertor is called as 4-bit (binary digit)
converter.
 Because there are 16 (24) combinations of
binary inputs for b0 to b3, an analog output
should have 16 possible corresponding values.
10
Working:

 When switch b0 is closed (connected to +5V):

• The voltage across R is 5V because of
V2=V1=0V.
• Therefore the current through R is
I0 = 5V/10KΩ=0.5mA
• However, input bias current IB is negligible;
hence the current (IF) through feedback
resistor RF is also IF = 0.5mA, which in turn
produces an output voltage of
• VO = – (1 KΩ) (0.5mA) = -0.5V 11
 When switch b1 is closed and b0 is open:

• This connects R/2 to the positive supply of +5V,

• Therefore current through R/2 is
I1 = 5V/5KΩ = 1mA.
• Hence, the current through feedback resistor RF
is also IF = 1mA, which in
turn produces an output voltage of
VO = – (1 KΩ) (1mA) = -1V.

 If both switch b0 and b1 are closed:

• The current through RF will be

IF = I0 + I1 = (0.5mA) + (1mA) = 1.5mA
• Hence, the output voltage 12
Hence depending on whether switches b0 to b3
are open or closed,
The binary-weighted currents will be set up in
the input resistors.
 The sum of these currents is equal to the
current through RF, which in turn is
converted to a proportional output voltage.

 When all the switches are closed, the output

will be maximum.
The output voltage equation is given by

13
Where each of the inputs b3, b2, b1, and b0 may
either be high (+5V) or low (0V)

 The below graph shows the analog outputs

versus possible combinations of inputs.
 The output is a negative-going staircase
waveform with 15 steps of -0.5V each.

 The drawback of weighted resistor DAC is

that it requires binary-weighted resistors, which
may not be readily available, especially if the
number of inputs is more than four
14
The below graph shows the analog outputs versus
possible combinations of inputs.

15
Advantages:

• It is Simple in Construction.

• It provides fast conversion.

Disadvantages:

• This type requires large range of resistors with

necessary high precision for low resistors.
•  Requires low switch resistances in transistors.
• Can be expensive. Hence resolution is limited to
8-bit size.

16
 ii) DAC CONVERTER
WITH R-2R RESISTORS:

17
R-2R Resistive Ladder Network
• As its name implies, the “ladder” description comes
from the ladder-like configuration of the resistors
used within the network.
• A R-2R resistive ladder network provides a simple
means of converting digital voltage signals into an
equivalent analogue output.
• Input voltages are applied to the ladder network at
various points along its length and the more input
points the better the resolution of the R-2R ladder.
• The output signal as a result of all these input
voltage points is taken from the end of the ladder
which is used to drive the inverting input of an
operational amplifier.
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Then a R-2R resistive ladder network is nothing
more than long strings of parallel and series
connected resistors acting as interconnected
voltage dividers along its length, and whose output
voltage depends soley on the interaction of the
input voltages with each other.

Consider the basic 4-bit R-2R ladder network (4-

bits because it has four input points) below.

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ii. DAC CONVERTER WITH R-2R RESISTORS:

20
 The figure shows a D/A converter with R and 2R
resistors.
 The binary inputs are simulated by switches b0
through b3, and the output is proportional to the
binary inputs.
 Binary inputs can be in either the high (+5V) or low
(0V) state.
 Assume that the most significant bit (MSB) switch
b3 is connected to +5V and other switches are
connected to ground, as shown in the figure

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 By applying Thevenin's theorem for the R-2R ladder
circuit, Equivalent resistance RTH is calculated as
𝑅𝑇𝐻 = [{[(2𝑅 || 2𝑅 + 𝑅 )|| 2𝑅] + 𝑅 }|| 2𝑅 ]+ 𝑅 = 2𝑅 =
20𝑘Ω
 The resultant circuit after applying Thevenin's
theorem is as shown below

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 In the figure shown above, the negative input is
at virtual ground;
therefore the current through RTH is 0A.
 The Current through 2R connected to +5V is
𝐼 = 5𝑉 20𝑘 Ω = 0.25𝑚𝐴
The same current I flows through RF and in turn
produces the output voltage of
𝑉𝑂 = − 20𝑘Ω 0.25𝑚𝐴 = −5𝑉

 Using the same analysis, the output voltage

when all the switches are connected to +5V can
be calculated as

23
Where each of the inputs b3, b2, b1, and b0 may be
either high (+5V) or low (0V).
 The below graph shows the analog outputs versus
possible combinations of

inputs.

24
Advantages:
• Only two resistor values are used in R-2R ladder type.
• It does not need as precision resistors as Binary
weighted DACs.
• It is cheap and easy to manufacture.

Disadvantages:
• It has slower conversion rate.

For N bit DAC:

•  Number of different levels = 2N
•  Number of Steps = 2N - 1

Resolution or step size of DAC = Analog output/Number

of steps = Va/( 2N - 1 ) 25
4-bit R-2R Resistive Ladder Network

26
This 4-bit resistive ladder circuit may look
complicated, but its all about connecting resistors
together in parallel and series combinations and
working back to the input source using simple circuit
laws to find the proportional value of the output.
Lets assume all the binary inputs are grounded at 0
volts, that is: VA = VB = VC = VD = 0V (LOW).
The binary code corresponding to these four inputs
will therefore be: 0000.

27
Starting from the left hand side and using the simplified
equation for two parallel resistors and series resistors, we can
find the equivalent resistance of the ladder network as

Resistors R1 and R2 are in “parallel” with each other but in

“series” with resistor R3. Then we can find the equivalent
resistance of these three resistors and call it RA for simplicity (or
any other form of identification you want).

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Then RA is equivalent to “2R”. Now we can see that the
equivalent resistance “RA” is in parallel with R4 with the parallel
combination in series with R5.

Again we can find the equivalent resistance of this

combination and call it RB.

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 So RB combination is equivalent to “2R”. Hopefully we can see
that this equivalent resistance RB is in parallel with R6 with the
parallel combination in series with R7 as shown.

As before we find the equivalent resistance and call it RC.

30
Again, resistor combination RC is equivalent to “2R” which is
in parallel with R8 as shown

when two equal resistor values are paralled together, the

resulting value is one-half, so 2R in parallel with 2R equals an
equivalent resistance of R. So the whole 4-bit R-2R resistive
ladder network comprising of individual resistors connected
together in parallel and series combinations has an equivalent
resistance (REQ) of “R” when a binary code of “0000” is applied to
its four inputs. 31
R-2R DAC Circuit with Four Zero (LOW) Inputs

The ouput voltage for an inverting operational amplifier is given

as: (RF/RIN)*VIN.
If we make RF equal to R, that is RF = R = 1, and as R is
terminated to ground (0V), then there is no VIN voltage value,
(VIN = 0) so the output voltage would be: (1/1)*0 = 0 volts. So for
a 4-bit R-2R DAC with four grounded inputs (LOW), the output
voltage will be “zero” volts, thus a 4-bit digital input
of 0000 produces an analogue output of 0 volts. 32
 R-2R DAC with Input VA

Input VA is HIGH and logic level “1” and all the other inputs
grounded at logic level “0”. As the R/2R ladder network is a
linear circuit we can find Thevenin’s equivalent resistance using
the same parallel and series resistance calculations as above to
calculate the expected output voltage. The output voltage,
VOUT is therefore calculated at 312.5 milli-volts (312.5 mV). 33
• As we have a 4-bit R-2R resistive ladder network,
this 312.5 mV voltage change is one-sixteenth the
value of the +5V input (5/0.3125 = 16) voltage so is
classed as the Least Significant Bit, (LSB).

• Being the least significant bit, input VA will therefore

determine the “resolution” of our simple 4-bit
digital-to-analogue converter, as the smallest
voltage change in the analogue output corresponds
to a single step change of the digital inputs.

• Thus for our 4-bit DAC this will be 312.5mV (1/16th)

for a +5V input.

34
 R-2R DAC with Input VB

With input VB HIGH and logic level “1” and all the other inputs
grounded at logic level “0”, the output voltage, VOUT is calculated
at 625mV, and which is one-eighth (1/8th) the value of the +5V
input (5/0.625 = 8) voltage.

We can also see that it is double the output voltage when only
input bit VA was applied, and we would expect this as its the
2nd bit (input) so has double the weighting of the 1st bit. 35
R-2R DAC with Input VC

.With input VC HIGH and logic level “1” and the other input bits
at logic level “0”, the output voltage, VOUT is calculated at 1.25
volts, and which is one-quarter (1/4) the value of the +5V input
(5/1.25 = 4) voltage.
.Again we can see that this voltage is double the output of input
bit VB but also 4 times the value of bit VA.
• This is because input VC is the 3rd bit so has double the
weighting of the 2nd bit and four times the weighting of the 36
 R-2R DAC with Input Vd

With only input VD HIGH and logic level “1” and the other inputs
at logic level “0”, the output voltage, VOUT is calculated at 2.5
volts. This is on-half (1/2) the value of the +5V input (5/2.5 = 2)
voltage.
Again we can see that this voltage is double the output of input
bit VC, 4 times the value of bit VB and 8 times the value of input
bit VA as it is the 4th bit and therefore classed as the Most
37
Significant Bit, (MSB).
Digital-to-Analogue Output Voltage Equation

• Where the denominator value of 16 corresponds to

the 16 (24) possible combinations of inputs to the
4-bit R-2R ladder network of the DAC.
• We can expand this equation further to obtain a
generalised R-2R DAC equation for any number of
digital inputs for a R-2R D/A converter as the
weighting of each input bit will always be
referenced to the least significant bit (LSB), giving
us a generalised equation of: 38
 Generalised R-2R DAC Equation

Where: “n” represents the number of digital inputs

within the R-2R resistive ladder network of the DAC
producing a resolution of: VLSB = VIN/2n.
• Clearly then input bit VA when HIGH will cause the
smallest change in the output voltage,
• while input bit VD when HIGH will cause the
greatest change in the output voltage.
• The expected output voltage is therefore calculated
by summing the effect of all the individual input bits
which are connected HIGH. 39
4-bit R-2R D/A Converter Output

40
41
Notice that the full-scale analogue output voltage for
a binary code of 1111 never reaches the same value
as the digital input voltage (+5V) but is less by the
equivalent of one LSB bit, (312.5mV in this example).
• However, the higher the number of digital input
bits (resolution) the nearer the analogue output
voltage reaches full-scale when all the input bits
are HIGH.
• Likewise when all the input bits are LOW, the
resulting lower resolution of LSB makes
VOUT closer to zero volts.

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 Analog to Digital Converter
Circuit

SUCCESSIVE-APPROXIMATION
A/D CONVERTER:

43
What is an analog-digital converter?
The output of a microphone, the voltage at a
photodiode or the signal of an accelerometer are
examples of analog values that need to be converted so
that a microprocessor can work with them. light
entering a digital camera, into a digital signal.

Application of ADC
• Used in computer to convert the analog signal to
digital signal.
• Used in cell phones.
• Used in microcontrollers.
• Used in digital signal processing

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 ADC’s Analog-to-Digital Converters basics
• As much as it’s an analog world, it is often
being chopped up into digital pieces.

• As communications go digital and the

computing power increases, signals are being
transformed into digital words that are easier to
transmit and compute mathematically.

• The process of converting signals is an analog

to digital process that gave rise to Analog-to-
Digital Converters or ADCs.

45
 Just what does an
A/D converter DO?

• Converts analog signals into binary words

ADC process

2 steps
 Sampling and Holding (S/H)
 Quantizing and Encoding (Q/E)
47
 Sampling and
Holding

• Holding signal benefits

the accuracy of the A/D
conversion

• Minimum sampling rate

should be at least twice
the highest data

frequency of the analog 48

signal
 Data-Converter Circuits
Because digital integrated
circuits are economical and
accurate, it is convenient to
process signals in digital
form, for example, to
perform algebraic
manipulations, to transmit
or store signals.

Figure 9.36 The process of periodically sampling an analog signal. (a) Sample-and-hold (S/H) circuit. The switch closes for a small part ( t seconds)
of every clock period (T). (b) Input signal waveform. (c) Sampling signal (control signal for the switch). (d) Output signal (to be fed to A/D 49
converter).
A digital signal synchronizes to a clock frequency.
According the Nyquist criteria, ADCs sample at a rate
of at least twice the highest frequency of the analog
input signal that is to be digitized. This frequency is
called the Nyquist sampling rate.

50
Analog → Digital Conversion
2-Step Process:

⚫ Quantizing - breaking down analog value is a

set of finite states.

⚫ Encoding - assigning a digital word or number to

each state and matching it to the input signal.

51
Step 1: Quantizing

Example:

• You have 0-10V signals.

• Separate them into a set of
discrete states with 1.25V
increments. (How did
we get 1.25V? See
next slide…)

52
Quantizing
• The number of possible states that the
converter can output is: N=2n

• where n is the number of bits in the AD converter

Example:
• For a 3 bit A/D converter, N=23=8.
Analog quantization size:

Q=(Vmax-Vmin) / N = (10V – 0V) / 8 = 1.25V

53
Step 2: Encoding
⚫ Here we assign the
digital value (binary
number) to each
state for the
computer to read.

54
 Accuracy of A/D Conversion
There are two ways to best improve accuracy of
A/D conversion:

⚫ increasing the resolution which improves the

accuracy in measuring the amplitude of the
analog signal.

⚫ increasing the sampling rate which increases the

maximum frequency that can be measured

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Resolution:
⚫ Resolution (number of discrete values the converter
can produce) = Analog Quantization size (Q)
(Q) = Vrange / 2n,
where Vrange is the range of analog voltages which
can be represented

⚫ limited by signal-to-noise ratio (should be around

6dB)

⚫ In our previous example: Q = 1.25V, this is a high

resolution. A lower resolution would be if we used a 2-
bit converter, then the resolution would be
10/22 = 2.50V.
56
Sampling Rate
Frequency at which ADC evaluates analog signal. As we
see in the second picture, evaluating the signal more often
more accurately depicts the ADC signal.

57
ADC granularity increases with sampling rate and
resolution as shown in the diagram below. The y axis is
the resolution which is actually the number of bits of
the ADC. The x axis is the sampling rate.

ADC Accuracy
Depends on the
Sampling Rate
and Resolution

58
The basic types of ADCs include:

1. Flash ADC.
2. Sigma-delta ADC.
3. Dual slope converter.
4. Successive approximation converter.

59
1. Flash ADC
⚫ Consists of a series of comparators, each one
comparing the input signal to a unique reference voltage.

⚫ The comparator outputs connect to the inputs of a

priority encoder circuit, which produces a binary output
Advantages
• Simplest in terms of operational theory
• Most efficient in terms of speed, very fast
( limited only in terms of comparator and gate propagation delays)
• Disadvantages
• Lower resolution
• Expensive
• For each additional output bit, the number of comparators is
Doubled ( i.e. for 8 bits, 256 comparators needed).
60
2. Sigma Delta ADC
⚫ Over sampled input signal goes to the Integrator

⚫ Output of integration is compared to GND

⚫ Iterates to produce a serial bit stream

⚫ Output is serial bit stream with # of 1’s proportional

to Vin

• Advantages
Disadvantages
• High resolution • Slow due to oversampling
• No precision external
61
components needed
3. Dual Slope Converter

⚫ The sampled signal charges a capacitor for a fixed

amount of time
⚫ By integrating over time, noise integrates out of the
Conversion

⚫ Then the ADC discharges the capacitor at a fixed

rate with the counter counts the ADC’s output bits. A
longer discharge time results in a higher count 62
 Comparison of ADC Technologies
ADCs are chosen based on speed and accuracy. The more bits in
the ADC, the higher the accuracy and the slower it is as each bit
adds a clock cycle. The various types of ADCs are compared for
speed and accuracy in the following figure:

63
 Successive approximation
• A successive-approximation ADC uses a comparator
and a binary search to successively narrow a range
that contains the input voltage.

• At each successive step, the converter compares the

input voltage to the output of an internal 
digital to analog converter which initially represents
the midpoint of the allowed input voltage range.

• At each step in this process, the approximation is

stored in a successive approximation register (SAR)
and the output of the digital to analog converter is
updated for a comparison over a narrower range. 64
SUCCESSIVE-APPROXIMATION A/D
CONVERTER:

65
 The figure shows a successive approximation type of
A/D converter.
 A successive approximation A/D converter consists of a
comparator, a successive approximation register (SAR),
output latches, and a D/A converter.
 The main part of the circuit is the 8-bit SAR, whose
output is given to an 8-bit D/A converter.
 The analog output Va of the D/A converter is then
compared to an analog signal Vin by the comparator.
 The output of the comparator is the serial data input to
the SAR.
 The SAR then adjusts its digital output (8-bits) until it
is equivalent to analog input Vin.
 The 8-bit latch at the end of the conversation holds onto
the resultant digital data output. 66
 Working of successive-approximation A/D
converter:
 At the start of a conversion cycle, the SAR is reset by
making the start signal (S) high.
 The MSB of the SAR (Q7) is set as soon as the first
transition from LOW to HIGH is introduced.
 The output is given to the D/A converter which
produces an analog equivalent of the MSB and is
compared with the analog input Vin.
 If comparator output is LOW, D/A output will be
greater than Vin and the MSB will be cleared by the SAR.
 If comparator output is HIGH, D/A output will be less
than Vin and the MSB will be set to the next position (Q7
to Q6) by the SAR.
67
 Working of successive-approximation

 According to the comparator output, the SAR will

either keep or reset the Q6 bit.
 This process goes on until all the bits are tried.
 After Q0 is tried, the SAR makes the conversion
complete (CC) signal HIGH to show that the parallel
output lines contain valid data.
 The CC signal, in turn, enables the latch, and digital
data appear at the output of the latch.
 As the SAR determines each bit, digital data is also
available serially.
 As shown in the figure above, the CC signal is
connected to the start conversion input to convert the
cycle continuously
68
Input and Output waveform

69
Working of successive-approximation

First case set the MSB bit

Where,
Set = 1
If. Vin > VA
Reset = 0
Set the next bit.

If. Vin < VA

Then reset the previous bit
And set the next bit

70
71
 Successive Approximation
Advantages
⚫ Capable of high speed and reliable
⚫ Medium accuracy compared to other ADC types
⚫ Good tradeoff between speed and cost
⚫ Capable of outputting the binary number in serial (one
bit at a time) format.

Disadvantages
⚫ Higher resolution successive approximation ADC’s will
be slower
⚫ Speed limited to ~5Msps
72
 SMALL-SIGNAL HALF-WAVE

RECTIFIERS:

i. Positive small-signal half-wave rectifier circuit:

ii. Negative small-signal half-wave rectifier

circuit

73
i). Positive small-signal half-wave
rectifier circuit

Fig: Positive small-signal HWR 74

 Fig: Input and Output Waveform

• A positive small-signal half-wave rectifier is shown in

the figure.
• The resultant circuit can rectify signals with peak
values down to a few millivolts.
• D1 is used in the feedback path and the analysis can
be done for input Vin> 0V and Vin< 0 V. 75
 Positive small-signal HWR.....
Case 1 : Vin> 0V:

• Consider the input to be positive going.

• As Vin starts increasing in the positive
direction, the VOA also starts increasing
positively until diode D1 is forward biased.
• When D1 is forward biased, it closes a feedback
loop and the op-amp works as a voltage
follower.
• Therefore, the output voltage VO follows the
input voltage Vin during the positive half-cycle
as shown in the output waveform 76
 Positive small-signal HWR.....
Case 2: Vin< 0V:
• When Vin starts increasing in a negative direction,
VOA, also increases negatively until it is equal to
negative saturation voltage (Vsat≅-VEE).
• This reverse biases diode D1 and opens the feedback
loop as shown in the below figure.
• Therefore, during negative half-cycle of the input
signal, VO is 0V

77
ii. Negative small-signal half-wave
rectifier circuit:

Fig: Negative small-signal HWR 78

 Negative small-signal HWR
• The resultant circuit can rectify signals with peak
values down to a few millivolts.
• D1 is used in the feedback path and the analysis can
be done for input Vin> 0V and Vin< 0 V.

Fig: Input and

Output Waveform 79
Case 1 : Vin> 0V: Negative small-signal HWR

• When Vin starts increasing in a positive direction, VOA,

also increases positively until it is equal to positive
saturation voltage (Vsat≅VCC).
• This reverse biases diode D1 and opens the feedback
loop as shown in the below figure.
• Therefore, during positive half-cycle of the input
signal, VO is 0V

80
 Negative small-signal HWR

Case 2: Vin< 0V:

• When the input is negative-going.

• As Vin starts increasing in the negative direction, the
VOA also starts increasing negatively until diode D1 is
forward biased.
• When D1 is forward biased, it closes a feedback loop
and the op-amp works as a voltage follower.

• Therefore, the output voltage VO follows the input

voltage Vin during the negative half-cycle as shown in
the output waveform.
81
 5.4: ACTIVE FILTERS:
5.4.1: FIRST ORDER_ LOW-PASS BUTTERWORTH
FILTER:
5.4.2: SECOND ORDER_ LOW-PASS
BUTTERWORTH FILTER:
5.4.3: FIRST ORDER_HIGH-PASS BUTTERWORTH
FILTER:
5.4.4: SECOND ORDER_ HIGH-PASS
BUTTERWORTH FILTER:
5.4.5: BAND-PASS FILTERS
5.4.5: BAND-REJECT FILTERS

82
 ACTIVE FILTERS:
An electric filter is often a frequency selective circuit
that passes a specified band of frequencies and blocks or
alternates signals and frequencies outside this band.

Filters may be classified as

1. Analog or digital.
2. Active or passive
3. Audio (AF) or Radio Frequency (RF)

83
1. Analog or digital filters:
• Analog filters are designed to process analog signals,
• while digital filters process analog signals using the
digital technique.

2. Active or Passive:
• Depending on the type of elements used in their
construction, a filter may be
• classified as passive or active
1) Elements used in passive filters are Resistors,
capacitors, inductors.
2) Elements used in active filters are transistor or op-
amp.
84
Active filters offer the following advantages
over passive filters:
1. Gain and Frequency adjustment flexibility:
Since the op-amp is capable of providing a gain, the i/p
signal is not attenuated as it is in a passive filter. [Active
filter is easier to tune or adjust].
2. No loading problem:
Because of the high input resistance and low o/p
resistance of the op-amp, the active filter does not cause
the loading of the source or load.
3. Cost:
Active filters are more economical than the passive filter.
This is because of the variety of cheaper op-amps and
the absence of inductors. 85
The most commonly used filters are
these:

1. Low pass Filters

2. High pass Filters
3. Band pass filters
4. Band reject filters
5. All pass filters.

86
The frequency response of the active filters:

87
1. Low Pass Filter:
• It has a constant gain from 0 Hz to a high cutoff
frequency f1.
• At fH the gain in down by 3db.
• The frequency between 0Hz and fH is known as the
passband frequencies.
Whereas the range of frequencies beyond fH, that are
attenuated includes the stopband frequencies.
• Butterworth, Chebyshev, and causer filter are some of
the most commonly used practical filters.
• The key characteristic of the butter worth filter is
that it has a flat passband as well as a stop band. For
this reason, it is sometimes called flat-flat filters.
88
• Chebyshev filter -> has a ripple pass band & flat
stopband.
• Causer Filter -> has a ripple pass band & ripple
stopband. It gives the best stopband response among
the three.

2. High pass filter:

• High pass filter with a stop band 0 < f < fL and a
passband f > fL
• Where fL – low cut off frequency and f –operating
frequency.
3. Band pass filter:
• It has a passband between 2 cut off frequencies fH
and where fH > fL and two, stopbands : 0<f< fL and
f > fH between the bandpass filter (equal to fH - fL). 89
4. Band –reject filter (Band stop or Band
elimination):

• It performs exactly opposite to the bandpass.

•
• It has a band stop between 2 cut-off
frequency fL and fH and 2 passbands:
•
0<f< fL and f > fH fC -> center frequency.

90
5.4.1: FIRST ORDER_ LOW-PASS
BUTTERWORTH FILTER:

91
 FIRST ORDER LOW-PASS BUTTERWORTH
FILTER:

Fig:First order LPF Butterworth Fig: LPF Frequecy response

filter circuit
92
Figure shows a first-order low-pass Butterworth filter
that uses an RC network for filtering.
• op-amp is used in the non inverting configuration.
• Resistor R1 & Rf determine the gain of the filter.
• According to the voltage –divider rule, the voltage at
the non-inverting terminal (across capacitor) C is:

Simplifying the above equation we get

93
And the output voltage of the non inverting
amplifier circuit is,

94
The gain magnitude and phase angle equations of the
low-pass filter can be obtained by converting the above
equation into its equivalent polar form, we get

95
The operation of the low-pass filter can be verified
from the gain magnitude equation:

1. At very low frequencies, that is, f < fH

2. At f = fH ,

3. At f > fH ,

96
• Thus the low-pass filter has a constant gain
Af
from 0 Hz to the high cutoff frequency fH.

• At fH the gain is 0.707Af, and after fH it

decreases at a constant rate with an increase
in frequency as shown in the frequency
response

97
Filter Design First Order LPF Butterworth
Filter:
A low-pass filter can be designed by
implementing the following steps:
• Choose a value of high cutoff frequency fH.

• Select a value of C less than or equal to 1µF.

• Calculate the value of R using R = 1 / 2𝜋fH C

• Finally, select values of R1 and RF dependent

on the desired passband gain Af using.
A = 1 +( R / R )
98
5.4.2: SECOND ORDER_ LOW-
PASS BUTTERWORTH
FILTER:

99
 SECOND ORDER_ LOW-PASS
BUTTERWORTH FILTER:

Fig: Second order LPF

Fig: LPF Frequecy response
Butterworth filter circuit 100
Figure shows a Second-order low-pass Butterworth
filter that uses an RC network for filtering.

• A first order low-pass filter can be converted second

order type by using an additional RC network, as
shown in figure.
• A stop-band response having a 40-db/decade roll-off
is obtained with the second order low-pass filter.

• The gain of the II order filter is set by R1 and RF,

while the high cut off frequency fH is determined by
R2,C2,R3 and C3.

101
The voltage gain magnitude equation for a
second order low-pass Butterworth filter is
given by

102
Filter Design:
1. Choose a value for a high cut off freq (fH ).

2. To simplify the design calculations, set R2 = R3 = R

and C2 = C3 = C then choose a value of C<=1μf.

3. Calculate the value of R using eqn 𝑅 = 1 / 2𝜋𝑓𝐻 𝐶

4. Finally, because of the equal resistor (R2 = R3) and

capacitor (C2 = C3) values, the pass band volt gain
AF = (1 + RF / R1) of the second order LPF has to be
equal to 1.586. That is RF = 0.586 R1.
Hence choose a value of R1≤100kΩ and Calculate the
103

value of R .
5.4.3: FIRST ORDER_HIGH-
PASS BUTTERWORTH
FILTER:

104
 FIRST ORDER_HIGH-PASS
BUTTERWORTH FILTER:

Fig:First order HPF Butterworth Fig: HPF Frequecy

filter circuit response 105
• Figure shows a first-order high-pass Butterworth filter
that uses an RC network for filtering.

• Op-amp is used in the non inverting configuration.

• Resistor R1 & Rf determine the gain of the filter.

• According to the voltage –divider rule, the voltage at

the non-inverting terminal (across Resistor) R is:

106
Simplifying the above equation we get

And the output voltage of the non inverting amplifier

circuit is

107
Where
Gain of the filter as function of
frequen. Passband of the filter

Low cutoff frequency of the filter

f = Frequency of the input signal 108

The gain magnitude equations of the high-pass filter
can be obtained by converting the above equation into
its equivalent polar form, we get

The operation of the high-pass filter can be verified from

the gain magnitude equation:
4. At very low frequencies, that is, f < fL ,

5. At f = fL

6. At f > fL
, 109
Filter Design First Order LPF Butterworth
Filter:
A high-pass filter can be designed by implementing the
following steps:
• Choose a value of low cutoff frequency fH.
• Select a value of C less than or equal to 1µF.
• Calculate the value of R using R = 1/2𝜋fL C
• Finally, select values of R1 and RF dependent on the
desired passband gain Af using Af = 1 +Rf / R1

110
5.4.4: SECOND ORDER HIGH-
PASS BUTTERWORTH
FILTER:

111
 SECOND ORDER HIGH-PASS
BUTTERWORTH FILTER:

Fig: Second order HPF

Fig: HPF Frequecy
Butterworth filter circuit
response
• Figure shows a Second-order high-pass Butterworth
filter that uses an RC network for filtering.

• A first order low-pass filter can be converted second

order type by using an additional RC network, as
shown in figure.
• A stop-band response having a 40-db/decade roll-off is
obtained with the second order high-pass filter.

• The gain of the IInd order filter is set by R1 and RF,

while the high cut off frequency fH is determined by
R2,C2,R3 and C3

113
• The voltage gain magnitude euation for a
second order low-pass Butterworth filter is
given by

114
5.4.5: BAND-PASS
FILTERS:

115
A band-pass filter has a passband between two cutoff
frequencies fH and fL such that fH > fL.
• Any input frequency outside this passband is
attenuated.

Types of band-pass filters:

• Basically there are two types of band-pass filters:

1.) Wide band pass filter: A band pass filter if figure of

merit or quality factor Q is less than 10 (Q<10).

2.) Narrow band pass filter: A band pass filter if figure

of merit or quality factor Q is greater than 10 (Q>10).

116
• Thus Q is a measure of selectivity, meaning the
higher the value of Q the more selective is the filter,
or the narrower is the bandwidth (BW).
• The relationship between Q, the -3db bandwidth,
and the centre frequency fc is given by an equation

For the wide band-pass filter the center frequency fC

can be defined as

Where fH = high cutoff frequency (Hz)

fL = low cutoff frequency (Hz) 117
 5.4.5.1: WIDE BAND-PASS FILTER
• A wide band-pass filter can be formed by simply
cascading high-pass and low-pass filter as shown in
the circuit diagram

Fig: ±20dB/decade wide band-pass filt 118

• Frequency response of wide band-pass filter is
shown in the graph.
• The circuit design is as same as low-pass and high-
pass filters.

Fig: Frequency response of wide band-pass filter 119

5.4.5.2: NARROW BAND-PASS
FILTER:

Fig: Narrow band-pass Fig: Frequency

filter response 120
• The narrow band-pass filter using multiple feedback
is shown in the figure.
• The unique features of this circuit are:
• It has two feedback paths, and this is the reason that
it is called a multiple-feedback filter.

• The op-amp is used in the inverting mode.

• The frequency response is as shown in the figure.

• Generally, the narrow band-pass filter is designed for

specific values of centre frequency fC and Q or fC and
bandwidth

121
 • The circuit components are determined from the
following relationships,
Let C1 = C2 = C

Where Af is the gain at fC, given by

The gain Af, however, must satisfy the condition

122
• The advantageof the abovenarrow band-pass filter
circuit is that its centre frequency fC can be changed
to new centre frequency fC′ without changing the
gain or bandwidth.
• This can be accomplished by changing R2 to R2′ so
that

_______ __ __ _

123
5.5: THE 555 TIMER:

124
• The 555 is a monolithic timing circuit that can
produce accurate and highly stable time delays or
oscillation.

• The timer basically operates in one of two modes

they are:
. * Monostable (one-shot) multivibrator.
* Astable (free-running) mulivibrator.

• The IC555 timer device is available as an 8-pin

metal can, an 8-pin mini DIP, or a 14-pin DIP.

125
 The important fetures of the 555 timer
are:
• It operates on +5V TO +18V supply voltage in both
astable and monostable modes.
• It has an adjustable duty cycle.
• Timing is from microseconds through hours.
• It has a high current output.
• The output can drive TTL.
• It has a temperature stability of 50 parts per million
(ppm) per degree Celsius change in temperature.

126
 THE 555 TIMER IC CONFIGURATION
AND BLOCK DIAGRAM:

 The 555 Timer is a 8-pin IC, The pin configuration is shown in

the figure
PIN DESCRIPTION:

Pin 1: Ground:
• All voltages are measured with respect to
this terminal.

Pin 2: Trigger:
• The o/p of the timer depends on the
amplitude of the external trigger pulse
applied to this pin.
128
Pin 3: Output:
• There are 2 ways a load can be connected to the o/p
terminal either between pin3 & ground or between
pin 3 & supply voltage
• (Between Pin 3 & Ground- ON load )
• (Between Pin 3 & + Vcc - OFF load )
• When the input is low: The load current flows
through the load connected between Pin 3 & +Vcc in
to the output terminal & is called the sink current.
• When the output is high: The current through the
load connected between Pin 3 & +Vcc (i.e. ON load) is
zero. However the output terminal supplies current to
the normally OFF load. This current is called the
source current..
129
Pin 4: Reset:
• The 555 timer can be reset (disabled) by applying a
negative pulse to this pin. When the reset function is
not in use, the reset terminal should be connected to
+Vcc to avoid any false triggering.

Pin 5: Control voltage:

• An external voltage applied to this terminal changes
the threshold as well as trigger voltage. In other
words by connecting a potentiometer between this
pin & GND, the pulse width of the output waveform
can be varied. When not used, the control pin should
be bypassed to ground with 0.01µF capacitor to
prevent any noise problems.
130
Pin 6: Threshold:
• This is the non inverting input terminal of upper
comparator which monitors the voltage across the
external capacitor.

Pin 7: Discharge:
• This pin is connected internally to the collector of
transistor Q1.
• When the output is high Q1 is OFF.
• When the output is low Q is (saturated) ON.

Pin 8: +Vcc:
• The supply voltage of +5V to +18V is applied to this
pin with respect to ground.
131
Block diagram of 555 Timer:

132
• In the block diagram of 555 timer, three 5k internal
resistors act as voltage divider providing bias voltage
of 2/3 Vcc to the upper comparator & 1/3 Vcc to the
lower comparator.

• It is possible to vary time electronically by applying a

modulation voltage to the control voltage input
terminal 5.

• In the Stable state:

The output of the control FF is high.
This means that the output is low because of
power amplifier which is basically an inverter.
Q = 1; Output = 0
133
• At the Negative going trigger pulse:
• The trigger passes through (Vcc/3) the output of the
lower comparator goes high & sets the FF. Q = 1; Q
=0

• At the Positive going trigger pulse:

• It passes through 2/3Vcc, the output of the upper
comparator goes high and resets the FF. Q = 0; Q = 1

• The reset input (pin 4) provides a mechanism to

reset the FF in a manner which overrides the effect
of any instruction coming to FF from lower
comparator
134
5.5.1: THE 555 TIMER AS A
MONOSTABLE
MULTIVIBRATOR:

135
THE 555 TIMER AS A MONOSTABLE
MULTIVIBRATOR:

136
• A monostable multivibrator is also called as one-shot
multivibrator.
• It is a pulse generating circuit in which the duration of
the pulse is determined by the RC network connected
externally to the 555 timer.
• In a stable state or standby state the output of of the
circuit is approximately zero or at logic-low level.
• When an external trigger pulse is applied, the output
is forced to go high (≅ 𝑉𝐶𝐶 ).
• The time output remains high is determined by the
external RC network connected to the timer.
• At the end of the timing interval, the output
automatically reverts back to its logic-low state
137
• The output stays low until the trigger pulse is again
applied.
• Then the cycle repeats.
• The monostable circuit has only one stable state
(outout low), hence the name monostable.
• Normally, the output of the monostable
multivibrator is low.
• Figure shows the 555 timer configured for
monostable multivibrator

138
Monostable Operation:

139
• Initially when the output is low, that is, the circuit is
in a stable state, transistor Q1 is on and the capacitor
C is shorted out to ground.
• When negative trigger pulse is applied to pin 2, the
transistor Q1 is turned off, which releases the short
circuit across the external capacitor C and drives the
output high.
• The capacitor C now starts charging up towards VCC
through RA.
• When the voltage across the capacitor equals 2/3VCC,
comparator 1’s output switches from low to high,
which inturn drives the output to its low state via the
output of the flip-flop
140
• At the same time, the output of the flip-flop turns
transistor Q1 on, and hence capacitor C rapidly
discharges through the transistor.

• The output of the monostable remains low until

trigger pulse is again applied.
• The the cycle repeats.

• The figure shows the trigger input, output voltage,

and the capacitor voltage waveforms.

141
The figure shows the trigger input, output voltage, and
the capacitor voltage waveforms.

142
 The voltage across the capacitor as in fig (b) is
given by

Rearranging the above equation

Where T –width of the pulse 143

5.5.2: THE 555 TIMER AS AN
ASTABLE MULTIVIBRATOR

144
5.5.2: THE 555 TIMER AS AN ASTABLE
MULTIVIBRATOR

145
THE 555 TIMER AS AN ASTABLE
MULTIVIBRATOR:

• An astable multivibrator is also called as free-

running multivibrator.
• It is a rectangular wave generating circuit.
• The time during which the output is either high or
low is determined by two resistors and a capacitor,
which are externally connected to the 555 timer.
• Figure shows the 555 timer connected as an astable
multivibrator.

146
Astable operation:
1. Initially, when the output is high :
• Capacitor C starts charging toward Vcc through RA
& RB.
• However, as soon as voltage across the capacitor
equals 2/3 Vcc, Comparator 1 triggers the Flip-Flop
& output switches low.
2. When the output becomes Low:
• Capacitor C starts discharging through RB and
transistor Q1.
• when the voltage across C equals 1/3 Vcc, comparator
2’s output triggers the Flip-Flop & the output goes
High.
147
• Then cycle repeats.
• The output voltage snd capacitor voltage waveforms
are shown in the figures.
• As sown in the waveforms, the capacitor is
periodically charged and discharged between 2/3 VCC
and 1/3 VCC, respectively.

148
• The time during which the capacitor charges from
1/3 VCC to 2/3 VCC is equal to the time the output is
high and is given by

𝑡𝑐 = 0.69 (𝑅𝐴 + 𝑅𝐵 ) C

• Similarly, the time during which the capacitor

discharges from 2/3 VCC to 1/3 VCC is equal to the
time the output is low and is given by
𝑡𝑑 = 0.69 (𝑅B ) C
Thus the total period of the output waveform is
𝑇 = 𝑡𝑐 + 𝑡𝑑

𝑇 = 0.69 (𝑅𝐴 + 2𝑅𝐵 )𝐶 149

  Thus the frequency of oscillation is s

 The duty cycle is the ratio of the time tC during which

the output is high to the total time period T.
 It is generally expressed as percentage is expressed as

150
END

151