Lecture 1

Logic Families
o When you work with digital ICs, you should be familiar not only with their logical operation but also with such
operational properties as voltage levels, noise immunity, power dissipation, fan-out, and propagation delay time.
o In this Lecture, the practical aspects of these properties are discussed.

Integrated Circuits (ICs):

• An IC is a complete electronic circuit in which both the Active and passive components are fabricated on an extremely tiny
single chip of silicon.
• Active components are those which have the ability to produce gain. Examples are : transistors and FETs.
• Passive Components or devices are those which do not have this ability. Examples are : resistors, capacitors and
inductors.
Advantages of ICs: Drawbacks of ICs:

1. Extremely small physical size. 1. Coils or inductors cannot be fabricated.

2. Very small weight 2. ICs function at fairly low voltages.
3. Reduced cost.
3. They handle only limited amount of power.
4. Extremely high reliability.
5. Suitability for small-signal operation. 4. They are quit delicate and cannot withstand rough handling or
6. Low power consumption. excessive heat.
7. Easy replacement. However, the advantages of ICs far outweigh their disadvantages or drawbacks.
Scale of integration:

  S SI − small scale integration<12

MSI − Medium scale integration 12 −99
LSI − Large scaleintegration 100 − 9 , 999
VLSI −Very large scale integration 10 ,000 − 99 , 999
ULSI −Ultra largescale integration 100 , 000 −999 ,999
GSI − Giga scale integration >1000 , 000
}C icuit per C hip

Classification ICs by function:

a. Linear: LICs are also referred to as analog ICs because their inputs and outputs can take on a continuous range of
values and the outputs are generally proportional to the inputs.

They are frequently used in:

1. Operational amplifiers. 6. Multipliers.
7. Voltage comparators.
2. Small-signal amplifiers.
8. Voltage regulators etc..
3. Power amplifiers.
4. RF and IF amplifiers.
5. Microwave amplifiers
b. Digital: Digital ICs contain circuits whose input and output voltages are limited to two possible levels-low or high.
It is so because digital signals are usually binary. Sometimes, digital circuits are referred to as .

 Digital ICs include circuits such as:

1. Logic gates.
2. Flip-flops.
3. Counters.
4. Clock chips.
5. Calculator chips.
6. Memory chips.
7. Microprocessors () etc…
 Classification of ICs by Structure:

Integrated Circuit
(IC)

Monolithic Film Hybrid

(Active and Passive) (Passive ) (Active and Passive)

Thin-film

Thick-film
Fig. 1
 Main Logic Families
• All logic circuits are available in IC modules and are divided into many families. Each family is classified by abbreviations
which indicate the type of logic circuit used:
o Resistance-transistor logic (RTL) : It was the first family group of logic circuits to be developed and packaged in IC in
early 1960s.
o Diode-transistor logic (DLT) : It followed RTL in late 1960s


  Transistor-Transistor Logic (TTL) OR : was introduced in the early 1970s.

o Schottky TTL : was introduced to improve the speed of TTL.

o Emitter-coupled logic (ECL): It is Fastest logic line currently available.

o
  Integrated-injection logic : It is one of the latest of the bipolar types of logic.

 Complementary metal-oxide semiconductor (CMOS): It has the lowest power dissipation of the currently-available
logic circuits.
 Saturated and Non-saturated Circuits

o Those logic circuits in which transistors are driven into to saturation are called saturated logic circuits or simply saturated
logic.

o Those Circuits which avoid saturation of their transistors are designed non-saturated logic.

o The disadvantage of saturated logic is the delay that occurs when the transistors is brought out of saturation.

o When a transistor is saturated, its base is flooded with carriers. Even when base voltage is switched off, the base remains
flooded for some time till all carriers leave it.

 o The time required by the carriers to leave the base is called saturation delay time .

o Obviously, saturated logic circuits have low switching speeds whereas non-saturated type are much faster.

o TTL is the example of a saturated logic whereas ECL represents a non-saturated logic.
 CMOS Series
o The categories of CMOS in terms of the dc supply voltage are :
5 V CMOS.
3.3 V CMOS.
2.5 V CMOS.
1.8 V CMOS..
o The lower-voltage CMOS families are a more recent development and are the result of an effort to reduce the power
dissipation.
o Since power dissipation is proportional to the square of the voltage, a reduction from 5 V to 3.3 V, for example,
cuts the power by 34% with other factors remaining the same.
o Within each supply voltage category, several series of CMOS logic gates are available.

o These series within the CMOS family differ in their performance characteristics and are designated by the prefix 74
or 54 followed by a letter or letters that indicate the series and then a number that indicates the type of logic device.
o The prefix 74 indicates commercial grade for general use.

o The prefix 54 indicates military grade for more severe environments.

o The basic CMOS series for the 5 V category and their designations include:
• 74HC and 74HCT—High-speed CMOS (the "T" indicates TTL compatibility).
• 74AC and 74ACT—Advanced CMOS.
• 74AHC and 74AHCT—Advanced High-speed CMOS.

o The basic CMOS series for the 3.3 V category and their designations include
• 74LV Low-voltage CMOS.
• 74LVC—Low-v01tage CMOS.
• 74ALVC—Advanced Low-voltage CMOS.
o In addition to the 74 series there is a 4000 series, which is an older, low-speed CMOS technology that is still available,
although in limited use.
o In addition to the "pure" CMOS, there is a series that combines both CMOS and TTL called BiCMOS. The basic
BiCMOS series and their designations are as follows:

• 74BCT—BiCMOS.
• 74ABT Advanced BiCMOS.
• 74LVT Low-voltage BiCMOS.

• 74ALB—Advanced Low-voltage BiCMOS.

 TTL Series

o Like CMOS, several series of TTL logic gates are available, all which operate from a 5 V dc supply.

o These series within the TTL family differ in their performance characteristics and are designated by the prefix
74 or 54 followed by a letter or letters that indicate the series and a number that indicates the type of logic
device within the series.
o A TTL IC can be distinguished from CMOS by the letters that follow the 74 or 54 prefix.

o The basic TTL series and their designations are as follows:

• 74—standard TTL (no letter).

• 74S—Schottky TTL.
• 74AS—Advanced Schottky TTL
• 74LS—Low-power Schottky TTL.
• 74ALS—Advanced Low-power Schottky TTL
• 74F—Fast TTL.
 Basic Operating Characteristics and Parameters of Logic Families
When we work with digital ICs from different logic families, we should be familiar with. not only their logical operation
but also with the basic operational properties.

Following are the important basic operational properties :

1. DC supply voltage.

2. TTL and CMOS logic levels.

3. Noise immunity.

4. Noise margin.

5. Power dissipation.

6. Propagation delay.

7. Speed-power product.

8. Loading and fan-out.

 DC supply voltage

o The nominal value of the dc supply voltage for TTL (transistor-transistor logic) devices is +5 V.

o CMOS (complementary metal-oxide semiconductor) devices are available in different supply voltage categories: +5 V,
+3.3 V, 2.5 V, and 1.2 V.
o Although omitted from logic diagrams for simplicity, the dc supply voltage is connected to the Vcc pin of an IC
package, and ground is connected to the GND pin. Both voltage and ground are distributed internally to all
elements within the package, as illustrated in Fig. 2 for a 14-pin package.

Fig. 2
 Logic Levels
o The voltages used to represent a 1 and a 0 are called logic levels.

o Ideally, one voltage level represents a HIGH and another voltage level represents a LOW.

o In a practical digital circuit, however, a HIGH can be any voltage between a specified minimum value and a specified
maximum value. Likewise, a LOW can be any voltage between a specified minimum and a specified maximum.
o There can be no overlap between the accepted range of HIGH levels and the accepted range of LOW levels.
o The voltage values between VL(max) and VH(min) are unacceptable for proper operation

Fig. 2
 CMOS Logic Levels
o For CMOS circuits and as indicated in Fig. 3

• The ranges of input voltages (VIL) that can represent a valid LOW (logic 0) are from 0 V to 1.5 V for the +5 V logic and
0 V to 0.8 V for the 3.3 V logic.
• The ranges of input voltages (VIH) that can represent a valid HIGH (logic 1) are from 3.5 V to 5 V for the 5 V logic and 2
V to 3.3 V for the 3.3 V logic,.
• The ranges of output voltages (VOL) that can represent a valid LOW (logic 0) are from 0 V to 0.33 V for the +5 V logic
and 0 V to 0.4 V for the 3.3 V logic.
• The ranges of input voltages (VIH) that can represent a valid HIGH (logic 1) are from 3.5 V to 5 V for the 5 V logic and 2
V to 3.3 V for the 3.3 V logic,.

+5 V logic Fig. 3
+3.3 V logic
 TTL Logic Levels

o The input and output logic levels for TTL are given in Fig. 4
o Just as for CMOS, there are four different logic level specifications: V IL, VIH, VOL, and VOH

Fig. 4
 Noise Immunity
o Noise is unwanted voltage that is induced in electrical circuits and can present a threat to the proper operation of the
circuit.
o Wires and other conductors within a system can pick up stray high-frequency electromagnetic radiation from adjacent
conductors in which currents are changing rapidly or from many other sources external to the system.

o Also, power-line voltage fluctuation is a form of low-frequency noise.

o In order not to be adversely affected by noise, a logic circuit must have a certain amount of noise immunity.

o This is the ability to tolerate a certain amount of unwanted voltage fluctuation on its inputs without changing its output
state.
o For example, if noise voltage causes the input of a 5 V CMOS gate to drop below 3.5 V in the HIGH state, the input is in
the unallowed region and operation is unpredictable .Thus, the gate may interpret the fluctuation below 3.5 V as a LOW
level, as illustrated in Fig. 5.

Fig. 5
o Similarly, if noise causes a gate input to go above 1.5 V in the LOW state, an uncertain condition is created, as illustrated in
Fig. 6.

Fig. 6
 Noise Margin
o A measure of a circuit's noise immunity is called the noise margin, which is expressed in volts.

o There are two values of noise margin specified for a given logic circuit:

• High-Level noise margin (VNH)

• Low-Level noise margin (VNL)

o Sometimes you will see the noise margin expressed as a percentage of Vcc
Fig. 6
Example: Determine the High-level and Low-level noise margins for 5 Volt CMOS Family?.
 Power Dissipation
o A logic gate draws current from the dc supply voltage source, as indicated in Fig. 7.

o When the gate is in the HIGH output state, an amount of current designated by ICCH is drawn; and in the LOW output
state, a different amount of current, ICCL, is drawn.

Fig. 6

 o As an example, if is specified as 1.5 mA when Vcc is 5 V and if the gate is in a static (nonchanging) HIGH output state,
the power dissipation () of the gate is:

o When a gate is pulsed, its output switches back and forth between HIGH and LOW, and the amount of supply current
varies between ICCH and ICCL.

o The average power dissipation depends on the duty cycle and is usually specified for a duty cycle of 50%.

o When the duty cycle is 50%, the output is HIGH half the time and LOW the other half.
o The average supply current is therefore:

o The average power dissipation is:

 Example: A certain gate draws 2 A when its output is HIGH and 3.6 A when its output is LOW. What is its average
power dissipation if Vcc is 5 V and the gate is operated on a 50% duty cycle?
o Power dissipation in a TTL circuit is essentially constant over its range of operating frequencies.

o Power dissipation in CMOS, however, is frequency dependent. It is extremely low under static (dc) conditions and
increases as the frequency increases. These characteristics are shown in the general curves of Fig. 8.

o For example, the power dissipation of a low-power Schottky (LS) TTL gate is a constant 2.2 mW.

 o The power dissipation of an HCMOS gate is 2.75 W under static conditions and 170 W at 100 kHz.

Fig. 7
 Propagation Delay Time
o When a signal passes (propagates) through a logic circuit, it always experiences a time delay, as illustrated in Fig. 8.
o A change in the output level always occurs a short time, called the propagation delay time, later than the change in the
input level that caused it.
o There are two propagation delay times specified for logic gates:
 • The time between a designated point on the input pulse and the corresponding point on the output pulse when the
output is changing from HIGH to LOW
 • The time between a designated point on the input pulse and the corresponding point on the output pulse when the
output is changing from LOW to HIGH.

o These propagation delay times are illustrated in Fig. 8, with the 50% points on the pulse edges used as references.

Fig. 7
o The propagation delay time of a gate limits the frequency at which it can be operated.

o The greater the propagation delay time, the lower the maximum frequency. Thus, a higher speed circuit is one that has a
smaller propagation delay time.
o For example, a gate with a delay of 3 ns is faster than one with a 10 ns delay.
 Speed-Power Product
o The speed-power product provides a basis for the comparison of logic circuits when both propagation delay time and
power dissipation are important considerations in the selection of the type of logic to be used in a certain application.
o The lower the speed-power product, the better. The unit of speed-power product is the picojoule (pJ).

o For example, HCMOS has a speed-power product of 1.2 PJ at 100 kHz while LS TTL has a value of 22 pJ.
 Loading and Fan-Out
o When the output of a logic gate is connected to one or more inputs of other gates, a load on the driving gate is created, as
shown in Fig. 8.

o There is a limit to the number of load gate inputs that a given gate can drive. This limit is called the fan-out of the gate.

Fig. 8
 CMOS Loading
o Loading in CMOS differs from that in TTL because the type of transistors used in CMOS logic present a predominantly
capacitive load to the driving gate, as illustrated in Fig. 9.

Fig. 9
o In this case, the limitations are the charging and discharging times associated with the output resistance of the driving
gate and the input capacitance of the load gates.

o When more load gate inputs are added to the driving gate output, the total capacitance increases because the input
capacitances effectively appear in parallel.

o This increase in capacitance increases the charging and discharging times, thus reducing the maximum frequency at
which the gate can be operated. Therefore, the fan-out of a CMOS gate depends on the frequency of operation.

o The fewer the load gate inputs, the greater the maximum frequency.
 TTL Loading
A TTL driving gate sources current to a load gate input in the HIGH state(1m) and sinks current from the load gate in the
LOW state (ID.

Current sourcing and current sinking are illustrated in simplified form in Fig. 9, where the resistors represent the internal
input and output resistance of the gate for the two conditions.

Fig. 9
o As more load gates are connected to the driving gate, the loading on the driving gate
increases.
o The total source current increases with each load gate input that is added, as illustrated in Fig. 10.
o As this current increases, the internal voltage drop of the driving gate increases, causing the output, V OH, to decrease

o If an excessive number of load gate inputs are connected, V OH drops below VOH(min) and the High-Level noise margin is
reduced, thus compromising the circuit operation. Also, as the total source current increases, the power dissipation of the
driving gate increases.

Fig. 10
o The fan-out is the maximum number of load gate inputs that can be connected without adversely affecting the
specified operational characteristics of the gate.

o For example, low power Schottky (LS) TTL has a fan-out of 20 unit loads. One input of the same logic family as the
driving gate is called a unit load.

o The total sink current also increases with each load gate input that is added, as shown in Fig. 11 . As this current
increases, the internal voltage drop of the driving gate in creases, causing V OL to increase.

o If an excessive number of loads are added, VOL exceeds OL(max)' and the LOW-level noise margin is reduced.

o In TTL, the current-sinking capability (LOW output state) is the limiting factor in determining the fan-out.
Fig. 11