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    VLSI Design (EE-402) Lithography

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    Zahidullah
    This document provides an overview of the CMOS fabrication process used to manufacture VLSI chips. It describes the key steps including depositing the polysilicon gate, adding n-type and p-type diffusion regions to form transistors, creating contacts, and depositing metal interconnect layers. Photolithography is used with multiple photo masks to pattern each layer. Design rules specify the minimum feature sizes and spacing between elements to ensure correct transistor operation during the manufacturing process.

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    © All Rights Reserved
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    VLSI Design (EE-402) Lithography

    Uploaded by

    Zahidullah
    195 views31 pages
    This document provides an overview of the CMOS fabrication process used to manufacture VLSI chips. It describes the key steps including depositing the polysilicon gate, adding n-type and p-type diffusion regions to form transistors, creating contacts, and depositing metal interconnect layers. Photolithography is used with multiple photo masks to pattern each layer. Design rules specify the minimum feature sizes and spacing between elements to ensure correct transistor operation during the manufacturing process.

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    lithography slides

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    This document provides an overview of the CMOS fabrication process used to manufacture VLSI chips. It describes the key steps including depositing the polysilicon gate, adding n-type and p-type diffusion regions to form transistors, creating contacts, and depositing metal interconnect layers. Photolithography is used with multiple photo masks to pattern each layer. Design rules specify the minimum feature sizes and spacing between elements to ensure correct transistor operation during the manufacturing process.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    195 views31 pages

    VLSI Design (EE-402) Lithography

    Uploaded by

    Zahidullah
    This document provides an overview of the CMOS fabrication process used to manufacture VLSI chips. It describes the key steps including depositing the polysilicon gate, adding n-type and p-type diffusion regions to form transistors, creating contacts, and depositing metal interconnect layers. Photolithography is used with multiple photo masks to pattern each layer. Design rules specify the minimum feature sizes and spacing between elements to ensure correct transistor operation during the manufacturing process.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 31

    VLSI Design

    By
    Dr. Yousuf Khan
    CMOS fabrication process
    • Inverter cross-section with well and substrate
    contacts
    CMOS inverter
    • polysilicon gate over a thin layer of silicon dioxide (SiO2,
    also called gate oxide)
    • A thick layer of SiO2 called field oxide prevents metal from
    shorting to other layers except where contacts are explicitly
    etched
    • The substrate must be tied to a low potential to avoid
    forward-biasing the p-n junction
    • between the p-type substrate and the n+ nMOS source or
    drain.
    • Likewise, the n-well must be tied to a high potential. This is
    done by adding heavily doped substrate and well contacts,
    or taps, to connect GND and VDD to the substrate and n-
    well, respectively
    Lithography
    • The fabrication sequence consists of a series
    of steps in which layers of the chip are defined
    through a process called lithography
    • Use of light to define or transfer patterns on
    the desired specimen is known as
    photolithography
    Photolithography
    • Optically project the shadow
    of the pattern on to the
    surface of the chip
    • Chip fabrication allows
    resolutions smaller than
    0.12 µm
    • Modern lithography
    continues to shrink the
    feature sizes
    Mask or Reticle
    • Mask consist of transparent and opaque
    regions usually defined on a high quality glass
    • Typically chromium is used to define pattern
    on mask
    Photolithography
    • To transfer the mask patterns to the surface of
    the specimen, the surface of the specimen is
    first coated with a light resistive liquid called
    photoresist
    • Spin coating of photoresist
    Photoresist exposure
    • Positive photoresist
    • Negative photoresist
    • Beading effect of
    photoresist
    CMOS inverter mask set
    • The inverter could be defined
    by a hypothetical set of six
    masks: n-well, polysilicon, n+
    diffusion, p+ diffusion,
    contacts, and metal
    • The process begins with
    • the creation of an n-well on a
    bare p-type silicon wafer
    Manufacturing the n-well
    Manufacturing the n-well
    • The wafer is first oxidized in a high-temperature
    (typically 900–1200 °C) furnace that causes Si and
    O2 to react and become SiO2 on the wafer surface
    • The oxide must be patterned to define the n-well
    • An organic photoresist that softens where
    exposed to light is spun onto the wafer
    • The photoresist is exposed through the n-well
    mask
    • The softened photoresist is removed to expose
    the oxide
    Manufacturing the n-well
    • The oxide is etched with hydrofluoric acid (HF)
    where it is not protected by the photoresist
    • The well is formed where the substrate is not
    covered with oxide
    • Two ways to add dopants are diffusion and ion
    implantation
    Manufacturing the n-well
    • In the diffusion process, the wafer is placed in a
    furnace with a gas containing the dopants
    • When heated, dopant atoms diffuse into the
    substrate. The well is wider than the hole in the
    oxide on account of lateral diffusion (figure (g))
    • With ion implantation, dopant ions are
    accelerated through an electric field and blasted
    into the substrate
    • The remaining oxide is stripped with HF to leave
    the bare wafer with wells in the appropriate
    places
    Manufacturing polysilicon and n-
    diffusion
    Transistor gates fabrication
    • Gate are made up of polycrystalline silicon,
    generally called polysilicon, over a thin layer of
    oxide
    • The thin oxide is grown in a furnace
    • Then the wafer is placed in a reactor with silane
    gas (SiH4) and heated again to grow the
    polysilicon layer through a process called
    chemical vapor deposition
    • The polysilicon is heavily doped to form a
    reasonably good conductor
    Fabrication of transistor active area
    • n+ regions are introduced for the transistor active area and
    the well contact
    • a protective layer of oxide is formed and patterned with the
    n-diffusion mask (Figure (d)) to expose the areas where the
    dopants are needed
    • polysilicon gate over the nMOS transistor blocks the
    diffusion so the source and drain are separated by a
    channel under the gate
    • This is called a self-aligned process
    • because the source and drain of the transistor are
    automatically formed adjacent to the gate without the
    need to precisely align the masks
    • Finally, the protective oxide is stripped
    P-diffusion, contacts, and metal
    P-diffusion, contacts, and metal
    • The process is repeated for the p-diffusion mask
    • The field oxide is grown to insulate the wafer
    from metal and patterned with the contact mask
    to leave contact cuts where metal should attach
    to diffusion or polysilicon
    • Finally, aluminum is sputtered over the entire
    wafer, filling the contact cuts as well
    • Sputtering involves blasting aluminum into a
    vapor that evenly coats the wafer
    • The metal is patterned with the metal mask
    (Fig(g)) and plasma etched to remove metal
    everywhere except where wires should remain
    Sputter deposition and plasma etching
    Modern fabrication processes
    • Create complex doping profiles around the
    channel of the transistor and print features
    that are smaller than the wavelength of the
    light being used in lithography
    • Modern processes also have 5–10+ layers of
    metal, so the metal and contact steps must be
    repeated for each layer
    • Chip manufacturing has become a commodity,
    and many different foundries will build
    designs from a basic set of masks
    Layout Design Rules
    Layout Design Rules
    • Metal and diffusion have minimum width and spacing
    of 4 λ
    • Contacts are 2 λ × 2 λ and must be surrounded by 1 λ
    on the layers above and below
    • Polysilicon uses a width of 2 λ
    • Polysilicon overlaps diffusion by 2 λ where a transistor
    is desired and has a spacing of 1 λ away where no
    transistor is desired
    • Polysilicon and contacts have a spacing of 3 λ from
    other polysilicon or contacts.
    • N-well surrounds pMOS transistors by 6 λ and avoids
    nMOS transistors by 6 λ
    IC fabrication
    • Over glass layer to protract the surface from
    external contaminations (Silicon nitride)
    • Pad frame and bonding pads
    Classification of solids
    Testing with probes

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