UNIT II

Central Processor
organization
INTRODUCTION
 The CPU performs bulk of the processing
jobs.
 Major components
 Register Set
 Stores temporary data during execution of instructions
 Arithmetic and Logic Unit
 Performs operations to execute instructions
 Control Unit
 Supervises the operation of the ALU and transfer of data
between register set and ALU
Components of CPU

REGISTER SET

CONTROL UNIT

ARITHMETIC AND LOGIC UNIT

 Computer architecture

 It is defined as the computer structure and behavior as seen by

the programmer that uses machine language instructions.
 Instructions formats
 addressing modes
 Instruction set
 General organization of cpu register (2)
 Reduced instruction set computer (RISC)
 complex instruction set computer (CISC)
General Register Organization
 MAR (The register that holds a address for the
memory)
 PROGRAM COUNTER (pc) keeps track of memory
address of next instruction to be executed.
 INSTRUCTION REGISTER holds the current
instruction until it is decoded .
 PROCESSOR REGISTER (AC)
general purpose processing register that has intermediate results
and it is called as an accumulator
Bus system organization
Bus structure consists of a set of common lines, one for each bit of a
register, through which binary information is transferred at one at a
time.
Bus organization
 Seven cpu register
 2 multiplexer
 2 buses (A and B)
 ALU
 Decoder
 Input
 Output
 Operations
 Selection lines
Encoding of Register selection fields.

Binary Code SELA SELB SELD

000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7
Encoding of ALU operation

OPR Select Operation Symbol

00000 Transfer A TSFA
00001 Increment A INCA
00010 Add A + B ADD
00101 Subtract A-B SUB
00110 Decrement A DEC A
01000 AND A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA
Example

 R1 ← R2 + R3
 MUX A selection (SELA): to place the content of R2 into bus A
 MUX B selection (SELB): to place the content of R3 into bus B
 ALU operation selection (OPR): to provide the arithmetic addition
(A + B)
 Decoder destination selection (SELD): to transfer the
content of the output bus into R1
 The four control selection variables are generated in the
control unit.
Example - contd.

 The various selection variables form a 14

bit control word

Field SELA SELB SELD OPR

Symbol R2 R3 R1 ADD
Control Word 010 011 001 00010
Stack Organization
 A useful feature included in the CPU.
 Item stored first is the last to be retrieved
(LIFO).
 Two operations- push (insert to stack ) and
pop (delete from stack)
 Register that holds the address of the stack –
Stack Pointer (SP)
 Can be implemented as Register Stack or
Memory Stack
Register Stack
 organized as a collection of a finite
number of registers.
63

FULL EMPTY
2

1
SP 0

DR
Push operation
 PUSH SP ← SP + 1 increment stack pointer
M [SP] ← DR write item on top of the
stack
If (SP = max) then (FULL ← 1)
check if stack is full
EMPTY ← 0 mark the stack not
empty.
Pop Operation
 POP DR ←M[SP] read item from the top of
stack
SP ←SP –1 decrement SP
If (SP = 0) then (EMPTY ←1)
check if stack is empty
FULL ← 0 mark the stack not full.
Memory Stack
 Implemented in a random-access
memory attached to a CPU.
 A portion of memory is assigned to a
stack and a processor register is used
as the stack pointer.
 3 segments r used in memory
 Program counter, address register,
stack pointer
Computer memory with program, data
and stack

PC 1000
Program

AR 2000
Data

3000
DR Stack

SP 3999
4000
4001
Push and Pop Operations
 Push : SP ←SP-1
M[SP] ←DR
Stack pointer is decremented so that it points at the
address of the next word.
 Pop : DR ←M[SP]
SP ←SP +1
The top item is read from the stack into a data
register.
The stack pointer is then incremented to point at a
next item.
Instruction Formats
 The most common fields found in
instruction format are:-
 An operation code field that specified the
operation to be performed
 An address field that designates a memory
address or a processor registers.
 A mode field that specifies the way the
operand or the effective address is
determined.
Instruction formats
 The operation code field of an instruction
format is a group of bits that define various
processor operations.
 The address field is either a memory address
or a register address.
 There may be varying number of address
fields depending upon the internal
organization of the CPU registers.
Types of Instruction format
1. Four address instruction
2. Three address instruction
3. Two address instruction
4. One address instruction
Four address Instruction
The instruction formats where the number of
operands in memory, the address where
results r stored and also the address, where
the next instruction to be carried out is
stored.
eg: ADD P Q R S where
P&Q address of the operand
R address of memory (storage)
s next instruction.
Three address instruction
Address field to specify either processor register
or a memory operand.
eg: ADD R1,R2,R3 implies R1←R2+R3.
general format:
dest←[src1]op[scr2]
dest = destination
scrc1& scr2= source operand
Op= opcode field
Evaluate X = (A + B) * (C + D)
 Three Address Instructions
ADD R1, A, B ; R1 ←M [A] + M [B]
ADD R2, C, D ; R2 ← M [C] + M [B]
MUL X, R1, R2 ; M [X] ← R1 * R2
Advantage: shorter programs
Disadvantage : too many bits required to
represent three addresses
Two address instruction
1. Two address are commonly used in
commercial instruction.
2. The first operand listed in the
instruction is assumed to both source
and destination.
ADD R1 R2 R1←R1+R2
general format:
dest←[dest] op[scr]
Evaluate X = (A + B) * (C + D)
Two Address Instructions
MOV R1, A ; R1 ← M [A]
ADD R1, B ; R1 ← R1 + M [B]
MOV R2, C ; R2 ← M [C]
ADD R2, D ; R2 ← R2 + M [D]
MUL R1, R2 ; R1 ← R1 * R2
MOV X1 R1 ; M [X] ← R1
One address instruction
The availability of an accumulator
register in a processor allows
intermediate results to be kept with out
unnecessary storing and retrieving
from the memory.
eg: ADD B AC←[AC]+B
General format: AC←[AC]OP[SCR]
Evaluate X = (A + B) * (C + D)
 One address instructions : accumulator organization
LOAD A ; AC ←M [A]
ADD B ; AC ← AC + M [B]
STORE T ; M [T] ← AC
LOAD C ; AC ← M [C]
ADD D ; AC ← AC + M[D]
MUL T ; AC ← AC + M[T]
STORE X ; M [×]← AC
All operations are done between the AC register and a memory
operand. T is the address of a temporary memory location
required for storing the intermediate result.
Zero address instruction
 A stack organise computer generally
uses the zero address instruction.
Evaluate X = (A + B) * (C + D)
 Zero Address Instructions : stack organization
PUSH A ; TOS ← A
PUSH B ; TOS ← B
ADD ; TOS ←(A + B)
PUSH C ; TOS ← C
PUSH D ; TOS ← D
ADD ; TOS ← (C + D)
MUL ; TOS ← (C + D) * (A + B)
POP X ; M [X] ← TOS
Data transfer & manipulation
 Most of the computer provide an extensive
set of instruction to give the user the
flexibility to carry out various computational
tasks.
 Most common instruction can be classified
into the three categories
1. Data transfer instructions.
2. Data manipulation instructions.
3. Program control instructions.
Data transfer instructions
 Data transfer instructions move data
from one place to another in the
computer, without changing the data
content.
 The most common transfer are between
memory and processor register.
Instruction mnemonic
LOAD LD
STORE ST
MOVE MOV
EXCHANGE XCH
INPUT IN
OUTPUT OUT
PUSH PUSH
POP POP
 DATA TRANSFER INSTRUCTIONS.

 LOAD - instruction specifies data transfer from memory to

a processor register.
 STORE-instruction designates a transfer from processor
register into memory.
 MOVE-instruction is generally used in computers with
multiple processor register.
 EXCHANGE-the instruction swaps the information from two
registers or a register.
 INPUT &OUTPUT-the instruction transfer data among
processor register to input output terminals.
 PUSH & POP instruction transfer data b\w processor
registers to memory stack.
DATA MANIPULATION
INSTRUCTION
 Data manipulation instructions perform
operations on data and perform
computations.
 They are usually divided into 3 basic types.
1. Arithmetic instructions
2. Logical and bit manipulation instruction.
3. Shift instruction.
 Arithmetic instructions

 The basic arithmetic operations

addition(+), subtraction(-)
,multiplication(*),division(/).
 Most computers provides instruction for
all the above 4 operations.
Instruction mnemonic
INCREMENT INC
DECREMENT DEC
ADD ADD
SUBTRACT SUB
MULTIPLY MUL
DIVIDE DIV
ADD WITH CARRY ADDC
SUBTRACT WITH SUB B
BORROW
Logical and bit manipulation
instruction
 Logical instructions perform binary
operations on strings of bits stored in
register.
 They are useful for manipulating
individual bit or a group of bits that
represent binary coded information.
Logical and bit manipulation
instruction
CLEAR CLR
COMPLEMENT COM
AND AND
OR OR
EXCULSIVE OR XOR
CLEAR CARRY CLRC
SET CARRY SETC
COMPLEMENT CARRY COMC
ENABLE , DISABLE ET,DI
SHIFT INSTRUCTION
 Shift are operations in which the bits of
a word are moved to the left r right.
 The bit shift in at end of the word
determines the type of shift used.
 Shift instructions may specify either
logical shifts, arithmetic shifts, or rotate
–type operations.
SHIFT INSTRUCTION
LOGICAL SHIFT RIGHT SHR
LOGICAL SHIFT LEFT SHL
ARITHMETIC SHIFT SHRA
RIGHT
ARITHMETIC SHIFT SHLA
LEFT
ROTATE RIGHT ROR
ROTATE LEFT ROL
ROTATE RIGHT AND RORC /ROLC
LEFT THROUGH CARRY
Addressing Modes
 The way the operands are chosen
during execution of an instruction is
determined by the addressing mode.
 It reduces the number of bits in the
addressing field of the instruction.

Opcode Mode Address

Purpose of Addressing modes
 To provide programming flexibility to
the user like pointers to memory,
counters for loop control, indexing of
data, etc.
 To reduce the no. of bits in the
addressing field of the instruction.
Addressing Modes
 Mode fields is used to locate operands.
 If instruction contains an address field,
it may be a register or a memory
address.
 If more than one address field, each
field is associated with its own mode.
Types of addressing modes
 Implied Mode- operands are specified implicitly in the
definition of instruction itself. Eg. “Increment Accumulator”.
It is an implied mode instruction because the operand in the
accumulator register is implied in the definition of the
instruction.
zero address instruction in a stack organization are implied
mode instruction.
 Immediate Mode- in this mode the operand is specified in
the instruction itself. The operand field contains the actual
operand to be used for operation specified in the instruction.
eg: LOAD (LD) 352
 Register Mode- the address field of an instruction specifies a
processor register, the instruction is said to be register mode.
k bit field can specify any one of 2k register.
Eg: LD R1 ADD R1 R2
Types of addressing modes
 Register Indirect Mode- the address field contains the address of a
register which holds the memory address of the operand.
eg:LD (R1) AC ←M [R1] M 5000[ABC]
 Auto increment or Auto decrement –
 similar to register indirect mode except that the value of the register is
incremented or decremented after it has been used to access memory.
Usually used to refer to a table of data.
eg:LD(R1)+ M 5000 [AAA] , LD (R1)- M4999 [RRR].
 Direct Address mode-
 the address field contains the memory address of the operand.
 Indirect Address Mode-
 the address field contains the address of the memory location that contains
the operand.
Types of addressing modes
 Relative addressing mode
the content of pc is added to the address part
of the instruction in order to obtain the
effective address.
Eg: LD $ ADR AC←M[ADR+PC]
AC←[5000]+[PC]
If the pc is 1000 then AC←[5000]+[1000]
AC ←[6000]
Types of addressing modes
 Indexed addressing mode (value)
in this mode the content of an index register
is added to the part of the instruction to
obtain the effective address.
Eg: LD ADR[X] AC←M[ADR+X]
 base addressing mode (addressing mode)

base register is added to the part of the

instruction to obtain the effective address.
Eg: LD ADR[X] AC←M[ADR+X]
 Examples of addressing mode
Binary mode Name assemble Loc of
code r operand
000 0 Register R R
001 1 Register (R) M[R]
indirect
010 2 Auto ( R)+ M[R] then
increment R←R+2
100 4 Auto -(R) R←R-2
decrement then M[R]
110 6 Index X(R) M[R+X]
011 3 Auto @(R)+ M[M[R]]
Typical Program Control Instructions
Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Call CALL
Return RET
Compare CMP
Test TST