Computer Architecture

A Quantitative Approach, Fifth Edition

Instruction-Level Parallelism
and Its Exploitation
 Introduction
Introduction
Pipelining become universal technique in 1985
Overlaps execution of instructions
Exploits Instruction Level Parallelism

Beyond this, there are two main approaches:

Hardware-based dynamic approaches
Used in server and desktop processors
Not used as extensively in PMP processors
Compiler-based static approaches
Not as successful outside of scientific applications
 Introduction
Instruction-Level Parallelism
When exploiting instruction-level parallelism,
goal is to maximize CPI
Pipeline CPI =
Ideal pipeline CPI +
Structural stalls +
Data hazard stalls +
Control stalls

Parallelism with basic block is limited

Typical size of basic block = 3-6 instructions
Must optimize across branches
 Introduction
Data Dependence
Loop-Level Parallelism
Unroll loop statically or dynamically
Use SIMD (vector processors and GPUs)

Challenges:
Data dependency
Instruction j is data dependent on instruction i if
Instruction i produces a result that may be used by instruction j
Instruction j is data dependent on instruction k and instruction k
is data dependent on instruction i

Dependent instructions cannot be executed

simultaneously
 Introduction
Data Dependence
Dependencies are a property of programs
Pipeline organization determines if dependence
is detected and if it causes a stall

Data dependence conveys:

Possibility of a hazard
Order in which results must be calculated
Upper bound on exploitable instruction level
parallelism

Dependencies that flow through memory

locations are difficult to detect
 Introduction
Name Dependence
Two instructions use the same name but no flow
of information
Not a true data dependence, but is a problem when
reordering instructions
Antidependence: instruction j writes a register or
memory location that instruction i reads
Initial ordering (i before j) must be preserved
Output dependence: instruction i and instruction j
write the same register or memory location
Ordering must be preserved

To resolve, use renaming techniques

 Introduction
Other Factors
Data Hazards
Read after write (RAW)
Write after write (WAW)
Write after read (WAR)

Control Dependence
Ordering of instruction i with respect to a branch
instruction
Instruction control dependent on a branch cannot be moved
before the branch so that its execution is no longer controller
by the branch
An instruction not control dependent on a branch cannot be
moved after the branch so that its execution is controlled by
the branch
 Introduction
Examples
Example 1: OR instruction dependent
DADDU R1,R2,R3 on DADDU and DSUBU
BEQZ R4,L
DSUBU R1,R1,R6
L:
OR R7,R1,R8

Example 2: Assume R4 isnt used after

DADDU R1,R2,R3 skip
BEQZ R12,skip
Possible to move DSUBU
DSUBU R4,R5,R6
before the branch
DADDU R5,R4,R9
skip:
OR R7,R8,R9
 Compiler Techniques
Compiler Techniques for Exposing ILP
Pipeline scheduling
Separate dependent instruction from the source
instruction by the pipeline latency of the source
instruction
Example:
for (i=999; i>=0; i=i-1)
x[i] = x[i] + s;
 Compiler Techniques
Pipeline Stalls
Loop: L.D F0,0(R1)
stall
ADD.D F4,F0,F2
stall
stall
S.D F4,0(R1)
DADDUI R1,R1,#-8
stall (assume integer load latency is 1)
BNE R1,R2,Loop
 Compiler Techniques
Pipeline Scheduling
Scheduled code:
Loop: L.D F0,0(R1)
DADDUI R1,R1,#-8
ADD.D F4,F0,F2
stall
stall
S.D F4,8(R1)
BNE R1,R2,Loop
 Compiler Techniques
Loop Unrolling
Loop unrolling
Unroll by a factor of 4 (assume # elements is divisible by 4)
Eliminate unnecessary instructions
Loop: L.D F0,0(R1)
ADD.D F4,F0,F2
S.D F4,0(R1) ;drop DADDUI & BNE
L.D F6,-8(R1)
ADD.D F8,F6,F2
S.D F8,-8(R1) ;drop DADDUI & BNE
L.D F10,-16(R1)
ADD.D F12,F10,F2
S.D F12,-16(R1) ;drop DADDUI & BNE
L.D F14,-24(R1)
ADD.D F16,F14,F2
note: number
S.D F16,-24(R1)
DADDUI R1,R1,#-32
of live registers
BNE R1,R2,Loop vs. original loop
 Compiler Techniques
Loop Unrolling/Pipeline Scheduling
Pipeline schedule the unrolled loop:

Loop: L.D F0,0(R1)

L.D F6,-8(R1)
L.D F10,-16(R1)
L.D F14,-24(R1)
ADD.D F4,F0,F2
ADD.D F8,F6,F2
ADD.D F12,F10,F2
ADD.D F16,F14,F2
S.D F4,0(R1)
S.D F8,-8(R1)
DADDUI R1,R1,#-32
S.D F12,16(R1)
S.D F16,8(R1)
BNE R1,R2,Loop
 Compiler Techniques
Strip Mining
Unknown number of loop iterations?
Number of iterations = n
Goal: make k copies of the loop body
Generate pair of loops:
First executes n mod k times
Second executes n / k times
Strip mining
 Branch Prediction
Branch Prediction
Basic 2-bit predictor:
For each branch:
Predict taken or not taken
If the prediction is wrong two consecutive times, change prediction
Correlating predictor:
Multiple 2-bit predictors for each branch
One for each possible combination of outcomes of preceding n
branches
Local predictor:
Multiple 2-bit predictors for each branch
One for each possible combination of outcomes for the last n
occurrences of this branch
Tournament predictor:
Combine correlating predictor with local predictor
 Branch Prediction
Branch Prediction Performance

Branch predictor performance

 Branch Prediction
Dynamic Scheduling
Rearrange order of instructions to reduce stalls
while maintaining data flow

Advantages:
Compiler doesnt need to have knowledge of
microarchitecture
Handles cases where dependencies are unknown at
compile time

Disadvantage:
Substantial increase in hardware complexity
Complicates exceptions
 Branch Prediction
Dynamic Scheduling
Dynamic scheduling implies:
Out-of-order execution
Out-of-order completion

Creates the possibility for WAR and WAW

hazards

Tomasulos Approach
Tracks when operands are available
Introduces register renaming in hardware
Minimizes WAW and WAR hazards
 Branch Prediction
Register Renaming
Example:

DIV.D F0,F2,F4
ADD.D F6,F0,F8
antidependence
S.D F6,0(R1)
SUB.D F8,F10,F14 antidependence
MUL.D F6,F10,F8

+ name dependence with F6

 Branch Prediction
Register Renaming
Example:

DIV.D F0,F2,F4
ADD.D S,F0,F8
S.D S,0(R1)
SUB.D T,F10,F14
MUL.D F6,F10,T

Now only RAW hazards remain, which can be strictly

ordered
 Branch Prediction
Register Renaming
Register renaming is provided by reservation stations
(RS)
Contains:
The instruction

Buffered operand values (when available)

Reservation station number of instruction providing the

operand values
RS fetches and buffers an operand as soon as it becomes
available (not necessarily involving register file)
Pending instructions designate the RS to which they will send
their output
Result values broadcast on a result bus, called the common data bus (CDB)
Only the last output updates the register file
As instructions are issued, the register specifiers are renamed
with the reservation station
May be more reservation stations than registers
 Branch Prediction
Tomasulos Algorithm
Load and store buffers
Contain data and addresses, act like reservation
stations

Top-level design:
 Branch Prediction
Tomasulos Algorithm
Three Steps:
Issue
Get next instruction from FIFO queue
If available RS, issue the instruction to the RS with operand values if
available
If operand values not available, stall the instruction
Execute
When operand becomes available, store it in any reservation
stations waiting for it
When all operands are ready, issue the instruction
Loads and store maintained in program order through effective
address
No instruction allowed to initiate execution until all branches that
proceed it in program order have completed
Write result
Write result on CDB into reservation stations and store buffers
(Stores must wait until address and value are received)
Branch Prediction
Example
 Branch Prediction
Hardware-Based Speculation
Execute instructions along predicted execution
paths but only commit the results if prediction
was correct
Instruction commit: allowing an instruction to
update the register file when instruction is no
longer speculative
Need an additional piece of hardware to prevent
any irrevocable action until an instruction
commits
I.e. updating state or taking an execution
 Branch Prediction
Reorder Buffer
Reorder buffer holds the result of instruction
between completion and commit

Four fields:
Instruction type: branch/store/register
Destination field: register number
Value field: output value
Ready field: completed execution?

Modify reservation stations:

Operand source is now reorder buffer instead of
functional unit
 Branch Prediction
Reorder Buffer
Register values and memory values are not
written until an instruction commits
On misprediction:
Speculated entries in ROB are cleared

Exceptions:
Not recognized until it is ready to commit
 Multiple Issue and Static Scheduling
Multiple Issue and Static Scheduling
To achieve CPI < 1, need to complete multiple
instructions per clock

Solutions:
Statically scheduled superscalar processors
VLIW (very long instruction word) processors
dynamically scheduled superscalar processors
Multiple Issue and Static Scheduling
Multiple Issue
 Multiple Issue and Static Scheduling
VLIW Processors
Package multiple operations into one instruction

Example VLIW processor:

One integer instruction (or branch)
Two independent floating-point operations
Two independent memory references

Must be enough parallelism in code to fill the

available slots
 Multiple Issue and Static Scheduling
VLIW Processors
Disadvantages:
Statically finding parallelism
Code size
No hazard detection hardware
Binary code compatibility
 Dynamic Scheduling, Multiple Issue, and Speculation
Dynamic Scheduling, Multiple Issue, and Speculation

Modern microarchitectures:
Dynamic scheduling + multiple issue + speculation

Two approaches:
Assign reservation stations and update pipeline
control table in half clock cycles
Only supports 2 instructions/clock
Design logic to handle any possible dependencies
between the instructions
Hybrid approaches

Issue logic can become bottleneck

Dynamic Scheduling, Multiple Issue, and Speculation
Overview of Design
 Dynamic Scheduling, Multiple Issue, and Speculation
Multiple Issue
Limit the number of instructions of a given class
that can be issued in a bundle
I.e. on FP, one integer, one load, one store

Examine all the dependencies amoung the

instructions in the bundle

If dependencies exist in bundle, encode them in

reservation stations

Also need multiple completion/commit

 Dynamic Scheduling, Multiple Issue, and Speculation
Example
Loop: LD R2,0(R1) ;R2=array element
DADDIU R2,R2,#1 ;increment R2
SD R2,0(R1) ;store result
DADDIU R1,R1,#8 ;increment pointer
BNE R2,R3,LOOP ;branch if not last element
Dynamic Scheduling, Multiple Issue, and Speculation
Example (No Speculation)
Dynamic Scheduling, Multiple Issue, and Speculation
Example
 Adv. Techniques for Instruction Delivery and Speculation
Branch-Target Buffer
Need high instruction bandwidth!
Branch-Target buffers
Next PC prediction buffer, indexed by current PC
 Adv. Techniques for Instruction Delivery and Speculation
Branch Folding
Optimization:
Larger branch-target buffer
Add target instruction into buffer to deal with longer
decoding time required by larger buffer
Branch folding
 Adv. Techniques for Instruction Delivery and Speculation
Return Address Predictor
Most unconditional branches come from
function returns
The same procedure can be called from
multiple sites
Causes the buffer to potentially forget about the
return address from previous calls
Create return address buffer organized as a
stack
 Adv. Techniques for Instruction Delivery and Speculation
Integrated Instruction Fetch Unit
Design monolithic unit that performs:
Branch prediction
Instruction prefetch
Fetch ahead
Instruction memory access and buffering
Deal with crossing cache lines
 Adv. Techniques for Instruction Delivery and Speculation
Register Renaming
Register renaming vs. reorder buffers
Instead of virtual registers from reservation stations and
reorder buffer, create a single register pool
Contains visible registers and virtual registers
Use hardware-based map to rename registers during issue
WAW and WAR hazards are avoided
Speculation recovery occurs by copying during commit
Still need a ROB-like queue to update table in order
Simplifies commit:
Record that mapping between architectural register and physical register
is no longer speculative
Free up physical register used to hold older value
In other words: SWAP physical registers on commit
Physical register de-allocation is more difficult
 Adv. Techniques for Instruction Delivery and Speculation
Integrated Issue and Renaming
Combining instruction issue with register
renaming:
Issue logic pre-reserves enough physical registers
for the bundle (fixed number?)
Issue logic finds dependencies within bundle, maps
registers as necessary
Issue logic finds dependencies between current
bundle and already in-flight bundles, maps registers
as necessary
 Adv. Techniques for Instruction Delivery and Speculation
How Much?
How much to speculate
Mis-speculation degrades performance and power
relative to no speculation
May cause additional misses (cache, TLB)
Prevent speculative code from causing higher
costing misses (e.g. L2)

Speculating through multiple branches

Complicates speculation recovery
No processor can resolve multiple branches per
cycle
 Adv. Techniques for Instruction Delivery and Speculation
Energy Efficiency
Speculation and energy efficiency
Note: speculation is only energy efficient when it
significantly improves performance

Value prediction
Uses:
Loads that load from a constant pool
Instruction that produces a value from a small set of values
Not been incorporated into modern processors
Similar idea--address aliasing prediction--is used on
some processors