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    Latch Versus Register: Latch Stores Data When Clock Is Low

    Uploaded by

    Srikrishna Jana
    - A latch stores data when the clock is low, while a register stores data when the clock rises. - There are positive and negative latches that are transparent when the clock is high or low, respectively. - A master-slave register uses two latches triggered on opposite edges to avoid metastability and ensure data is captured on both edges. - Various latch and register designs can be built from NMOS-only mux-based cells or CMOS transmission gates to be edge-triggered and avoid clock overlap issues.

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    © All Rights Reserved
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    Latch Versus Register: Latch Stores Data When Clock Is Low

    Uploaded by

    Srikrishna Jana
    42 views23 pages
    - A latch stores data when the clock is low, while a register stores data when the clock rises. - There are positive and negative latches that are transparent when the clock is high or low, respectively. - A master-slave register uses two latches triggered on opposite edges to avoid metastability and ensure data is captured on both edges. - Various latch and register designs can be built from NMOS-only mux-based cells or CMOS transmission gates to be edge-triggered and avoid clock overlap issues.

    Original Description:

    Latch Versus Register

    Original Title

    Latch Versus Register

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    - A latch stores data when the clock is low, while a register stores data when the clock rises. - There are positive and negative latches that are transparent when the clock is high or low, respectively. - A master-slave register uses two latches triggered on opposite edges to avoid metastability and ensure data is captured on both edges. - Various latch and register designs can be built from NMOS-only mux-based cells or CMOS transmission gates to be edge-triggered and avoid clock overlap issues.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    42 views23 pages

    Latch Versus Register: Latch Stores Data When Clock Is Low

    Uploaded by

    Srikrishna Jana
    - A latch stores data when the clock is low, while a register stores data when the clock rises. - There are positive and negative latches that are transparent when the clock is high or low, respectively. - A master-slave register uses two latches triggered on opposite edges to avoid metastability and ensure data is captured on both edges. - Various latch and register designs can be built from NMOS-only mux-based cells or CMOS transmission gates to be edge-triggered and avoid clock overlap issues.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    of 23

    Latch versus Register

    Latch Register
    stores data when stores data when
    clock is low clock rises

    D Q D Q

    Clk Clk

    Clk Clk

    D D

    Q Q
    Latches
    Positive Latch Negative Latch

    In D Q Out In D Q Out
    G G

    CLK CLK

    clk clk

    In In

    Out Out

    Out Out Out Out


    stable follows In stable follows In
    Latch-Based Design
    N latch is transparent P latch is transparent
    when = 0 when = 1

    N P
    Logic
    Latch Latch

    Logic
    Timing Definitions

    CLK
    t Register
    tsu thold D Q

    D DATA CLK
    STABLE t
    tc 2 q

    Q DATA
    STABLE t
    Positive Feedback: Bi-Stability
    V i1 V o1 =V i2 V o2

    V o1 Vi2
    V o2 =V i1

    V i1 V o2

    A
    V i2 =V o1

    B
    V i1 =V o2
    Meta-Stability
    A A
    V i2 5 V o1

    V i2 5 V o1
    C C

    B B
    V i1 5 V o2 V i1 5 V o2

    Gain should be larger than 1 in the transition reg


    Writing into a Static Latch
    Use the clock as a decoupling signal,
    that distinguishes between the transparent and opaque states
    CLK
    CLK

    Q D D
    CLK
    CLK
    D

    CLK
    Forcing the state
    Converting into a MUX (can implement as NMOS-only)
    Mux-Based Latches
    Negative latch Positive latch
    (transparent when CLK= 0)
    (transparent when CLK= 1

    Q 0 Q
    1

    D 0 D 1

    CLK CLK

    Q Clk Q Clk In Q Clk Q Clk In


    Mux-Based Latch

    CLK

    CLK

    CLK
    Mux-Based Latch

    CLK
    QM
    CLK

    QM

    CLK

    CLK

    NMOS only Non-overlapping clocks


    Master-Slave (Edge-
    Triggered) Register
    Slave
    Master

    0 Q D
    1 QM
    1
    QM
    D 0 Q

    CLK
    CLK

    Two opposite latches trigger on edge


    Also called master-slave latch pair
    Master-Slave Register
    Multiplexer-based latch pair

    I2 T2 I3 I5 T4 I6 Q

    QM
    D I1 T1 I4 T3

    CLK
    Clk-Q Delay

    2.5
    CLK

    1.5
    Volts

    D
    tc 2 q(lh) tc 2 q(hl)
    Q
    0.5

    2 0.5
    0 0.5 1 1.5 2 2.5
    time, nsec
    Setup Time
    3.0 3.0
    Q
    2.5 2.5

    2.0 QM 2.0 I 2 2 T2

    1.5 1.5 Q

    Volts
    Volts

    CLK CLK
    D D
    1.0 1.0
    I 2 2 T2 QM
    0.5 0.5

    0.0 0.0

    2 0.5 2 0.5
    0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1
    time (nsec) time (nsec)
    (a) Tsetup5 0.21 nsec (b) Tsetup5 0.20 nsec
    Reduced Clock Load
    Master-Slave Register
    CLK CLK

    D T1 I1 T2 I3 Q

    I2 I4
    CLK CLK
    Avoiding Clock Overlap
    CLK X CLK
    Q
    A
    D
    B

    CLK CLK
    (a) Schematic diagram

    CLK

    CLK
    (b) Overlapping clock pairs
    Other Latches/Registers: C MOS 2

    VDD VDD

    M2 M6

    CLK M4 CLK M8
    X
    D Q
    CL1 CL2
    CLK M3 CLK M7

    M1 M5

    Master Stage

    Keepers can be added to make circuit pseudo-static


    Insensitive to Clock-Overlap
    VDD VDD VDD VDD

    M2 M6 M2 M6

    0 M4 0 M8
    X X
    D Q D Q
    1 M3 1 M7

    M1 M5 M1 M5

    (a) (0-0) overlap (b) (1-1) overlap


    Other Latches/Registers:
    TSPC
    VDD VDD VDD VDD

    Out

    In CLK CLK In CLK CLK

    Positive latch Negative latch


    (transparent when CLK= 1)
    (transparent when CLK= 0)
    Including Logic in TSPC
    VDD VDD VDD VDD

    In1 In2
    PUN
    Q Q

    In CLK CLK CLK CLK

    In1
    PDN

    Example: logic inside the latch


    AND latch
    TSPC Register
    VDD VDD VDD

    CLK Q
    M3 M6 M9
    Y
    Q
    D CLK X CLK
    M2 M5 M8

    CLK
    M1 M4 M7
    Pulse-Triggered Latches
    An Alternative Approach
    Ways to design an edge-triggered sequential ce

    Master-Slave Pulse-Triggered Latch


    Latches
    L1 L2 L
    Data Data
    D Q D Q D Q

    Clk Clk Clk Clk


    Clk
    Pulsed Latches
    Hybrid Latch Flip-flop (HLFF), AMD K-6 and K-7 :

    CLK P1 P3
    x Q

    M6
    M3

    D P2 M5
    M2

    M4
    M1

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