Arm Cortex-A9 Mpcore Processor: Presented by
Arm Cortex-A9 Mpcore Processor: Presented by
Arm Cortex-A9 Mpcore Processor: Presented by
MPCore Processor
Presented byM. Jawwad Rafiq
FA15-R01-017
Cell no: +923336335584
Cortex-A Series
Efficient application processors for
every level of performance.
Application processors for OS and
user applications.
Processors in smartphones, tablets,
notebooks, eBook readers etc.
Cortex-A Series
High performance, in a family of low
power.
Cortex-A9 single core processor or a
scalable multicore processor: the
Cortex-A9 MPCore processor.
Where is it used?
Examples:
-
PlayStation Vita
Registers
ARM has 37 registers in total, all of
which are 32-bits long.
1 dedicated program counter
1 dedicated current program status
register
5 dedicated saved program status
registers
30 general purpose registers
16 registers only visible in ARM.
A particular SPSR (saved program
Registers
Pipeline Stages in A9
Presentation Overview
Micro-architecture
Memory System
Microarchitecture Overview
Variable length, out of order, superscalar
pipeline
Two instructions are fetched in one cycle
Issue up to 4 instructions per cycle into:
Primary data processing pipeline
Secondary data processing pipeline
Load-store pipeline
Compute engine (FPU/NEON) pipeline
CortexA9 Microarchitecture
Renam
e
Issue
Execut
e
Write
back
Decode
Instructio
n Fetch
Memor
y
Instruction Fetch
Instruction Decode
Rename
Register Renaming
- Resolving data dependencies and
unroll small loops by hardware
- Virtual renaming of registers
Issue
Execute
Memory Hierarchy
Cortex A9 MPcore
CPU
Instruc
tion
Cache
Data
Cache
CPU
CPU
Instruc
tion
Cache
Data
Cache
Instruc
tion
Cache
Data
Cache
L2
L2 Cache
Cache
Main
Main Memory
Memory
CPU
Instruc
Data
tion
Cache
Cache
Accelerator
Coherence
Port
L1 caches
Cortex A9
MPcore
CP
U
D$
D$
I$
I$
CP
U
CP
U
D$
D$
I$
I$
D$
D$
I$
I$
SCU
AXI RW
64-bit
bus
CP
U
D
D
$
$
I$
I$
ACP
ACP
AXI RW
64-bit
bus
L2
L2 Cache
Cache
Main
Main Memory
Memory
16, 32 or 64KB
Support for Security Extensions
I cache:
D cache:
L2 cache
Cortex A9
MPcore
CP
U
D$
D$
I$
I$
CP
U
CP
U
D$
D$
I$
I$
D$
D$
I$
I$
SCU
AXI RW
64-bit
bus
CP
U
D
D
$
$
I$
I$
ACP
ACP
AXI RW
64-bit
bus
L2
L2 Cache
Cache
Main
Main Memory
Memory
Shared
128KB to 8MB
CP
U
D$
D$
I$
I$
CP
U
CP
U
D$
D$
I$
I$
D$
D$
I$
I$
SCU
AXI RW
64-bit
bus
CP
U
D
D
$
$
I$
I$
ACP
AXI RW
64-bit
bus
L2
L2 Cache
Cache
Main
Main Memory
Memory