Ibm Cell Processor

A chip with one PPC hyper-threaded core
called PPE and eight specialized cores called

SPEs.
The challenge to be solved by the Cell was

to put all those cores together on a single
chip.
This was made possible by the use of a bus

with outstanding performance.
The Cell processor can be split into four

components:
external input and output structures,

the main processor called the Power
Processing Element (PPE)
eight fully-functional co-processors called
the Synergistic Processing Elements, or
SPEs,
a specialized high-bandwidth circular data
bus connecting the PPE, input/output
elements and the SPEs, called the Element
Interconnect Bus or EIB.
The PowerPC Processor Element, usually

denoted as PPE is a dual-threaded powerpc
processor version 2.02.
This 64-bit RISC processor also has the

Vector/SIMD Multimedia Extension.
The PPEs role is crucial in the Cell architecture

since it is on the one hand running the OS, and
on the other hand controlling all other
resources, including the SPEs .
The PPE is made out of two main units:
1: The Power Processor Unit(ppu)

2:The Power Processor Storage Subsystem
(PPSS).
It is the processing part of the PPE and is

composed of:
A full set of 64-bit PowerPC registers.
32 128-bit vector multimedia registers.
a 32KB L1 instruction cache.

a 32KB L1 data cache.
All the common components of a ppc

processors with vector/SIMD
extensions (instruction control unit, load
and store unit, fixed-Point integer unit,
floating-point unit, vector unit, branch unit,
virtual memory management unit).
The PPU is hyper-threaded and supports 2

simultaneous threads.
This handles all memory requests from the

PPE and requests made to the PPE by other
processors or I/O devices.
It is composed of:
A unified 512-KB L2 instruction and
data cache.
Various queues
A bus interface unit that handles bus
arbitration and pacing on the Element
Interconnect Bus
Each Cell chip has 8 Synergistic Processor

Elements.
They are 128-bit RISC processor which are

specialized for data-rich, compute-intensive
SIMD applications.
This consist of two main units.
1:The Synergistic Processor Unit (SPU)

2:The Memory Flow Controller (MFC)
This deals with instruction control and execution.
It includes various components:
A register file of 128 registers of 128 bits

each.
A unified instruction and data 256-kB Local
Store (LS).
A channel-and-DMA interface.
As usual, an instruction-control unit, a load
and store unit, two fixed-point units, a floating
point
unit.
The SPU implements a set of SIMD

instructions, specific to the Cell.
Each SPU is independent, and has its own

program counter.
Instructions are fetched in its own Local

Store
LS
Data are also loaded and stored in the LS.
It is actually the interface between the SPU

and the rest of the Cell chip.
MFC interfaces the SPU with the EIB.
In addition to a whole set of MMIO

registers, this contains a DMA controller.
1:The Element Interconnect Bus:
this bus makes it possible to link all parts of the chip.
The EIB itself is made out of a 4-ring structure (two

clockwise, and two counterclockwise) that is used to
transfer data, and a tree structure used to carry
commands.
It is actually controlled by what is called the Data

Arbitrer.
This structure allows 8 simultaneous transaction on

the bus.
2: Input/output interfaces
The Memory Interface Controller (MIC).

It provides an interface between the EIB and the main
storage.
It currently supports two Rambus Extreme Data Rate
(XDR) I/O (XIO) memory channels.
The Cell Broadband Engine Interface (BEI).

This is the interface between the Cell and I/O devices,
such as GPUs and various bridges.
It supports two Rambus FlexIO external I/O channels.
One of this channel only supports non-coherent
transfers. The other supports either coherent or
noncoherenT.
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IBM/Toshiba/Sony joint project - 4-5 years, 400 designers

234 million transistors, 4+ Ghz
256 Gflops (billions of floating pointer operations per second)
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Cell is Multi-Core
Cell is a Flexible Architecture
Cell is a Broadband Architecture
Cell is a Real-Time Architecture
Cell is a Security Enabled Architecture

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A chip with one PPC hyper-threaded core

called PPE and eight specialized cores called

The challenge to be solved by the Cell was

This was made possible by the use of a bus

The Cell processor can be split into four

external input and output structures,

The PowerPC Processor Element, usually

This 64-bit RISC processor also has the

The PPEs role is crucial in the Cell architecture

The PPE is made out of two main units:

1: The Power Processor Unit(ppu)

It is the processing part of the PPE and is

A full set of 64-bit PowerPC registers.

32 128-bit vector multimedia registers.

a 32KB L1 instruction cache.

All the common components of a ppc

The PPU is hyper-threaded and supports 2

This handles all memory requests from the

Each Cell chip has 8 Synergistic Processor

They are 128-bit RISC processor which are

This consist of two main units.

1:The Synergistic Processor Unit (SPU)

This deals with instruction control and execution.

It includes various components:

A register file of 128 registers of 128 bits

The SPU implements a set of SIMD

Each SPU is independent, and has its own

Instructions are fetched in its own Local

It is actually the interface between the SPU

MFC interfaces the SPU with the EIB.

In addition to a whole set of MMIO

1:The Element Interconnect Bus:

this bus makes it possible to link all parts of the chip.

The EIB itself is made out of a 4-ring structure (two

It is actually controlled by what is called the Data

This structure allows 8 simultaneous transaction on

The Memory Interface Controller (MIC).

The Cell Broadband Engine Interface (BEI).

IBM/Toshiba/Sony joint project - 4-5 years, 400 designers

Cell is a Flexible Architecture

Cell is a Broadband Architecture

Cell is a Real-Time Architecture

Cell is a Security Enabled Architecture

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