Virtual Memory
Virtual Memory
Virtual Memory
A0-A31
CPU
Memory
D0-D31
D0-D31
Data
Virtual
Physical
Address
Translation
CPU
D0-D31
Physical
Addresses
A0-A31
Memory
D0-D31
Data
Translation:
Program can be given consistent view of memory, even though physical
memory is scrambled
Makes multithreading reasonable (now used a lot!)
Only the most important part of program (Working Set) must be in
physical memory.
Contiguous structures (like stacks) use only as much physical memory as
necessary yet still grow later.
Protection:
Different threads (or processes) protected from each other.
Different pages can be given special behavior
(Read Only, Invisible to user programs, etc).
Kernel data protected from User programs
Very important for protection from malicious programs
Sharing:
Can map same physical page to multiple users
(Shared memory)
Physical
Address Space
frame
frame
frame
frame
A machine
usually supports
pages of a few
sizes
(MIPS R4000):
Physical
Memory Space
frame
frame
frame
frame
virtual
address
OS
manages
the page
table for
each
ASID
A machine
usually supports
pages of a few
sizes
(MIPS R4000):
Physical
Memory Space
Virtual Address
frame
frame
12
offset
V page no.
frame
frame
virtual
address
Page Table
Base Reg
index
into
page
table
Page Table
V
Access
Rights
PA
table located
in physical P page no.
memory
offset
12
Physical Address
22 21
12 11
0
P1 index P2 index Page Offset
dirty used
Dirty bit:
page written. 1 0
Head pointer
Place pages on free
list if used bit
is still clear.
Schedule pages
with dirty bit set to
be written to disk.
Tail pointer:
Clear the used
bit in the
page table
Architects role:
support setting
dirty and used
1
0
1
0
...
0
1
1
0
Freelist
Free Pages
Virtual
Addresses
Virtual
A0-A31
CPU
D0-D31
Data
Physical
Translation
Look-Aside
Buffer
(TLB)
A0-A31
Memory
D0-D31
What is
Translation Look-Aside Buffer (TLB) the table
of
A small fully-associative cache of
mapping
s that it
mappings from virtual to physical addresses
caches?
TLB caches
page table
entries.
virtual address
page
Physic
al
frame
addres
s
for ASID
off
Page Table
2
0
1
3
TLB
frame page
2
2
0
5
physical address
page
off
V=0 pages
either reside
on disk or
have not yet
been
allocated.
Page Offset
Index
Cache Tags
Virtual
Translation
Look-Aside
Buffer
Physical
(TLB)
Cache
Tag
Byte Select
Cache
Block
Hit
Q. What is the
downside?
A. Inflexibility. Size of
cache limited by page
size.
Cache
Block
cache
index
20
virt page #
2
00
12
disp
Solutions:
go to 8K byte page sizes;
go to 2 way set associative cache; or
SW guarantee VA[13]=PA[13]
10
1K
4
CPU
D0-D31
Virtual
Addresses
Virtual
Cache
D0-D31
Virtual
Physical
Addresses
Physical
Translation
Look-Aside
Buffer
(TLB)
A0-A31
Main Memory
D0-D31
Summary #1/3:
The Cache Design Space
Cache Size
cache size
block size
associativity
replacement policy
write-through vs write-back
write allocation
Associativity
Block Size
Bad
Good
Factor A
Less
Factor B
More