cs278 Week2b
cs278 Week2b
cs278 Week2b
Verilog
Simple synthesis
Translation
Structural
Use Verilog gate constructs to represent logic gates Write Verilog code that connects these parts together
Behavioral flow
Use procedural and assign constructs to indicate what actions to take The Verilog compiler converts to the schematic for you
Verilog Miscellanea
Letters, digits, _, $ Cant start with a digit Case-sensitive! There are also reserved words cant be one of these
Verilog Types
There are NO user-defined types There are only two data types:
wire
Represents a physical connection between structural elements (think of this as a wire connecting various gates) This is the most common type for structural style wire is a net type and is the default if you dont specify a type
reg
Represents an abstract storage element (think of this as an unsigned integer variable) This is used in the behavioral style only
module endmodule
Ports are a scalar wire type unless you specify otherwise Example: input [3:0] A; // a 4 bit (vector) input port (wire) called A
and And1(z1,x,y);
This is NOT like a typical programming language Everything operates concurrently (in parallel)
Primitive gates can have any number of inputs (called fan in)
The Verilog compiler will decide what the practical limit is and build the circuit accordingly (by cascading the gates)
A 0 0 0 0
B 0 0 1 1
C 0 1 0 1
L 0 0 0 0
If A = off, then light L is always off If A = on, the behavior depends on B and C only
1
1 1 1
0
0 1 1
0
1 0 1
0
1 1 0
with Verilog:
module light3Way(L,A,B,C); input A, B, C; output L;
Behavioral style uses Boolean algebra to express the behavior of the circuit
module light3Way(L,A,B,C); input A, B, C; output L; assign L = (A & ~B & C) | (A & B & ~C); endmodule
Continuous Assignment
The RHS is recomputed when a value in the RHS changes The new value of the RHS is assigned to the LHS after the propagation delay (default delay is 0) The LHS must be a net (i.e. wire) type Example: assign L = (A & ~B & C) | (A & B & ~C);
Boolean Operators
Examples ~A, A & B, A | B, A^B (xor), A~^B (xnor) !A, A&&B, A||B &A, ~&A, |A, ~|A, ^~A, ~^A Bit length L(A) 1 1
Relational
Arithmetic Shift Concatenate Replication
1
Max(L(A),L(B)) L(A) L(A)++L(B) B*L(A)
Condition
A?B:C
Max(L(B),L(C))
Gate Delays
The propagation delay is in units which can be set independently from the code
Graphical Entry
Waveform/Timing Diagram
Compiler
HDL Entry
Timing Analysis
UP2 Board
Analysis process
f = A B' + A' B
aka A B
Synthesis process
Synthesis (1)
Synthesis (2)
Boolean algebra: a mathematical technique Karnaugh maps: a visual technique Quine-McClusky: an algorithmic technique
Cost = 2 + 3 = 5
Cost = 6 + 11 = 17
# of gates Area of circuit Estimated routing cost (for wires) Shortest Critical Path Delay
2 single bit inputs (A, B) 1 single bit output sum S = A + B 1 single bit output carry-out Cout
A 0 0 1 1
B 0 1 0 1
S 0 1 1 0
A 0 0 1 1
B 0 1 0 1
Cout 0 0 0 1
3 single bit inputs (A, B, Cin) 1 single bit output sum S = A + B + Cin 1 single bit output carry-out Cout A 0 0 B 0 0 Cin 0 1 S 0 1 Cout 0 0
0
0 1 1 1 1
1
1 0 0 1 1
0
1 0 1 0 1
1
0 1 0 0 1
0
1 0 1 1 1
More Gates
1 NAND x y x 0 0 1 1
NOR x F y x 0 0 1 1 y 0 1 0 1 F 1 0 0 0 F x 0 0 1 1
XOR
XNOR x
NAND
x
y F y
NOR
y 0 1 0 1
F 1 1 1 0
y 0 1 0 1
F 0 1 1 0
x 0 0 1 1
y 0 1 0 1
F 1 0 0 1
x x y 0 0
F y
NAND: Opposite of AND (NOT AND) NOR: Opposite of OR (NOT OR) XOR: Exactly 1 input is 1, for 2-input XOR. (For more inputs -- odd number of 1s) XNOR: Opposite of XOR (NOT XOR)
Likewise, NOR same as OR with power/ground switched AND in CMOS: NAND with NOT OR in CMOS: NOR with NOT So NAND/NOR more common
Circuit a b c S
S = (abc) Use NOR Use XNOR Use XOR Useful for generating parity bit common for detecting errors
0 0 0
1 a0 b0 a1 b1 a2 b2 A=B
Detecting all 0s
Detecting equality
Detecting odd # of 1s
Circuit Simplification
Two circuits are functionally equivalent if the circuit behavior is the same for all inputs Simplification is the process of finding a functionally equivalent circuit that costs less
Boolean algebraic simplification is rarely done much in practice, but all other techniques are based on this process
S = (A' B' Cin)+(A' B Cin')+(A B' Cin')+(A B Cin) Cout = (A' B Cin)+(A B' Cin)+(A B Cin')+(A B Cin)
These can be greatly simplified Using Boolean algebra often results in a non-SOP form not even two-level logic
S = Cin'A'B + Cin'A B' + Cin A' B' + Cin A B = Cin'(A' B + A B') + Cin (A' B' + A B) = Cin' (A B) + Cin (A B)' = Cin (A B) = Cin A B Cout = Cin' A B + Cin A' B + Cin A B' + Cin A B = Cin(A B) + A B or equivalently = A B + B Cin + A Cin (the majority function)
A B Cin FA
S Cout
Using Boolean algebra to simplify expressions can be quite challenging There are easier ways
Neither the SOP nor the POS forms guarantee a minimum cost implementation
Most practical devices use only NAND or NOR gates anyway So, how is all of this helpful?
Circuit minimization methods can be developed from this basis Converting SOP and POS to NAND/NOR circuits is easy