Datasheet PDF
Datasheet PDF
Datasheet PDF
11/30/2012
REV: 00
Typical Application
VIN VOUT
RA
RB
RCS
VCC
1 2 4
VCC DRV CS
DIM
8 DIM LD5850 FB 5
COVP
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Pin Configuration
SOP-8 (TOP VIEW)
VCC
COMP
OVP
DIM
FB
8 7 6 5
1 YYWWPP
2 3 4
DRV
VCC
GND
CS
Ordering Information
Part number Package TOP MARK Shipping
Pin Descriptions
PIN NAME FUNCTION
1 VCC Power source VCC pin.
2 DRV Gate drive output to drive the external MOSFET.
3 GND Ground.
Current Sense pin. Connect with an external current sensing resistor to GND. CS
4 CS pin voltage is used to provide current feedback in the control loop and detect an
overcurrent condition.
5 FB LED output current feedback through a current sense resistor.
6 COMP Compensation of the error amplifier for voltage loop compensation.
7 OVP Over-voltage protection.
PWM Dimming Input. If the DIM pin voltage is below logic Voltage threshold, the
8 DIM DRV control would be stopped immediately until DIM pin voltage rises to high
again.
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LD5850
Block Diagram
VCC
DIM DIM
Vref OK
OVP
SCP
0.2V
2.5V
OVP
SCP Driver
DIM Stage
DRV
LED SHORT
14V
Osillator S Q
Slope
Compensation
PWM R
Comparator
CS LEB
0.6V
0.5V OCP LED SHORT
Comparator
GND
Voltage Divider 0.3V
& GM
Buffer FB
COMP
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LD5850
Absolute Maximum Ratings
VCC, DRV, CS, FB, OVP 30V
All Other Pins -0.3V ~ 5.5V
Power Dissipation, PD@85C, SOP-8 250mW
Package Thermal Resistance, SOP-8, JA 160°C/W
Maximum Junction Temperature 150C
Operating Junction Temperature -40C to 125C
Operating Ambient Temperature -40C to 85C
Storage Temperature Range -55C to 125C
Lead Temperature (Soldering, 10sec) 260C
ESD Level (Human Body Model) 2.0KV
ESD Level (Machine Model) 200V
Caution:
Stress exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stress above Recommended Operating Conditions may affect
device reliability.
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LD5850
Electrical Characteristics
(VCC=12V, TA=25C, unless otherwise noted.)
PARAMETER CONDITIONS MIN. TYP. MAX. UNITS
Input Power (VCC)
Turn On Level UVLO(on) 8.7 V
Turn Off Level UVLO(off) 7 V
Shutdown Current DIM=Low, over 200ms 40 A
Standby Current DIM=Low 1 mA
DIM=High,
Operating Current 5 mA
Switching at no load
Boost Converter
Switching frequency 162 180 198 KHz
Boost Maximum duty cycle Switching frequency=180KHz 85 90 95 %
Source current, VIN=12V 1.2 A
DRV gate drive
Sink current, VIN=12V 1.3 A
Output High Clamp Level VCC=24V 14 V
DRV pin Rising Time DRV pin load=1nF 75 ns
DRV pin Falling Time DRV pin load=1nF 75 ns
COMP clamp voltage 3.6 3.8 4.0 V
Feedback (FB)
Reference Voltage 0.3 V
Tolerance of Reference Voltage -3 3 %
PWM Dimming (DIM)
Enable 2 V
DIM Voltage threshold
Disable 0.8 V
Resistance from DIM pin to GND 600 K
PWM dimming frequency 0.1 1 KHz
Dimming Duty-Cycle 0 100 %
Shutdown Recover Delay Time
(Note 1) 200 ms
(TDOWN)
Current Sensing (CS)
Current Sense Input Threshold
0.45 0.5 0.55 V
Voltage
LEB time 275 nS
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PARAMETER CONDITIONS MIN. TYP. MAX. UNITS
Over Voltage Protection
Over Voltage Threshold OVP 2.375 2.5 2.625 V
LED Over Voltage Hysteresis OVP Hysteresis 1 V
Output Short Circuit Protection
Output short Voltage Threshold OSP 0.17 V
Over Temperature Protection
OTP Trip Point 150 °C
De-bounce Point 30 °C
Note 1:
DIM
Shutdown
ILED_full
LED current
Per channel Shutdown-
0mA
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Typical Performance Characteristics
17 LEDs in series, 500mA/string, unless otherwise noted.
ILED
VIN
VCC
VOUT VOUT
VDRV
VDIM
ILED
Fig. 2 VIN=24V, “DIM Turn On, Duty=100%” Fig. 3 VIN=24V, “Steady State, Duty=100%”
VIN VIN
VOUT VOUT
ILED
ILED
VDIM
VDIM
VIN
VOUT
VOVP
VOUT
ILED
VCOMP
VDIM
VDRV
Fig. 6 VIN=24V, “fDIM=240Hz, Dim Duty=100%” Fig. 7 VIN=24V, “LED Open Protection , Duty=100%
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LD5850
Application Information
Operation Overview LED Open Protection and OVP Trip Point
The LD5850 is designed for current-mode control power If there’s open in LED string, VOUT will start to boost up
converters. It provides all the advantages of current-mode OVP voltage. Once it rises up to the threshold of around
control, including cycle-by cycle current limit and the 2.5V, the MOSFET drive output (DRV) will turn off and the
simplified loop compensation. IC restart it only after OVP voltage drops below 1.5V.
R RA
VOVP 2.5 B
Output Drive Stage RB
An output stage of a CMOS buffer, with typical driving Place the bypass capacitor (COVP) between OVP and
capability of 1.2A/-1.3A, is incorporated to drive a power signal ground as close as possible. It’s superior to
MOSFET directly. The output voltage is clamped at 14V suppress the noise and protect OVP from abnormal
to protect the MOSFET gate even when the VCC voltage condition.
UVLO(off)
Current Sensing and Leading-edge
Blanking
t The LD5850 detects the primary MOSFET current across
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LD5850
spikes below 275ns and the negative spike of the CS pin PCB Layout Guideline
below -0.5V. It’s recommended to separate the high frequency
However, the pulse width of the turn-on spike is switching current from the low-level control signals in
determined according to the output power, circuit design layout. The high switching current (MOSFET, inductor,
and PCB layout. It is strongly recommended to add a gate driver and FB return ends) may disturb the other
smaller R-C filter for large power application to avoid CS low-level signals in the feedback loop and protection
pin from being damaged by the negative turn-on spike. circuitry. As a result, it may cause the control function to
275ns behave abnormally. To avoid these side effects, a few
blanking
time guidelines are recommended for the PCB layout as below.
DRV
1. Route the VIN bypass capacitor and the signal ground
close to the IC as possible. The traces between
OCP capacitor and VIN pin should be short as possible to
Signal CS
avoid noise interference.
R CS
2. Use broader traces for VIN, VOUT and power ground.
0.5V
Those components connected to VIN, VOUT and
Removable if the negative power ground carry high input/output current, such as
Spike is not over spec (-0.5V)
Fig. 2 power MOSFET and decoupling capacitors. To
The VRCS need be checked again by below equation to minimize power loss in these traces, the resistance of
avoid the output power be limited by VCOMP_CLAMP. traces should be kept as low as possible.
1.5 (1.3 Duty(%) ) (3 IL(Peak ) RCS ) 3.5V
3. Use broader traces between power MOSFET drain,
inductor and diode since they often carry high current
in these traces. To minimize power loss in these traces,
CS
Sense the resistance of traces should be minimized as
Amplifier
x3
possible.
RCS
4. Keep the gate drive traces short and broad around the
VSLOPE S
COMP IC driver output, DRV pin, and the power MOSFET.
VCOMP_clamp=3.5V The driving traces have a high current spike during
FB EA
inverter operation. To minimize power MOSFET
switching loss or oscillation voltage in the gate driver
signal, the drive traces should be as broad and short
as possible to minimize resistance and parasitic
Thermal Protection inductance.
Thermal protection limits the whole power dissipation in
this device. When the junction temperature reaches 150°C
approximately, the thermal sensor will send the signal of
shutdown logic to turn off this device and resume the
operation after the IC’s junction temperature cools by 30°
C
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LD5850
Package Information
SOP-8
Important Notice
Leadtrend Technology Corp. reserves the right to make changes or corrections to its products at any time without notice. Customers
should verify the datasheets are current and complete before placing order.
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LD5850
Revision History
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Leadtrend Technology Corporation www.leadtrend.com.tw
LD5850-DS-00 November 2012