The rest of this paper is organized as follows: Section II (DOUT). The conversion process is alternating between the
describes the interface circuit prototype. The digital serial two inputs of the DDC112 since it contains only one A/D
interface system dealing with the A/D control, data retrieving, converter. The integration and conversion process is done
and UART interface with the FPGA implementation are independently of the data retrieval process.
reported in Section III. In Section IV, the experimental setup
and the results of the measurements are presented and assessed. A. A/D Control and Data Retrieving
At last conclusions are drawn in Section V.
Fig. 3 shows the block diagram of the digital serial
interface between the DDC112U and the ATLYS FPGA
II. INTERFACE CIRCUITS PROTOTYPE development board. The maximum sampling rate for the
Fig. 2. illustrates the prototype of the interface circuit with DDC112U is 2 KSPS: it is controlled by the CONV signal
4×4 tactile sensor array. The DDC112 is a dual inputs which allows a maximum integration time of 500μs. Fig. 4
converter consisting of two identical input channels where each shows the time diagram of the signals control and data
performs the function of current to voltage integration followed retrieval. Using a counter on the clock cycles of the FPGA
by a multiplexed analog to digital (A/D) conversion. Each device (100 MHz), the FPGA sets the CONV signal which
input has two integrators so that the current to voltage allows the DDC112U to start integration. With the falling edge
integration can be continuous in time. The output of the four of DVALID, the data from the last conversion is available for
integrators are switched to one delta-sigma (ΔΣ) converter via retrieval. The falling edge of DXMIT in combination with the
a four input multiplexer. With the DDC112 in the continuous data clock (DCLK) will initiate the serial transmission of the
integration mode, the output of the integrators from one side of data from the DDC112U. Data is retrieved from the DDC112
both of the inputs will be digitized while the other two when DVALID falls and completed before the occurrence of
integrators are in the integration mode [11]. This integration the next CONV transition from high to low or low to high.
and A/D conversion process is controlled by the system clock, The DVALID output goes low when the shift register of the
CLK. With a 10 MHz system clock, the integrator combined DDC112U contains valid data. Taking into consideration that
with the delta sigma converter accomplishes a single 20 bits the DDC112U is converting at the maximum sampling rate
conversion in approximately 220μs. The results from first side (Tint = 500μs), the time during which one retrieving operation
(side A) and second side (side B) of each signal input are must be done is:
stored in a serial output shift register. The DVALID output
goes low when the shift register contains valid data. Hence, a Treceive = Tint – t1– t2 (1)
specific digital serial interface is required to control the Where t1 = 421.2 μs and t2 =10 μs are two fixed times when
integration time and the conversion phase, and also to retrieve the DDC112U work with frequency of 10MHz.
the converted data when available. This has been done using
ATLYS development board containing the Spartan®-6 FPGA For that, Treceive = 500 – 421.2 – 10 = 68.8μs. Then the 40
device. clock cycle of the DCLK (for 40 bits) must be done before this
deadline:
III. DIGITAL SERIAL INTERFACE TDCLK ≤ 68.8 /40 = 1.72μs
The DDC112U deals with a digital synchronous serial FDCLK ≥ 582 KHz (2)
interface to provide the digital results. The serial interface
consists of a data clock (DCLK), an enable transmit pin
(DXMIT), a data valid pin (DVALID), a serial data output pin TABLE 1
DIGITAL SERIAL INTERFACE IMPLEMENTATION RESULTS
Resources Utilization
Slice registers 215
Slice LUTs 214
Operating frequency (MHz) 198.7
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Fig. 5. Setup Measurements
C. Hardware Implementation
To this end, selecting FDCLK = 2 MHz data retrieval process The digital serial interface has been implemented in VHDL
is guaranteed without any risk of reaching the next CONV using Xilinx ISE Design Suite 14.7. Design has been
transition. On the other hand, one bit of DOUT will be synthesized, placed and routed, and programmed to the
available on each falling edge of DCLK. For that, the digital Spartan-6 XC65SLX45 FGG484 FPGA device. "XPower
interface retrieves the data on the rising edge of DCLK to Analyser" provided by ISE tool has been used in order to
ensure a bit retrieving each clock cycle. Data are stored in Data analyze the power consumption of the CORDIC circuit.
register having the length of 40 bits. Implementation results are reported in Table 1; it presents a
good performance in terms of hardware resources and power
B. UART to USB Interface consumption.
In order to assess the functionality of the interface circuit,
and to analyze on PC the retrieved data from sensor signals IV. EXPERIMENTAL SETUP AND MEASURMENTS
when a mechanical stimuli is applied, an UART to USB
interface has been implemented. Two different “ping-pong” The measurements of the response of two tactile sensors are
registers have been used: data_reg and temp_reg. When presented in this work. The array consists of 4×4 tactile
data_reg is filled with the all 40 bits, data is stored into sensors, from which only two sensors were directly connected
temp_reg in order to free up data_reg to the next retrieving to the input of the DDC112U.
operation. The temporary register temp_reg is in charge of Fig. 5 illustrates the different instruments used for this
sending the data to the ATLYS board while data_reg deals setup. The frequency generator controls the oscillation
with the A/D interface. To send data in real time and to avoid frequency of the shaker which has been fixed to 27 Hz for the
memorizing in the FPGA, data contained in the temporary current setup. A force sensor is mounted on the shaker to read
register (40 bits) have to be sent before the next retrieving out the corresponding force value using LabVIEW tool. On the
operation, such that: other hand, when the shaker applies a mechanical stimulus on
the surface of tactile sensor, the generated electrical signal is
connected to the DDC112U board to be converted. As
TTX < Tint – 40 × TDCLK = 480 μs (3)
described above, the FPGA is used to perform two different
Where TTX is the transmission time. The followed procedure tasks: 1) A/D control and data retrieving, and 2) the UART to
respects the time constraints, and sending data before the USB interface to send the converted data to MATLAB in order
arrival of the next converted data is guaranteed for a TTX = 370 to be elaborated. The work aims to study the feedback
μs. capacitors of the DDC112U to analyze the performance when
(a) (b)
Fig. 6. (a) Mean measured voltage vs Force and (b) Charge vs Force the four capacitance values under study.
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applying mechanical force on its surface. Tactile signal
analysis has been provided when the proposed interface based
on DDC112U and an FPGA Xilinx Spartan®-6 is used.
Experimental results demonstrate the correct functionality of
the proposed system when the measured voltage and charge in
terms of the input force have been assessed. Future work will
consist on the implementation of the interface electronics with
DDC232/264 allowing high number of input channels. Such
interfaces will be able to deal with arrays of sensors having up
Fig. 7. d33 piezoelectric coefficient for the four capacitance values to 64 channels with the possibility to cascade a number of
under study. circuits if a large area e-skin is targeted.
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