General Description: ISA To Ethernet MAC Controller With Integrated 10/100 PHY
General Description: ISA To Ethernet MAC Controller With Integrated 10/100 PHY
General Description: ISA To Ethernet MAC Controller With Integrated 10/100 PHY
1. General Description
The DM9000 is a fully integrated and cost-effective different processors. The PHY of the DM9000 can
single chip Fast Ethernet MAC controller with a interface to the UTP3, 4, 5 in 10Base-T and UTP5 in
general processor interface, a 10/100M PHY and 4K 100Base-TX. It is fully compliant with the IEEE 802.3u Spec.
Dword SRAM. It is designed with low power and high Its auto-negotiation function will automatically configure the
performance process that support 3.3V with 5V DM9000 to take the maximum advantage of its abilities. The
tolerance. DM9000 also supports IEEE 802.3x full- duplex flow control.
This programming of the DM9000 is very simple, so user
The DM9000 also provides a MII interface to connect can port the software drivers to any system easily.
HPNA device or other transceivers that support MII
interface. The DM9000 supports 8-bit, 16-bit and 32-
bit uP interfaces to internal memory accesses for
2. Block Diagram
PHYceiver MAC
Processor
Interface
transceiver PCS
Control &Status
Memory
MII Registers
TX+/- Management
10 Base-T
RX Machine
Tx/Rx
RX+/-
Internal
SRAM
MII Management
Autonegotiation Control
& MII Register
Final 1
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Table of Contents
(22H~23H) ..............................................................18
1. General Description ..............................................1
6.21 RX SRAM Write Pointer Address Register
(24H~25H) .......................................................19
6.22 Vendor ID Register (28H~29H).......................19
2. Block Diagram……………………………………… 1
6.23 Product ID Register (2AH~2BH) .....................19
6.24 Chip Revision Register (2CH).........................19
6.25 Special Mode Control Register (2FH).............19
3. Features ................................................................4
6.26 Memory Data Read Command without Address
Increment Register (F0H) ................................19
6.27 Memory Data Read Command with Address
4. Pin Configuration ..................................................5
Increment Register (F2H) ................................19
4.1 Pin Configuration I: with MII Interface.................5
6.28 Memory Data Read_ address Register
4.2 Pin Configuration II: with 32-Bit Data Bus...........6
(F4H~F5H) ......................................................19
6.29 Memory Data Write Command without Address
Increment Register (F6H) ................................19
5. Pin Description......................................................7
6.30 Memory Data Write Command with Address
5.1 MII Interface ........................................................7
Increment Register (F8H) ................................19
5.2 Processor Interface.............................................8
6.31 Memory Data Write_ address Register
5.3 EEPROM Interface. ............................................9
(FAH~FBH) ......................................................20
5.4 Clock Interface ....................................................9
6.32 TX Packet Length Register (FCH~FDH) ........20
5.5 LED Interface ......................................................9
6.33 Interrupt Status Register (FEH) ......................20
5.6 10/100 PHY/Fiber .............................................10
6.34 Interrupt Mask Register (FFH) ........................20
5.7 Miscellaneous Pins ...........................................10
5.8 Power Pins ........................................................10
7. EEPROM Format ................................................21
6. Vendor Control and Status Register Set.............11
6.1 Network Control Register (00H)........................13
8. MII Register Description......................................22
6.2 Network Status Register (01H) .........................13
8.1 Basic Mode Control Register (BMCR) – 00 ......23
6.3 TX Control Register (02H) ................................13
8.2 Basic Mode Status Register (BMSR) – 01........24
6.4 TX Status Register I (03H)................................14
8.3 PHY ID Identifier Register #1 (PHYID1) – 02 ...25
6.5 TX Status Register II (04H)...............................14
8.4 PHY Identifier Register #2 (PHYID2) – 03........25
6.6 RX Control Register (05H) ................................14
8.5 Auto-negotiation Advertisement Register
6.7 RX Status Register (06H) .................................15
(ANAR) – 04 ....................................................26
6.8 Receive Overflow Counter Register (07H) .......15
8.6 Auto-negotiation Link Partner Ability Register
6.9 Back Pressure Threshold Register (08H) .........15
(ANLPAR) – 05 ................................................27
6.10 Flow Control Threshold Register (09H) ..........16
8.7 Auto-negotiation Expansion Register (ANER) –
6.11 RX/TX Flow Control Register (0AH) ...............16
06 .....................................................................27
6.12 EEPROM & PHY Control Register (0BH) .......16
8.8 DAVICOM Specified Configuration Register
6.13 ROM & PHY Address Register (0CH) ............17
(DSCR) – 16 .....................................................28
6.14 EEPROM & PHY Data Register (0DH, 0EH)..17
8.9 DAVICOM Specified Configuration and Status
6.15 Wake Up Control Register (0FH)....................17
Register (DSCSR) – 17 ...................................29
6.16 Physical Address Register (10H~15H) ...........17
8.10 10BASE-T Configuration/Status (10BTCSR) –
6.17 Multicast Address Register (16H~1DH)..........18
18 .....................................................................30
6.18 General Purpose Control Register (1EH)…….18
6.19 General Purpose Register (1FH) ....................18
6.20 TX SRAM Read Pointer Address Register
2 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 3
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
3. Features
4 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
4. Pin Configuration
4.1 Pin Configuration I: with MII Interface
LINKACT#
CLK20MO
SPEED#
TX_EN
GPIO3
GPIO2
GPIO1
GPIO0
DGND
DGND
DVDD
DVDD
DVDD
EEDO
EECS
EECK
DUP#
MDIO
TXD3
TXD2
TXD1
EEDI
MDC
NC
NC
66
74
64
60
73
70
57
54
53
52
75
72
71
69
67
65
63
62
61
59
58
56
55
51
68
DGND 76 50 TXD0
NC 77 49 TX_CLK
LINK_O 78 48 TEST5
WAKEUP 79 47 RX_CLK
PW_RST# 80 46 RX_ER
DGND 81 45 RX_DV
SD15 82 44 COL
SD14 83 43 CRS
SD13 84 42 DGND
SD12 85 41 RXD3
SD11 86 40 RXD2
SD10
SD9
87
88
DM9000 39
38
RXD1
RXD0
SD8 89 37 LINK_I
DVDD 90 36 DVDD
IO16 91 35 AVDD
CMD 92 34 TXO-
SA4 93 33 TXO+
SA5 94 32 AGND
SA6 95 31 AGND
SA7 96 30 RXI-
SA8 97 29 RXI+
SA9 98 28 AVDD
DGND 99 27 AVDD
INT 100 26 BGRES
10
12
13
14
15
16
19
23
17
18
21
24
25
11
20
22
1
2
5
6
7
8
9
3
4
AEN
DVDD
DVDD
IOW#
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
IOWAIT
RST
DGND
DGND
SD
AGND
IOR#
TEST1
TEST2
TEST3
TEST4
X2_25M
X1_25M
Final 5
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
LINKACT#
CLK20MO
SPEED#
GPIO3
GPIO2
GPIO1
GPIO0
DGND
DGND
DVDD
DVDD
DVDD
EEDO
EECS
EECK
DUP#
SD16
SD17
SD18
SD19
EEDI
IO32
NC
NC
NC
66
74
64
60
73
70
57
54
53
52
75
72
71
69
67
65
63
62
61
59
58
56
55
51
68
DGND 76 50 SD20
NC 77 49 SD21
LINK_O 78 48 TEST5
WAKEUP 79 47 SD22
PW_RST# 80 46 SD23
DGND 81 45 SD24
SD15 82 44 SD25
SD14 83 43 SD26
SD13 84 42 DGND
SD12 85 41 SD27
SD11 86 40 SD28
SD10
SD9
87
88
DM9000 39
38
SD29
SD30
SD8 89 37 SD31
DVDD 90 36 DVDD
IO16 91 35 AVDD
CMD 92 34 TXO-
SA4 93 33 TXO+
SA5 94 32 AGND
SA6 95 31 AGND
SA7 96 30 RXI-
SA8 97 29 RXI+
SA9 98 28 AVDD
DGND 99 27 AVDD
INT 100 26 BGRES
10
12
13
14
15
16
19
23
17
18
21
24
25
11
20
22
1
2
5
6
7
8
9
4
3
X2_25M
X1_25M
IOWAIT
AEN
DVDD
DVDD
DGND
DGND
AGND
IOR#
IOW#
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
RST
SD
TEST1
TEST2
TEST3
TEST4
6 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
5. Pin Description
I= Input, O=Output, I/O= Input/Output, O/D= Open Drain, P= Power,
LI= reset Latch Input, #= asserted low
Note: The pins of MII interface are all have a pulled down resistor about 60k ohm internally
Final 7
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
14 RST I Hardware Reset Command, active high to reset the DM9000
6,7,8,9,10,
11,12,13, SD0~15 I/O Processor Data Bus bit 0~15
89,88,87,
86,85,84,
83,82
93,94,95, SA4~9 I Address Bus 4~9
96,97,98 These pins are used to select the DM9000.
When SA9 and SA8 are in high states, and SA7 and AEN are in low
states, and SA6~4 are matched with strap pins TXD2~0, the DM9000 is
selected.
92 CMD I Command Type
When high, the access of this command cycle is DATA port
When low, the access of this command cycle is ADDRESS port
91 IO16 O Word Command Indication
When the access of internal memory is word or dword width, this pin will
be asserted
This pin is low active at default
100 INT O Interrupt Request
This pin is high active at default, its polarity can be modified by EEPROM
setting or strap pin MDC. See the EEPROM content description for detail
56,53,52, SD16~31 (in I/O Processor Data Bus bit 16~31
51,50,49, double word These pins are used as data bus bits 16~31 when the DM9000 is set to
47,46,45, mode) double word mode (the straps pin EEDO is pulled high and WAKEUP is
44,43,41, not pull-high)
40,39,38
37
57 IO32 (in double O Double Word Command Indication
word mode) This pins is used as the double word command indication when the
DM9000 is set to double data word mode, and this pin will be asserted
when the access of internal memory is double word width
This pin is low active at default
Note: The pins of processor interface except SD8,SD9 and IO16 are all have a pulled down resistor about 60k ohm
internally
Final 9
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
34 TXO- O TP TX Output
35 AVDD P TX Power
5.7 Miscellaneous
16,17,18, TEST1~TEST4 I Operation Mode
19 Test 1, 2, 3, 4 = (1, 1, 0, 0) in normal application
10 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Key to Default
In the register description that follows, the default column
takes the form:
<Reset Value>, <Access Type>
Where:
<Reset Value>:
1 Bit set to logic one
0 Bit set to logic zero
X No default value
<Access Type>:
RO = Read only
RW = Read/Write
R/C = Read and Clear
RW/C1=Read/Write and Cleared by write 1
WO = Write only
12 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 13
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
14 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 15
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
16 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
6.13 EEPROM & PHY Address Register ( 0CH )
Bit Name Default Description
7:6 PHY_ADR 01,RW PHY Address bit 1 and 0, the PHY address bit [4:2] is force to 0. Force to 01 if
internal PHY is selected
5:0 EROA 0,RW EEPROM Word Address or PHY Register Address
6.14 EEPROM & PHY Data Register (EE_PHY_L: :0DH EE_PHY_H: :0EH)
Bit Name Default Description
7:0 EE_PHY_L X,RW EEPROM or PHY Low Byte Data
This data is made to write low byte of word address defined in Reg. CH to
EEPROM or PHY
7:0 EE_PHY_H X,RW EEPROM or PHY High Byte Data
This data is made to write high byte of word address defined in Reg. CH to
EEPROM or PHY
Final 17
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
18 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
6.26 Memory Data Read Command without Address Increment Register (F0H)
Bit Name Default Description
7:0 MRCMDX X,RO Read data from RX SRAM. After the read of this command, the read pointer of
internal SRAM is unchanged
6.27 Memory Data Read Command with Address Increment Register (F2H)
Bit Name Default Description
7:0 MRCMD X,RO Read data from RX SRAM. After the read of this command, the read pointer is
increased by 1,2, or 4, depends on the operator mode (8-bit,16-bit and 32-bit
respectively)
6.29 Memory Data Write Command without Address Increment Register (F6H)
Bit Name Default Description
7:0 MWCMDX X,WO Write data to TX SRAM. After the write of this command, the write pointer is
unchanged
Final 19
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
6.30 Memory data write command with address increment Register (F8H)
Bit Name Default Description
7:0 MWCMD X,WO Write Data to TX SRAM
After the write of this command, the write pointer is increased by 1,2, or 4, depends
on the operator mode. (8-bit, 16-bit,32-bit respectively)
20 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
7. EEPROM Format
name Word offset Description
MAC address 0 0~5 6 Byte Ethernet Address
Auto Load Control 3 6-7 Bit 1:0=01: Update vendor ID and product ID
Bit 3:2=01: Accept setting of WORD6 [8:0]
Bit 5:4=01: Accept setting of WORD6 [11:9]
Bit 7:6=01: Accept setting of WORD7 [3:0]
Bit 9:8=01: Accept setting of WORD7 [6:4]
Bit 11:10=01: Accept setting of WORD7 [7]
Bit 13:12=01: Accept setting of WORD7 [8]
Bit 15:14=01: reserved
Vendor ID 4 8-9 2 byte vendor ID (Default: 0A46H)
Product ID 5 10-11 2 byte product ID (Default: 9000H)
pin control 6 12-13 When word 3 bit [3:2]=01, these bits can control the IOR, IOW and INT pins
polarity.
Bit0: Reserved
Bit1: IOR pin is active low when set (default: active low)
Bit2: IOW pin is active low when set (default: active low)
Bit3: INT pin is active low when set (default: active high)
Bit4: INT pin s open-collected (default: force output)
Bit5: Reserved
Bit6: Reserved
Bit7: Reserved
Bit8: Reserved
Final 21
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
RESERVED 10 20-21
RESERVED 11 22-23
Key to Default
Where:
<Reset Value>:
1 Bit set to logic one
0 Bit set to logic zero
X No default value
(PIN#) Value latched from pin # at reset
<Access Type>:
RO = Read Only
RW = Read/Write
<Attribute (s)>:
SC = Self Clearing
P = Value Permanently Set
LL = Latching Low
LH = Latching High
22 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC controller with integrated 10/100 PHY
Final 23
Version: DM9000-DS-F01
April 12, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
0.8 Duplex mode 1,RW Duplex Mode
1 = Full duplex operation. Duplex selection is allowed when Auto-
negotiation is disabled (bit 12 of this register is cleared). With
enabled auto-negotiation, this bit reflects the duplex capability
selected by auto-negotiation
0 = Normal operation
0.7 Collision test 0,RW Collision Test
1 = Collision test is enabled. When set, this bit will cause the COL
signal to be asserted in response to the assertion of TX_EN
0 = Normal operation
0.6-0.0 RESERVED 0,RO Reserved
Write as 0, ignore on read
24 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
operation)
0 = Link is not established
The link status bit is implemented with a latching function, so that the
occurrence of a link failure condition causes the link status bit to be,
and remain cleared until it is read via the management interface
1.1 Jabber detect 0, Jabber Detect
RO/LH 1 = Jabber condition detected
0 = No jabber
This bit is implemented with a latching function. Jabber conditions
will set this bit unless it is cleared by a read to this register through a
management interface or a PHY reset. This bit works only in 10Mbps
mode
Extended Capability
1.0 Extended 1,RO/P
1 = Extended register capable
capability 0 = Basic register capable only
The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9000. The Identifier consists
of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model
revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E
Final 25
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
26 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) – 05
This register contains the advertised abilities of the link partner when received during Auto-negotiation
28 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
This bit is self-clear after reset is completed
MF Preamble Suppression Control
16.2 MFPSC 0, RW
MII frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
16.1 SLEEP 0, RW Sleep Mode
Writing a 1 to this bit will cause PHY to enter the Sleep mode and
power down all circuit except oscillator and clock generator circuit.
When waking up from Sleep mode (write this bit to 0), the
configuration will go back to the state before sleep; but the state
machine will be reset
Remote Loopout Control
16.0 RLOUT 0, RW
When this bit is set to 1, the received data will loop out to the
transmit channel. This is useful for bit error rate testing
Final 29
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
B3 b2 b1 b0
0 0 0 0 In IDLE State
0 0 0 1 Ability Match
0 0 1 0 Acknowledge Match
0 0 1 1 Acknowledge Match Fail
0 1 0 0 Consistency Match
0 1 0 1 Consistency Match Fail
0 1 1 0 Parallel Detects Signal_ link_ ready
0 1 1 1 Parallel Detects Signal_ link_ ready Fail
1 0 0 0 Auto-negotiation Completed Successfully
30 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
9. Functional Description
location 0x0C00 if the end of address (i.e. 16K) is
9.1 Host Interface
reached.
The host interface is the ISA BUS compatible mode.
There are eight IO bases, which are 300H, 310H,
320H, 330H, 340H, 350H, 360H, and 370H. The IO
9.3 Packet Transmission
base is latched from strap pins or loaded from the
EEPROM. There are two packets, sequentially named as index I
and index II, can be stored in the TX SRAM at the
There are only two addressing ports through the
same time. The TX Control Register (02h) controls the
access of the host interface. One port is the INDEX
insertion of CRC and pads. Their statuses are
port and the other is the DATA port. The INDEX port is
recorded at TX Status Register I (03h) and TX Status
decoded by the pin CMD =0 and the DATA port by the
Register II (04h) respectively.
pin CMD =1. The contents of the INDEX port are the
register address of the DATA port. Before the access The start address of transmission is 00h and the
of any register, the address of the register must be current packet is index I after software or hardware
saved in the INDEX port. reset. Firstly write data to the TX SRAM using the
DMA port and then write the byte count to byte_ count
register at TX Packet Length Register (0fch/0fdh). Set
9.2 Direct Memory Access Control the bit 0 of TX Control Register (02h). The DM9000
starts to transmit the index I packet. Before the
The DM9000 provides DMA capability to simplify the
transmission of the index I packet ends, the data of
access of the internal memory. After the programming
the next (index II) packet can be moved to TX SRAM.
of the starting address of the internal memory and
After the index I packet ends the transmission, write
then issuing a dummy read/write command to load the
the byte count data of the index II to BYTE_COUNT
current data to internal data buffer, the desired
register and then set the bit 0 of TX Control Register
location of the internal memory can be accessed by
(02h) to transmit the index II packet. The following
the read/write command registers. The memory’s
packets, named index I, II, I, II,…, use the same way
address will be increased with the size that equals to
to be transmitted.
the current operation mode (i.e. the 8-bit, 16-bit or 32-
bit mode) and the data of the next location will be
loaded into internal data buffer automatically. It is 9.4 Packet Reception
noted that the data of the first access (the dummy
The RX SRAM is a ring data structure. The start
read/write command) in a sequential burst should be
address of RX SRAM is 0C00h after software or
ignored because that the data was the contents of the
hardware reset. Each packet has a 4-byte header
last read/write command.
followed with the data of the reception packet which
The internal memory size is 16K bytes. The first CRC field is included. The format of the 4-byte header
location of 3K bytes is used for the data buffer of the is 01h, status, BYTE_COUNT low, and
packet transmission. The other 13K bytes are used for BYTE_COUNT high. It is noted that the start address
the buffer of the receiving packets. So in the write of each packet is in the proper address boundary
memory operation, when the bit 7 of IMR is set, the which depends on the operation mode (the 8-bit, 16-
memory address increment will wrap to location 0 if bit or 32-bit mode ).
the end of address (i.e. 3K) is reached. In a similar
way, in the read memory operation, when the bit 7 of
IMR is set, the memory address increment will wrap to
Final 31
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
9.5 100Base-TX Operation By scrambling the data, the total energy presented to
the cable is randomly distributed over a wide
The block diagram in figure 3 provides an overview of
frequency range. Without the scrambler, energy levels
the functional blocks contained in the transmit section.
on the cable could peak beyond FCC limitations at
The transmitter section contains the following
frequencies related to the repeated 5B sequences,
functional blocks:
like the continuous transmission of IDLE symbols. The
- 4B5B Encoder scrambler output is combined with the NRZ 5B data
- Scrambler from the code-group encoder via an XOR logic
- Parallel to Serial Converter function. The result is a scrambled data stream with
- NRZ to NRZI Converter sufficient randomization to decrease radiated
- NRZI to MLT-3 emissions at critical frequencies.
- MLT-3 Driver
9.5.3 Parallel to Serial Converter
9.5.1 4B5B Encoder
The Parallel to Serial Converter receives parallel 5B
The 4B5B encoder converts 4-bit (4B) nibble data scrambled data from the scrambler, and serializes it
generated by the MAC Reconciliation Layer into a 5- (converts it from a parallel to a serial data stream).
bit (5B) code group for transmission, see reference The serialized data stream is then presented to the
Table 1. This conversion is required for control and NRZ to NRZI encoder block
packet data to be combined in code groups. The
4B5B encoder substitutes the first 8 bits of the MAC 9.5.4 NRZ to NRZI Encoder
preamble with a J/K code-group pair (11000 10001)
upon transmit. The 4B5B encoder continues to After the transmit data stream has been scrambled
replace subsequent 4B preamble and data nibbles and serialized, the data must be NRZI encoded for
with corresponding 5B code-groups. At the end of the compatibility with the TP-PMD standard, for 100Base
transmit packet, upon the deassertion of the Transmit -TX transmission over Category-5 unshielded twisted
Enable signal from the MAC Reconciliation layer, the pair cable.
4B5B encoder injects the T/R code-group pair (01101
00111) indicating the end of frame. After the T/R 9.5.5 MLT-3 Converter
code-group pair, the 4B5B encoder continuously The MLT-3 conversion is accomplished by converting
injects IDLEs into the transmit data stream until the data stream output, from the NRZI encoder into
Transmit Enable is asserted and the next transmit two binary data streams, with alternately phased logic
packet is detected. one event.
32 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Table 1
Final 33
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
34 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC controller with integrated 10/100 PHY
Col lis i on d etec t io n is d is a ble d in F u ll Dup le x
9.6.8 Code Group Alignment
operation.
The Code Group Alignment block receives un-aligned
5B data from the descrambler and converts it into 5B
9.9 Carrier Sense
code group data. Code Group Alignment occurs after
the J/K is detected, and subsequent data is aligned on Carrier Sense (CRS) is asserted in half-duplex
a fixed boundary. operation during transmission or reception of data.
During full-duplex mode, CRS is asserted only during
receive operations.
9.6.9 4B5B Decoder
The 4B5B Decoder functions as a look-up table that
9.10 Auto-Negotiation
translates incoming 5B code groups into 4B (Nibble)
data. When receiving a frame, the first 2 5-bit code The objective of Auto-negotiation is to provide a
groups receive the start-of-frame delimiter (J/K means to exchange information between linked
symbols). The J/K symbol pair is stripped and two devices and to automatically configure both devices to
nibbles of preamble pattern are substituted. The last take maximum advantage of their abilities. It is
two code groups are the end-of-frame delimiter (T/R important to note that Auto-negotiation does not test
Symbols). the characteristics of the linked segment. The Auto-
Negotiation function provides a means for a device to
The T/R symbol pair is also stripped from the nibble,
advertise supported modes of operation to a remote
presented to the Reconciliation layer.
link partner, acknowledge the receipt and
understanding of common modes of operation, and to
9.7 10Base-T Operation reject un-shared modes of operation. This allows
devices on both ends of a segment to establish a link
The 10Base-T transceiver is IEEE 802.3u compliant.
at the best common mode of operation. If more than
When the DM9000 is operating in 10Base-T mode,
one common mode exists between the two devices, a
the coding scheme is Manchester. Data processed for
mechanism is provided to allow the devices to resolve
transmit is presented to the MII interface in nibble
to a single mode of operation using a predetermined
format, converted to a serial bit stream, then the
priority resolution function.
Manchester encoded. When receiving, the bit stream,
encoded by the Manchester, is decoded and Auto-negotiation also provides a parallel detection
converted into nibble format to present to the MII function for devices that do not support the Auto-
interface. negotiation feature. During Parallel detection there is
no exchange of information of configuration. Instead,
the receive signal is examined. If it is discovered that
9.8 Collision Detection
the signal matches a technology, which the receiving
For half-duplex operation, a collision is detected when device supports, a connection will be automatically
the tr a n s m it and r ec ei ve c ha nn el s ar e ac ti v e established using that technology. This allows devices
simultaneously. When a collision is detected, it will be not to support Auto-negotiation but support a common
reported by the COL signal on the MII interface. mode of operation to establish a link.
Final 35
Version: DM9000-DS-F01
April 12, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
9.11 Power Reduced Mode
9.11.1 Power Down Mode
The Signal detect circuit is always turned to monitor whether
there is any signal on the media (cable disconnected). The The Reg.0.11 of MII register can be set high to enter the
DM9000 automatically turns off the power and enters the Power Down mode, which disables all transmit, receive
Power Reduced mode, whether its operation mode is N- functions and MII interface functions, except the MDC/MDIO
way or force mode. When enters the Power Reduced management interface.
mode, the transmit circuit still sends out fast link pules with
minimum power consumption. If a valid signal is detected 9.11.2 Reduced Transmit Power Mode
from the media, which might be N-ways fast link pules,
10Base-T normal link pules, or 100Base-TX MLT3 signals, The additional Transmit power reduction can be
the dev ic e will wak e up and res um e a norm al gained by designing with 1.25:1 turns ration magnetic
operation mode. on its TX side and using a 8.5KΩ resistor on BGRES
and AGND pins, and the TXO+/TXO- pulled high
That can be writing Zero to Reg.16.4 of MII register to
resistors should be changed from 50 Ω to 78 Ω .
disable Power Reduced mode.
This configuration could be reduced about 20%
transmit power.
36 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Comments
Stresses above, which are listed under “Absolute sections of this specification, is not implied. Exposure
Maximum Ratings”, may cause permanent damage to to absolute maximum rating conditions for extended
the device. These are stress ratings only. Functional periods may affect the reliability of the device.
operation of this device at these or any other
conditions above, which indicated in the operational
Final 37
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
38 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
10.4.1 TP Interface
Symbol Parameter Min. Typ. Max. Unit Conditions
tTR/F 100TX+/- Differential Rise/Fall Time 3.0 - 5.0 ns
tTM 100TX+/- Differential Rise/Fall Time 0 - 0.5 ns
Mismatch
tTDC 100TX+/- Differential Output Duty Cycle 0 - 0.5 ns
Distortion
tT/T 100TX+/- Differential Output Peak-to-Peak 0 - 1.4 ns
Jitter
XOST 100TX+/- Differential Voltage Overshoot 0 - 5 %
→ T1 ← → T5 ←
AEN,SA ,CMD
IOR
← T2 ← T6 →
→
SD
← T3 → → ← T4
Note 1.2
IO16,IO32
→ ← T8
→ ← T7
Final 39
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Note::
1. The IO16 is valid when the SD bus width is 16-bit or 2. The IO32 is valid when the SD bus width is 32-bit,
32-bit, and the system address is data port (i.e. the system address is data port (i.e. CMD is high)
CMD is high) and the value of address port is and the value of address port is memory data
memory data register index.(ex. F0H, F2H, F6H or register index(ex. F0H, F2H, F6H or F8H)
F8H)
→ T1 ← → ← T5
AEN,SA,CMD
← T6 →
IOW ← T2 → ∫∫
→ ← T4
SD
← T3 →
IO16,IO32 Note1.2
→ ← T8
→ ← T7
Note: :
1. The IO16 is valid when the SD bus width is 16-bit or 2. The IO32 is valid when the SD bus width is 32-bit
32-bit and system address is data port (i.e. CMD is and system address is data port (i.e. CMD is high)
high) and the value of address port is memory data and the value of address port is memory data
register index (ex. F0H, F2H, F6H or F8H) register index (ex. F0H, F2H, F6H or F8H)
40 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
T2
← →
TXCK ∫∫
∫∫
TXEN
→ T1 ←
TXD[3:0] ∫∫
RXCK
∫∫
RXER,RXDV
→ T1 ← → T2 ←
RXD[3:0] ∫∫
Final 41
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
← T1 →
MDC
→ T2 ←
T3 → ← T5
MDIO (drive by DM9601) → ←
→ ← T2
EESS
→ T1 ←
EECK ∫∫
→ T4 ←
EEDO
→ ← T5 → T6 ←
EEDI
→ T7 ←
42 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final 43
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
RXI+
29 Transformer RJ45
50
Ω
1% 1:1
3
30
RXI- 0.1µF
50 6
Ω
1% AGND
3.3V AVDD
1
0.1µF
4
0.1µF
DM9000 50Ω
1%
AGND 5
AGND
1:1
33 2
TX0+
3.3V AVCC
50Ω
1%
7
34 8
TX0-
0.1µF
75 75
26 75Ω Ω Ω
BGRES 1% 75 1%
AGND 1% Ω
25 6.8KΩ, 1% 1%
BGGND
0.1µF/2KV
Figure 11-1
44 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
RXI+
29
50
Transformer RJ45
Ω
1% 1:1
3
30
RXI- 0.1µF
50 6
Ω
1% AGND
3.3V AVDD
1
0.1µF
4
0.1µF
DM9000 78Ω
1% AGND 5
AGND 1.25:1
33
TX+
2
78Ω 3.3V AVCC
1% 7
34
TX0- 8
0.1µF
75
26 75
75Ω Ω
BGRES 1% 75
Ω
AGND 1% Ω 1%
25 1%
BGGND 8.5KΩ, 1%
0.1µF/2KV or 0.01µF/
2KV
Chasis GND
AGND
Figure 11-2
Final 45
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Davicom Semiconductor recommends placing all the decoupling capacitor is 0.1μF or 0.01μF, as required by
decoupling capacitors for all power supply pins as close as the design layout.
possible to the power pads of the DM9000 (The best placed
distance is < 3mm from pin). The recommended
90 73
5 72
DM9000
20
55
27 28 35 36
Figure 11-3
46 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Davicom Semiconductor recommends a single ground network interface card not comply with specific FCC
plane approach to minimize EMI. Ground plane partitioning regulations (part 15). Figure 4 shows a recommended
can cause increased EMI emissions that could make the ground layout scheme.
Figure 11-4
Final 47
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
The power planes should be approximately illustrated in EXCCL4532U or equivalent. A 10μF electrolytic bypass
Figure 5. The ferrite bead used should perform an capacitors should be connected between VDD and Ground
impedance at least 75Ω at 100MHz. A suitable bead is at the device side of each of the ferrite bead.
the Panasonic surface mound bead, part number
Figure 11-5
48 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Refer to Table 2 for transformer requirements. using them in an application. The transformers listed
Transformers, meeting these requirements, are in Table 2 are electrical equivalents, but may not be
available from a variety of magnetic manufacturers. pin-to-pin equivalents.
Designers should test and qualify all magnetics before
X2_25M X1_25M
21 22
Y1 25M
C18 C19
22pf 22pf
AGND AGND
Figure 11-6
Crystal Circuit Diagram
Final 49
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
RXCLK TXCLK
TXCLK RXCLK
RXD0 TXD0
RXD1 TXD1
RXD2 TXD2
RXD3 TXD3
TXD0 RXD0
TXD1 RXD1
DM9000 TXD2 RXD2
SWITCH
TXD3 RXD3 HUB
RXDV TXEN
TXEN
RXDV
CRS CRS
COL COL
RXER RXER
TXER
MDC MDC
MDIO MDIO
Figure 11-7
Note: When operating DM9000 at Reverse MII mode, pin 87 is pulled high . At this application, the txclk , col and crs
pins will be changed from input to output.
50 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
50
76
HE
E
F
100
26
1 25
e b GD
~
~
GD
c
A2
See Detail F
A1
Seating Plane y L
D
L1 Detail F
Symbol Dimensions In Inches Dimensions In mm
A 0.063 Max. 1.60 Max.
A1 0.004 ± 0.002 0.1 ± 0.05
A2 0.055 ± 0.002 1.40 ± 0.05
b 0.009 ± 0.002 0.22 ± 0.05
c 0.006 ± 0.002 0.15 ± 0.05
D 0.551 ± 0.005 14.00 ± 0.13
E 0.551 ± 0.005 14.00 ± 0.13
e 0.020 BSC. 0.50 BSC.
F 0.481 NOM. 12.22 NOM.
GD 0.606 NOM. 15.40 NOM.
HD 0.630 ± 0.006 16.00 ± 0.15
HE 0.630 ± 0.006 16.00 ± 0.15
L 0.024 ± 0.006 0.60 ± 0.15
L1 0.039 Ref. 1.00 Ref.
y 0.004 Max. 0.1 Max.
θ 0° ~ 12° 0° ~ 12°
Notes:
1. Dimension D & E do not include resin fins.
2. Dimension GD is for PC Board surface mount pad pitch design reference only.
3. All dimensions are based on metric system.
Final 51
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
13. APPENDIX:
Before Modification
4 BKPM 0,RW Back pressure mode. This mode is for half duplex mode only. Generate a jam
pattern when a packet’s DA match and RX SRAM over BPHW
3 BKPA 0,RW Back pressure mode. This mode is for half duplex mode only. Generate a jam
pattern when any packet coming and RX SRAM over BPHW
Table A-1-A
After Modification
4 BKPA 0,RW Back pressure mode. This mode is for half duplex mode only. Generate a jam
pattern when any packet coming and RX SRAM over BPHW
3 BKPM 0,RW Back pressure mode. This mode is for half duplex mode only. Generate a jam
pattern when a packet’s DA match and RX SRAM over BPHW
Table A-1-B
Before Modification
16,17,18, TEST1~TEST4 I Operation Mode
19 Test1,2,3,4=(1,1,0,0) : the processor interface is ISA compatible
Test1,2,3,4=(1,1,0,1) : the processor interface is for general processor
Table A-2-A
After Modification
16,17,18, TEST1~TEST4 I Operation Mode
19 Test1,2,3,4=(1,1,0,0) in normal application
Table A-2-B
Before Modification
Bit Name Default Description
2:1 LBK 00,RW Loopback mode
Bit 2 1
0 0 normal
0 1 MAC internal loopback
1 0 internal PHY digital loopback
1 1 internal PHY analog loopback
Table A-3-A
52 Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
After Modification
Bit Name Default Description
2:1 LBK 00,RW Loopback mode
Bit 2 1
0 0 normal
0 1 MAC internal loopback
1 0 internal PHY 100M mode digital loopback
1 1 (Reserved)
Table A-3-B
Before Modification
Symbol Parameter Min. Typ. Max. Unit
T3 SD Setup time 5 ns
T6 IOW invalid to next IOW (access DM9000) 80 ns
TableA-4-A
After Modification
Symbol Parameter Min. Typ. Max. Unit
T3 SD Setup time 22 ns
T6 IOW invalid to next IOW (access DM9000) 84 ns
Table A-4-B
Final 53
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Contact Windows
For additional information about DAVICOM products, contact the sales department at:
Headquarters
Hsin-chu Office: Sales & Marketing Office:
3F, No. 7-2, Industry E. Rd., IX, 2F, No. 5, Industry E. Rd., IX,
Science-based Park, Hsin-chu City, Taiwan, R.O.C.
Hsin-chu City, Taiwan, R.O.C. TEL: 886-3-5798797
TEL: 886-3-5798797 FAX: 886-3-5646929
FAX: 886-3-5798858 Email: sales@davicom.com.tw
Web site: http://www.davicom.com.tw
WARNING
Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near
the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function.
54 Final
Version: DM9000-DS-F02
June 26, 2002
This datasheet has been downloaded from:
www.DatasheetCatalog.com