Benq q7c4 PDF
Benq q7c4 PDF
Benq q7c4 PDF
P/N: 99.L0Y72.ESE/ESA/EST
Page : 1 / 1
FP71V+(Q7C4) LCD Monitor Service Guide
Circuit Operation Theory
I. Introduction:
The Q7C4 is a 17” SXGA (1280x1024), 16.2M colors (R/G/B 6-bit + FRC) TFT LCD monitor with multi-media
function. It’s a Dual (analog and digital) interface LCD monitor with a 15 pins D-sub signal cable and a 24 pins
DVI-D cable. It’s compliant with VESA specification to offer a smart power management and power saving
function. It also offers OSD menu for users to control the adjustable items and get some information about this
monitor, and the best function is to offer users an easy method to set all adjustable items well just by pressing one
key, we called it “I-Key” which can auto adjusting all controlled items. Q7C4 also offer DDC2 function to meet
VESA standard.
Control board
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FP71V+(Q7C4) LCD Monitor Service Guide
Circuit Operation Theory
PMC Clock
39LV020 Generator
D-SUB 140MHz
ADC
GM5221
140MHz
DVI-D
Single Link
TMDS
IIC Keypad
SPI EEPROM
SXGA
1280×1024 VTI 3601(OD)
LCM
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FP71V+(Q7C4) LCD Monitor Service Guide
Circuit Operation Theory
(a) Circuit operation theory:
A basic operation theory for the interface board is to convert input signal into digital RGB.
Analog RGB signal is converted to digital signal through ADC. DVI-D signal is converted
through TMDS receiver. The microprocessor GM5221 receives video data and optimizes
the image automatically. It also supports input source selection, 16 color from a 64k palette
bitmap OSD, and keypad controlling. The output data are sent to LCD module.
(b) IC introduction:
1) DDC (Display Data Channel) function: We use DDC IC to support DDC2B function. DDC data
is stored in 24C02(EEPROM). Those data related to LCD monitor specification. PC can read
them by “SDA” and “SCL” serial communication for I²C communication for DDC2B.
2) GM5221 IC: There are A/D, Scaling and OSD functions in the GM5221 IC. Scaling IC is
revolutionary scaling engine, capable of expanding any source resolution to a highly uniform and
sharp image, combined with the critically proven integrated 8 bit triple-ADC and patented
Rapid-lock digital clock recovery system. It also support detect mode and DPMS control.
3) EEPROM: We use 24C16 to store all the adjustable data and user settings, and use two 24C02s
to store DVI and D-Sub EDID data.
4) PMC 39LV020: FrashROM. It contains final firmware.
5) VTI3601 IC: OverDrive IC. It can decrease the LCD response time.
6) ATMEL 25F512N: Serial EEPROM. It store OD table.
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FP71V+(Q7C4) LCD Monitor Service Guide
Circuit Operation Theory
A-2.) Power board diagram:
EMI Filter Rectifier and Isolation power Rectifier and filter Inverter circuit
filter transformer
LDO regulator
Feedback Isolation
Fig.1
#1 EMI Filter
This circuit (Fig. 2) is designed to inhibit electrical and magnetic interference for meeting FCC,
VDE, VCCI standard requirements.
Fig. 2
#2 Rectifier and filter
AC Voltage (90-264V) is rectified and filtered by BD601, C605 (See Fig 3) and the DC Output
voltage is 1.4*(AC input). (See Fig.3)
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FP71V+(Q7C4) LCD Monitor Service Guide
Circuit Operation Theory
Fig. 3
Fig. 4
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Circuit Operation Theory
#4 Rectifier and filter
D701 and C703 C704 are to produce DC output. (See Fig.5)
Fig. 5
#5 PWM Controller
The PWM controller NCP1200A implements a standard current mode architecture. With an
internal structure operating at a fixed 40KHz.Where the switch time is dictated by the peak
current setting-point. When the current setting-point falls below a given value. The output power
demand diminish, the IC automatically enters the so-called skip cycle mode and provides
excellent efficiency.
Fig. 6
#6 Feedback circuit
PC123 is a photo-coupler and TL431 is a shunt regulation. They are used to detect the output
voltage change and be the primary and secondary isolation. When output voltage changes, the
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FP71V+(Q7C4) LCD Monitor Service Guide
Circuit Operation Theory
feedback voltage will be compared and duty cycle will be decided to control the correct output
voltage. (See Fig.7)
Fig.7
2. General Specification
Input Voltage: 14.5V
Input Current: 2A max.
ON/OFF Voltage: 3.3V
Output Requirement:
Max. Output Current: 8mA
Min. Output Current: 3mA
Lamp Working Voltage: 700Vrms
Open Lamp Voltage: 1500Vrms
Frequency: 40-80KHz
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Circuit Operation Theory
3.1 ON/OFF SWITCH
The turn-on voltage was controlled by R815 and R816.The inverter was turned on or off
by the switching transistors Q801 and Q802, Also regulator IC801 is control by Q801
and Q802 decide supply 12.5V to inverter part or instead.
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Circuit Operation Theory
3.2 PWM Control circuit
TL1451 is a dual PWM controller. C807 and R811 decide the working frequency.
BLT_ADJ signal is from control board, control pulse width then decide how much
energy delivery to CCFL also decide CCFL brightness. Q803 and Q804 be the buffer to
rise the drive capability and the totem poles circuit can improve a capable of driving for
Q805.C813 decide the striking time delay.
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Circuit Operation Theory
3.3 Oscillator Circuit
Royer circuit uses the characteristic of transformer saturation to oscillate. When the DC power
inject, Q808 or Q809 will turns on, and the current Ic increases. After a period, the transistor will
leave the saturation status and Vce increase. The result causes the voltage of primary coil get
lower. Finally the transistor turn off, and another transistor turn on. These statuses are repeated
and the pin7 and pin8 of T801 will get a Sin Wave to turn on CCFL.
Connect with
PC Audio output
DC POWER AUDIO
Connect with INPUT INPUT
8 ohm/2W
Speaker
POWER IC
TDA7496
The audio block consists of an audio board and dual speaker drivers. The speaker drivers are
using 62 x 33 x 20 mm2 audio box (rated 2W/CH) with DC volume control, power is supplied
by power board and audio input is from PC audio output (Line Out).
1. Power IC: Use ST POWER IC TDA7496 which is stereo AB Class output amplifiers with
DC volume control. The devices are designed for use in TV and monitor, but
are also suitable for battery-feed portable recorders and radios. Use +14.5V
from power board and connect speaker drivers to offer 1W/CH.
2. DC Power Input: To supply +14.5V for TDA7496 power source.
3. Audio Input: Connect with PC audio output in 3.5mm to 3.5mm signal line.
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Circuit Operation Theory
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4. Speaker driver: Use 8 ohm / 62 x 33 x 20 mm speaker driver (rated 2W/CH).
5. DC Volume Control: The voltage range is 0 ~ 3.3V (from MCU).
(b) LED: It indicates the DPMS status of this LCD monitor; blue light means DPMS on
(Normal operating condition), amber light means DPMS off (Power off condition).
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Trouble Shooting
Q7C4 TROUBLE SHOOTING GUIDE
1. No Display or display is unstable
Interface Board -
No picture or picture
unstable
Y
Power off? Turn on power.
Y N
Is power stable? Check power BD.
Y
N
Is LED light blue? Check control BD.
Y N
Does DVI signal work? Check (U1) DDC data.
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Trouble Shooting
Y N
Does crystal work Check crystal (Y2) CKT or replace it.
correctly?
Y N
Y
N
Does LVDS cable Plug LVDS cable again or replace it.
connect to panel?
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Trouble Shooting
2. BUTTON function
Control board -
Y N
Is button switch
working? Replace control BD then
Check Interface BD N
L7~L12, R55~R60, Replace component then
R41, R42, RN1, RN2
OK?
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Trouble Shooting
3. OSD function
Check Interface BD
4. OD function
Picture Abnormal
N
OSD display OK? Change another I/F BD
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Trouble Shooting
4. Power Board
Y Y
IC801 PIN 9 IS
Check IC801 LED shined?
12~16V?
N N
N Y
Plug CN701 again or PWM existed?
3.3V existed? IS I/F board connected?
checking I/F BD (BLT_ADJ)
Y Y N
Y
Replace new fuse
N Y
Check CN801~CN804
Insert them again Check IC701 OK? Replace IC701
was pluged properly?
Y
N
Replace
IC801,Q805,Q812 Y
Checking F601
Replace new fuse
Broke?
Y
Check IC601 Vcc
Replace IC601,Q602,
existed?
Replace IC602,
IC702,D701 or check
I/F BD
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FP71V+(Q7C4) LCD Monitor Service Guide
Alignment Procedure
Table of Contents
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FP71V+(Q7C4) LCD Monitor Service Guide
Alignment Procedure
1. Alignment procedure (for function adjustment)
The list of necessary alignment for a LCD monitor
A. Preparation
1. Setup input timing to any preset modes or patterns.
2. Enter factory mode (press “EXIT” & “ENTER” & “Power” buttons at the same time to turn on monitor).
3. Press “I-Key” into “Burn In Mode” tag and select “On” to enable burn-in mode.
4. Power off the monitor, remove the input source and then power on again.
5. Setup unit and keep it warm up for at least 30 minutes.
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Alignment Procedure
1. Setup input timing UVGA7 (1024x768/75Hz), pattern 42 (5-Mosaic pattern with white color block) with Analog
signals from Chroma video pattern generator. (it depends on Scaler IC supplier’s recommendation)
2. Enter factory mode (press “EXIT” & “ENTER” & “Power” buttons at the same time to turn on monitor).
3. Press “I-Key” into “Burn In Mode” tag and select “On” to enable burn-in mode.
4. Change color temperature from “Reddish” (default) to “User Preset”.
5. Press hot-key “CONTRAST” to run “White Balance” function. (This procedure will get optimal gain/offset (clamp)
values)
6. Checking if the picture is ok, or reject this monitor and check its circuit board or wire/cable connection.
F. Command definition
PC Host will send 0x7C IIC slave address and then following 4 bytes command
I2C Send Command Byte1 Byte2 Byte3 Byte4 OK N.A. Remark
Write Contrast to MCU RAM CA 55 Data cksum √
Write Brightness to MCU RAM CA 56 Data cksum √ Write data to MCU RAM and
Write Red Gain to MCU RAM CA 57 Data cksum √ update the related register to
Write Green Gain to MCU RAM CA 58 Data cksum √ refresh the screen immediately.
Write Blue Gain to MCU RAM CA 59 Data cksum √ Don’t store data to EEPROM.
Read Contrast from MCU RAM C3 55 XX cksum √
Read Brightness from MCU RAM C3 56 XX cksum √
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FP71V+(Q7C4) LCD Monitor Service Guide
Alignment Procedure
Read Red Gain from MCU RAM by color index C3 57 XX cksum √
Read Green Gain from MCU RAM by color
index C3 58 XX cksum √ Base on current color index to
Read Blue Gain from MCU RAM by color index C3 59 XX cksum √ read back the right gain value.
Write C1 (Bluish) R-Gain Data to EEPROM AA 3C Data cksum √
Write C1 (Bluish) G-Gain Data to EEPROM AA 3D Data cksum √
Write C1 (Bluish) B-Gain Data to EEPROM AA 3E Data cksum √
Write C2 (sRGB) R-Gain Data to EEPROM AA 4C Data cksum √
Write C2 (sRGB) G-Gain Data to EEPROM AA 4D Data cksum √
Write C2 (sRGB) B-Gain Data to EEPROM AA 4E Data cksum √
Write C3 (Reddish) R-Gain Data to EEPROM AA 5C Data cksum √
Write C3 (Reddish) G-Gain Data to EEPROM AA 5D Data cksum √
Write C3 (Reddish) B-Gain Data to EEPROM AA 5E Data cksum √
Write User R-Gain Data to EEPROM AA 6C Data cksum √
Write User G-Gain Data to EEPROM AA 6D Data cksum √
Write User B-Gain Data to EEPROM AA 6E Data cksum √
Write Cx R-Gain Data to EEPROM AA 7C Data cksum √
Write Cx G-Gain Data to EEPROM AA 7D Data cksum √ Reserved for some model have
Write Cx B-Gain Data to EEPROM AA 7E Data cksum √ extra color temperature
Write Contrast to EEPROM AA 92 Data cksum √
Write Brightness to EEPROM AA 93 Data cksum √
1=C1/9300/Bluish,
2=C2/6500/sRGB,
3=C3/5800/Reddish,
4=User, 5=Cx
Write C/T index to EEPROM AA 94 0~4 cksum √
Write OSD-Hpos to EEPROM AA 95 Data cksum √
Write OSD-Vpos to EEPROM AA 96 Data cksum √
0=DE, 1=EN, 2=ES, 3=FR,
4=IT, 5=JA, 6=繁中, 7=簡中
Write Language to EEPROM AA 97 0~7 cksum √ (Also Update MCU RAM)
Write EEPROM OSD Timer AA 98 Data cksum √
Write EEPROM Volume AA 99 Data cksum √
For model with Gamma curve
Write EEPROM Gamma index AA 9A Data cksum √ selection function
Write OSD Transparency to EEPROM AA 9E Data cksum √
Write OSD Rotation to EEPROM AA 9F Data cksum √
Read C1 (Bluish) R-Gain data from EEPROM A3 3C XX cksum √
Read C1 (Bluish) G-Gain data from EEPROM A3 3D XX cksum √
Read C1 (Bluish) B-Gain data from EEPROM A3 3E XX cksum √
Read C2 (sRGB) R-Gain data from EEPROM A3 4C XX cksum √
Read C2 (sRGB) G-Gain data from EEPROM A3 4D XX cksum √
Read C2 (sRGB) B-Gain data from EEPROM A3 4E XX cksum √
Read C3 (Reddish) R-Gain data from EEPROM A3 5C XX cksum √
Read C3 (Reddish) G-Gain data from EEPROM A3 5D XX cksum √
Read C3 (Reddish) B-Gain data from EEPROM A3 5E XX cksum √
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FP71V+(Q7C4) LCD Monitor Service Guide
Alignment Procedure
Read User R-Gain data from EEPROM A3 6C XX cksum √
Read User G-Gain data from EEPROM A3 6D XX cksum √
Read User B-Gain data from EEPROM A3 6E XX cksum √
Read Cx R-Gain data from EEPROM A3 7C XX cksum √
Read Cx G-Gain data from EEPROM A3 7D XX cksum √ Reserved for some model have
Read Cx B-Gain data from EEPROM A3 7E XX cksum √ extra color temperature
Read Contrast from EEPROM A3 92 XX cksum √
Read Brightness from EEPROM A3 93 XX cksum √
1=C1/9300/Bluish,
2=C2/6500/sRGB,
3=C3/5800/Reddish, 4=User,
Read C/T index from EEPROM A3 94 XX cksum √ 5=Cx
Read OSD-Hpos EEPROM A3 95 XX cksum √
Read OSD-Vpos from EEPROM A3 96 XX cksum √
0=DE, 1=EN, 2=ES, 3=FR,
Read Language from EEPROM A3 97 XX cksum √ 4=IT, 5=JA, 6=繁中, 7=簡中
Read OSD Timer from EEPROM A3 98 XX cksum √
Read Volume from EEPROM A3 99 XX cksum √
For model with Gamma curve
Read Gamma index from EEPROM A3 9A XX cksum √ selection function
Read OSD Transparency from EEPROM A3 9E XX cksum √
Read OSD Rotation from EEPROM A3 9F XX cksum √
Change Color Temp. to C1/9300K/Bluish CC 01 XX cksum √
Change Color Temp. to C2/6500K/sRGB CC 02 XX cksum √
Change Color Temp. to C3/5800K/Reddish CC 03 XX cksum √ Change C/T immediately. And
Change Color Temp. to User CC 04 XX cksum √ store C/T index to EEPROM.
Change Color Temp. to Cx CC 05 XX cksum √ Reserved
Change Input Source to D-Sub CD 01 XX cksum √
Change Input Source to DVI CD 02 XX cksum √
On burn in mode CE 01 XX cksum √ Store data to EEPROM
XX* = Non “1” value
Off burn in mode CE XX* XX cksum √ Store data to EEPROM
Monitor is forced power saving CF 01 XX cksum √
Monitor wake up from power saving CF XX* XX cksum √ XX* = Non “1” value
User mode to factory mode 1A 5A XX cksum √
Auto Color (Offset1, Offset2, Gain) 1B 5A XX cksum √
For specified “Industry
Copy EDID Serial number to EEPROM 1C 5A XX cksum √ Customer” model.
Factory mode to User mode 1E 5A XX cksum √
Clear user mode and factory recall 1F 5A XX cksum √ Store data to EEPROM
Write EDID data to MCU DDC RAM 55 NA NA NA √ For MTV312 MCU type
Copy DDC RAM data to EEPROM BB NA NA NA √ For MTV312 MCU type
Drive WP pin to low to enable write DDC IC 55 NA NA NA √ For stand alone DDC IC
Drive WP pin to high to disenable write function BB NA NA NA √ For stand alone DDC IC
EEPROM Bank R/W (For Debug using only, not for Production Line Write EEPROM directly)
Read EEPROM Bank 0 B0 Address XX cksum √
Read EEPROM Bank 1 B1 Address XX cksum √
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FP71V+(Q7C4) LCD Monitor Service Guide
Alignment Procedure
Read EEPROM Bank 2 B2 Address XX cksum √ (For 24C08 type)
Read EEPROM Bank 3 B3 Address XX cksum √ (For 24C08 type)
Write EEPROM Bank 0 B8 Address Data cksum √
Write EEPROM Bank 1 B9 Address Data cksum √
Write EEPROM Bank 2 BA Address Data cksum √ (For 24C08 type)
Write EEPROM Bank 3 BB Address Data cksum √ (For 24C08 type)
Note A: Byte4 (cksum) = Byte1 + Byte2 + Byte3
Note B: Data = The value write to MCU or EEPROM
Note C: XX = don't care, any value (<=0xFF).
When PC Host sends 0x7D command to MCU, MCU must return as following (2 bytes)
Return Code R-Byte1 R-Byte2
Checksum error code FC AA
Normal return code the above Byte3 (/data) FC
If normal return code is exact FCh FC CF
2. EEPROM mapping
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Alignment Procedure
Reject criteria:
(a) Playback sound is not clear or distorted.
(b) Loss of high or low frequencies.
(c) Abnormal or no sound is heard.
Reject criteria:
(a) Both left and right channels sounded.
(b) The left and right channels playback are reversed.
(c) Abnormal or no sound is heard during right or left channels playback.
Reject criteria:
(a) The sound output level is not decrease or increase smoothly.
(b) Abnormal sound is heard during the volume control is turning.
(c) Sound is heard when the volume control turn to minimum.
(d) No increase or decrease of sound level when turning the volume control.
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FP71V+(Q7C4) LCD Monitor Service Guide
Alignment Procedure
(a) Playback and listen to the music.
(b) Into power saving mode, the Left and Right speakers is muted.
Reject criteria:
(a) The Left & Right speakers output are not muted.
(b) One of the Left or Right speaker is not muted.
4. Wire Dressing
- Assembly step by step
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Alignment Procedure
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FP71V+(Q7C4) LCD Monitor Service Guide
Alignment Procedure
E. Dress the wire which is connected to I/F BD as above left picture showed to avoid any interference
against with the Upcase.
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Alignment Procedure
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Alignment Procedure
H. Insert the LVDS FFC into the panel connector and stick the yellow tape on them.
I. Assembly the I/F & Power BD together with the Main Bracket.
J. Screw up the boards (6 screws) and connect wires (lamp wires & FFC).
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Alignment Procedure
L. Stick the yellow tape to make the FFC flatten along the Main Bracket.
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Alignment Procedure
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Alignment Procedure
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Alignment Procedure
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Alignment Procedure
6. Add Glue
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5 4 3 2 1
D D
M301
CON301 SW301 3
KEY_MENU CON302 C301 0.47u R301 75 3
1 1 2
2 1 5 5
3 LED301 BLU/ORG 4
G1 G2 2 4
4 3 2 2
5 BLU A2
SW302 4 C302 0.47u R302 75
6 J 1 1
7 ORG A1 KEY_ RIGHT 1 2 2060089104 6 6
8 7 7
9
G1 G2 C9 C10 L301 2210165031
10
A
100P K 100P K 45 OHM
2060089110 SW303 CON303
C1 KEY_LEFT 1 2 ZD301 1
100P K 5.6V 1
C2 C8 2
G1 G2 2
K K
C 100P K 100P K C
C3 C7 2060091102
1 2
100P K 100P K SW306 ZD302 C11
C4 C6 PW_SW 5.6V 100P K
100P K 100P K
C5
3 4
A
100P K CON304
1 1
SW304
KEY_EXIT 1 2 2 2
2060091102
G1 G2
SW305
I _KEY 1 2
G1 G2
B B
R303 0
Spring holes
OP1 OP2
OP OP
Project Code Model Name OEM/ODM Model Name
99.L0Y72.001 Q7C4 NA
Title
A
CTRL BOARD A
Table of Contents
1. Introduction 3
2. Operational Specification 3
2.1 Power supply ................................................................................................................................ 3
2.2 Signal interface ............................................................................................................................. 4
2.3 Video performance ....................................................................................................................... 5
2.4 Scan range .................................................................................................................................... 5
2.5 Plug & Play DDC2B Support....................................................................................................... 6
2.6 Support Timings ........................................................................................................................... 6
4. LCD Characteristics 9
4.1 The Physical definition & Technology summary of LCD panel................................................... 9
4.2 Optical characteristics of LCD panel............................................................................................ 9
5. User Controls 10
5.1 User’s hardware control definition ............................................................................................... 10
5.2 OSD control function definition ................................................................................................... 10
6. Mechanical Characteristics 11
6.1 Dimension..................................................................................................................................... 11
6.2 Weight........................................................................................................................................... 11
6.3 Plastic ........................................................................................................................................... 11
6.4 Carton ........................................................................................................................................... 12
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FP71V+(Q7C4) LCD Monitor Service Guide
Engineering Specification
Table of Contents
8. Certification 13
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FP71V+(Q7C4) LCD Monitor Service Guide
Engineering Specification
1. Introduction
This specification describes Q7C4, which is a 17.0” analog and digital interface color TFT LCD monitor with
audio. The monitor supports up to 1280x1024 pixel resolution and refresh rate of 75 Hz. The independent 6 bits
R, G, B colors are capable of displaying 16.2M colors (RGB-6bit + FRC data). In addition, dithering function is
supported. The features summary is shown below,
*All panel spec. in C201 definition depends on the variance of panel source.
Feature items Specifications Remark
Panel supplier & module name Yes AUO M170EG01 V.3
Screen diagonal Yes 432(17.0”)
Display Format Yes RGB
Pixel Pitch Yes 0.264x0.264
Viewing Angle (@ Contrast Ratio = 10) Yes 70/70/70/60
Analog interface with Scaling supported Yes Genesis GM5221
DVI interface with Scaling supported Yes Genesis GM5221
Video interface with Scaling supported No
Max resolution mode supported Yes 1280x1024@76Hz
Number of Display Colors supported Yes 16.2M
Contrast Ratio Yes 500:1
Luminance Yes 400
AC power input Yes 90~264V
DC power input (with AC power adapter) No
DPMS supported Yes <1W(110V) ,<2W(220V)
LED indicator for power status showed Yes
OSD for control & information supported Yes
Multi-language supported for OSD Yes
Buttons control supported Yes
Flywheel control supported No
Scaling function supported Yes
Auto adjustment function supported Yes
DDC function supported (EDID ver. 1.3) Yes
Audio speakers supported Yes
Audio Jack (input connector) supported Yes
Earphone Jack (input connector) supported Yes
Microphone function supported No
Mechanical Tilt base design Yes From -2 to +20 degree
VESA wall mounting design Yes
Mechanical Rotate design No N.A.
Mechanical Lift base design No N.A.
Kensington compatible lock design Yes
2. Operational Specification
2.1 Power supply
Item Condition Spec OK N.A Remark
Input Voltage range Universal input full range 90~264VAC /47~63Hz √
Input Current range 90 ~ 264VAC < 2.0 Arms √
Power Consumption Normal “On” operation < 40 W √
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FP71V+(Q7C4) LCD Monitor Service Guide
Engineering Specification
< 1 W in power preferred
DPMS DPMS “Off” state mode, 115V √
< 2 W, 230V
110 VAC < 30 A (peak)
Inrush Current
220 VAC < 60 A (peak)
√
Earth Leakage Current 264 VAC/50Hz < 3.5 mA √
1. 1500VAC, 1 sec Without damage
Hi-Pot
2. Ground test: 30A, 1sec < 0.1 ohm
√
Power Line Transient IEC1000-4-4 1KV √
Common: 2KV,
IEC1000-4-5 (Surge)
Differential: 1KV
√
CCFL operation range 90 ~ 264VAC 3 mA ~8mA √
CCFL Frequency 90 ~ 264VAC 40KHz ~ 80KHz √
Color: Black
Power cord √
Length: 1500 +/- 50 mm
6 10
11 15
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Engineering Specification
5 Cable Detected 13 H-Sync (or H+V)
6 Red Ground 14 V-sync
7 Green Ground 15 SCL
8 Blue Ground
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Engineering Specification
2.5 Plug & Play DDC2B Support
Item Condition Spec OK N.A Remark
DDC channel type DDC2B √
EDID Version 1.3 √
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Engineering Specification
3.4 Environment
Item Condition Spec OK N.A Remark
Operating 0 ~ +40 ℃ √
Temperature
Non-operating -20 ~ +60 ℃ √
Operating 10 ~ 90% √
Humidity
Non-operating 10 ~ 90% √
Operating 0~3048m (10,000ft) √
Altitude
Non-operating 0~12,192m (40,000ft) √
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Engineering Specification
3.5 Transportation
Item Condition Spec OK N.A Remark
(1) Sine wave
5~200Hz 1.5G, 1 octave/min,
15 min dwell on each resonant
frequency, all primary axis,
one sweep (30 min minimum)
per orientation, total of 90+
min.
(2) Random
5 ~100 Hz, 0 dB/Oct. 0.015
g2/Hz
100 ~200 Hz, -6 dB/Oct.
200 Hz, 0.0038 g2/Hz
(1) Vibration Package, Non-Operating √
Equivalent to 1.47 Grms, All
primary axis, 20 min per-
orientation, total is 60 min.
(3) Procedure:
Confirmed sample with
appearance and function ready
before testing then compare
with after test record as
brightness, uniformity and
contrast ratio. Perform
random vibration after
sine-wave vibration test.
Test Spectrum:
20 Hz 0.0185(g2/Hz)
200Hz 0.0185(g2/Hz)
(2) Unpackaged Vibration Unpackaged, Non-Operating Duration : 5 Minutes √
Axis : 3 axis ( Horizontal
and Vertical axis ,Z axis)
91 cm Height (MP stage)
(3) Drop Package, Non-Operating (1 corner, 3 edges, 6 faces) √
Waveform: half sine
Faces: 6 sides/ per orientation
Wooden package,
(4) Shock 3 shocks. √
Non-Operating Duration: <3ms
Velocity accelerate: 75g
8
Confidential
FP71V+(Q7C4) LCD Monitor Service Guide
Engineering Specification
3.8 Reliability
Item Condition Spec OK N.A Remark
MTBF Prediction Refer to MIL-217F > 60,000 Hours √
CCFL Life time At 25±2℃, under 7.0mA 50,000 Hours (typ.) √
Note-4: CCFL lifetime is determined as the time at which brightness of lamp is 50%. The typical lifetime of
CCFL is on the condition at 7.5mA lamp current.
4. LCD Characteristics
4.1 The Physical definition & Technology summary of LCD panel
Item Condition Spec OK N.A Remark
LCD Panel Supplier AUO √
Panel type of Supplier M170EG01 V3 √
Screen Diagonal 432mm(17.0”) √
Display area Unit=mm 337.920(H) x 270.336(V) √
Physical Size Unit=mm 358.5(H) x 296.5(V) x 17.0 (D) (typ.) √
Weight Unit=gram 1900 (typ.) √
Technology TN type √
Pixel pitch Unit=mm 0.264 x 0.264 √
Pixel arrangement R/G/B vertical stripe √
Display mode Normally white √
Support color 16.2M colors (RGB 6-bits + FRC data) √
9
Confidential
FP71V+(Q7C4) LCD Monitor Service Guide
Engineering Specification
[msec] Rising Time 6 9
Response Time [msec] Rising +Time
Falling Falling 82 13
4
Red x 0.61 0.64 0.67
Red y 0.31 0.34 0.37
Color / Chromaticity Green x 0.26 0.29 0.32
Coordinates (CIE) Green y 0.58 0.61 0.64
Blue x 0.11 0.14 0.17
Blue y 0.04 0.07 0.10
White x 0.28 0.31
Color Coordinates (CIE) White White y 0.30 0.33
Luminance Uniformity [%] 9 points measurement 75 80
White Luminance @ CCFL [cd/m2]
TBD 400
7.5mA (center)
Crosstalk (in 75Hz) [%] 1.5
* The test methods for the above items’ definition, please refer to the relative panel specification.
5. User Controls
5.1 User’s hardware control definition
Item Condition Spec OK N.A Remark
Monitor Power button √
Enter button √
Right/Inc. button √
Left/Dec. button √
Exit /Volume button √
I-key button √
Mode Selection button √
Mute button √
Input source select button √
5.2 OSD control function definition
Item Condition Spec OK N.A Remark
Auto Adjust Auto-Geometry √
Brightness √
Contrast √
Horizontal Position √
Vertical Position √
Pixel Clock √
Phase √
Bluish
Reddish
Color sRGB √
User: Separate R/G/B adjustment
OSD Horizontal position
OSD Position
OSD Vertical position
√
OSD Time From 5 sec to 60 sec √
Language 8 languages √
Color recall
Recall
Recall All
√
10
Confidential
FP71V+(Q7C4) LCD Monitor Service Guide
Engineering Specification
Mode Selection √
D-sub
Input Select
DVI
√
Sharpness √
Display Information For input timing √
Volume √
Mute √
Hot key for Brightness √
Hot key for Contrast √
Hot key for Volume √
Hot key for Mode √
* The detailed firmware functions’ specification, please refer to C212 S/W spec. document.
6. Mechanical Characteristics
6.1 Dimension
Item Condition Spec OK N.A Remark
Bezel opening 339.8 x 272.2 mm √
Monitor without Stand L x W x H mm 349.7*375.3*72mm √
Monitor with Stand L x W x H mm 385.8*375.3*201.1 mm √
Carton Box (outside) L x W x H mm 456 x 423 x 157mm √
Tilt: -2 ~ +20 degree
Tilt and Swivel range √
Swivel: 0 degrees
6.2 Weight
Item Condition Spec OK N.A Remark
Monitor (Net) 4.7 Kg √
Monitor with packing (Gross) 6.2 Kg √
6.3 Plastic
Item Condition Spec OK N.A Remark
Flammability 94-HB √
Heat deflection To ABS 65 ℃ √
UV stability ABS Delta E < 8.0 √
MPRII: ABS
Resin √
(VW55/VE0856/D350)
Bezel texture
Texture MT-11020 √ MT-11010
Bezel painting
Color BCS-Y5003A √ T8020C
11
Confidential
FP71V+(Q7C4) LCD Monitor Service Guide
Engineering Specification
6.4 Carton
Item Condition Spec OK N.A Remark
Color Kraft √
Material B Flute √
Compression strength 288 KGF √
Burst Strength 16 KGF/cm2 √
Stacked quantity 13 Layers √
7. Pallet & Shipment
7.1 Container Specification
Quantity of products Quantity of Products Quantity of pallet
Stowing Type Container (sets) (sets) (sets)
(Every container) (Every Pallet) (Every Container)
20' 780 Pallet A: 78 Pallet A: 6
With pallet Pallet B: 52 Pallet B: 6
40' 1820 Pallet A: 78 Pallet A: 14
Pallet B: 52 Pallet B: 14
20' 974 X X
X X
Without pallet
40' 2099 X X
X X
Package:
Carton Interior Dimension (mm) Carton External Dimension (mm)
L*W*H L*W*H
448 x 415 x 143 456 x 423 x 157
12
Confidential
FP71V+(Q7C4) LCD Monitor Service Guide
Engineering Specification
8. Certification
Item Condition Spec OK N.A Remark
Green design API Doc. 715-C49 √
Blue Angel German Standard √
E-2000 Switzerland √
Environment EPA USA Standard √
TCO’99 √
TCO’03 √
Green Mark √
Microsoft Windows PC98/99 √
DPMS VESA √
PC-Monitor
DDC 2B Version 1.3 √
USB External √
UL (USA) rd
UL60950 3 edition √
CSA (Canada) CAN/CSA-C22.2 No. 60950 √
Nordic / D.N.S.F EN60950 √
FIMKO EN60950 √
CE Mark 73/23/EEC √
IEC60950 √
Safety EN60950 √
CB EN60950 √
EN60950 /
TUV/GS √
EK1-ITB 2000:2003
CCC (China) √
GOST EN60950 √
SASO √
CE Mark 89/336/EEC √
FCC (USA) FCC Part 15 B √
EN55022 Class B √
EMC CISPR 22 Class B √
VCCI (Japan) VCCI Class B √
BSMI (Taiwan) CNS 13438 √
C-Tick (Australia) AS/ NZS CISPR22 √
X- Ray Requirement DHHS (21 CFR) USA X- Ray Standard √
DNHW √
13
Confidential
FP71V+(Q7C4) LCD Monitor Service Guide
Engineering Specification
PTB German X- Ray standard √
TUV / Ergo √
Ergonomics ISO 13406-2 √
prEN50279 √
14
Confidential
5 4 3 2 1
+3.3V
2
C1
DN1 D N2 DN3 D N4
C2 C3 C4
Note: C83, C103, C104, C144 is
3 3 3 3 ESD solution (for Gm5221)
0 .1U 0 .1U 0 .1U 0 .1U
BAV99 BAV99 BAV99 BAV99
1
+5V P C5V
D TP1 D
D N5 G ND G ND
2 1 P C5V
BAV70LT1 R1 R2 R3
2
75 75 75
D1
6.2V
J1
16
1
C5 6 TP2 R- R4 56 C6 0.01U K
0 .1U U1 R ED-
R5 R6 11 1
1 8 4.7K 4.7K G ND TP3 7 TP4 R+ L1 Z60 R7 20 C7 0.01U K
A0 VCC R ED+
12 2 68.60060.0T2
2 7 TP5 8 T1 G- R8 56 C8 0.01U K
A1 WP GREEN-
13 3
3 6 R9 SHORT(0) TP6 9
A2 SCL
14 4
4 5 R 10 SHORT(0) TP7 10 TP8 G+ L2 Z60 R 11 20 C9 0.01U K
GND SDA GREEN+
15 5 68.60060.0T2
Cable_Detect_A B- R 12 56 C 10 0.01U K +5V
AT24C02 BLUE-
2
D-Sub15 B+ L3 Z60 R 13 20 C 11 0.01U K
BLUE+
D2 D3 G ND 68.60060.0T2
CTRL_GND 6.2V 6.2V
C 12
#
"
!
0 .1U
17
G ND
14
14
G ND G ND
D SUB_SDA U 2A U 2B
R 14 100 1 2 3 4 R 15 100
D SUB_SCL VS
74LVC14A 74LVC14A
14
14
7
7
U 2C U 2D
R 16 100 5 6 9 8 R 17 100
HS
C C
2
74LVC14A 74LVC14A
D4 D5 C 13 C 14
7
6.2V R 18 6.2V R 19 47P 47P S03 version Add Add ,
10K 10K 50V J 50V J
R16~R17,R76~R81 for ESD
1
solution
G ND
G ND
+3.3V
G ND
G1
+5V D N6
2 1 DVIPC5V
G1
TP9
1 RX2-TP10 C 15 C 16 C 17 C 18 C 19 C 20 C 21 C 22 BAV70LT1
1
3
9 TP11 0 .1U 0 .1U 0 .1U 0 .1U 0 .1U 0 .1U 0 .1U 0 .1U
2
RX1-
9 RX0-TP12 D N7
17
17
2 TP13 RX2+ RX0- 3 BAV99
RX0M
2 RX1+TP14 G ND
10
10 DVIPC5V
2
18 RX0+
18 +3.3V DN8
3
3
1
B C 23 B
11 RX0+ 3 BAV99
11 RX0P 0 .1U
19 R 20 R 21
19 U3
2
4 4.7K 4.7K
J2 4 DN9
12 1 8
12 A0 VCC
1
20 RX1- 3 BAV99
20 RX1M
5 2 7
5 A1 WP
2
13
13 TP15 D N 10 R 22 SHORT(0) D VISCL
21 3 6 D VISCL
21 A2 SCL
1
22
22 TP18 D VISDA D N11 D N 12
7 AT24C02
7
1
8 BAV99
8 TP20 R 24 10K D N 13
16
16
1
25 D N14
C1
1
27 G ND R XC- 3 BAV99
C3 RXCM
29
C5 Cable_Detect_D
2
30
C5_ D N 15
26
C2
1
2
28 R XC+ 3 BAV99
C4 RXCP
D6 D7 D8
G2
0 .1U
1
G ND G ND G ND
G ND G ND
A A
F B1 80 OHM
F B2 80 OHM
3A
3A
1
C 30 C 25
+ C 26 C 27 C 28 C 29 C 31 C 32 C 33 C 34 C 35 OPEN(1U Z) C 36
22U 25V 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
2
GND
GND 1.8V_AVDD
1
+ C 37 C 38 + C 39 C 40 C 41 C 42 C 43 3A 3.3V_AVDD
190
205
116
121
126
137
164
166
139
179
22U 25V 0.1U 22U 25V 0.1U 0.1U 0.1U 0.1U C 44 C 45 U4
50
73
95
86
41
75
96
24
11
26
27
40
9
OPEN(1U Z) 0.1U
2
RVDD_3.3
RVDD_3.3
RVDD_3.3
RVDD_3.3
RVDD_3.3
VDD_RX2_1.8
VDD_RX1_1.8
VDD_RX0_1.8
VDD_RXPLL_1.8
VDD_ADC_1.8
VDD_RPLL_1.8
CVDD_1.8
CVDD_1.8
CVDD_1.8
CVDD_1.8
CVDD_1.8
CVDD_1.8
CVDD_1.8
AVDD_LV_E_3.3
AVDD_LV_E_3.3
AVDD_LV_3.3
AVDD_LV_O_3.3
AVDD_LV_O_3.3
GND
GND GND
10
RESERVED
113 13 TXE3+
C VD D_1.8 +3.3V 3.3V_LBAD AVDD_IMB_3.3 CH3P_LV_E
120 14 TXE3-
+1.8V 3.3V_PLL 3.3V_LBAD AVDD_RX2_3.3 CH3N_LV_E
125 15 TXEC+
AVDD_RX1_3.3 CLKP_LV_E
Close t o respect ive pow er Pins 130
AVDD_RX0_3.3 CLKN_LV_E
16 TXEC-
F B6 80 OHM F B7 80 OHM 134 17 TXE2+
AVDD_RXC_3.3 CH2P_LV_E
141 18 TXE2-
3A 3A AVDD_BLUE_3.3 CH2N_LV_E
1
171
AVDD_RPLL_3.3
29 TXO3+
GND CH3P_LV_O
115 30 TXO3-
AGND_IMB CH3N_LV_O
117 31 TXOC+
GND 3.3V_PLL AGND_RX2 CLKP_LV_O
122 32 TXOC-
G ND AGND_RX1 CLKN_LV_O
127 33 TXO2+
+3.3V 3.3V_DVDD AGND_RX0 CH2P_LV_O
131 34 TXO2-
AGND_RXC CH2N_LV_O
Close t o respect ive pow er Pins 136
GND_RXPLL CH1P_LV_O
35 TXO1+
F B8 80 OHM C 56 C 57 144 AGND 36
AGND_BLUE CH1N_LV_O TXO1-
R 25 OPEN(0) 149 37 TXO0+
3A X1 AGND_GREEN CH0P_LV_O
1
C C
XTAL 177 46
LBADC_GND RESERVED
G ND
GND 56
GND JTAG_RESET
57
TCLK RESERVED
170 58
+3.3V 3.3V_LVDS XTAL TCLK RESERVED
169 59
XTAL RESERVED
60
HOST_SCL RESERVED
71 61
F B9 80 OHM HOST_SDA HOST_SCL/UART_DI RESERVED
J3 72 62
R 26 SHORT(0) HOST_SDA/UART_DO RESERVED
D SUB_SCL 77 63
3A DDC_SCL_VGA RESERVED
1
D SUB_SDA R 27 SHORT(0) 78 64
C 64 C 65 C 66 C 67 C 68 C 69 3 HOST_SDA R 28 SHORT(0) DDC_SDA_VGA JTAG_TDO
+ D VISCL 79 65
22U 25V 0.1U 0.1U 0.1U 0.1U 0.1U 2 HOST_SCL R 29 SHORT(0) DDC_SCL_DVI RESERVED
D VISDA 80 66
1 DDC_SDA_DVI JTAG_TDI
2
1
When +3.3V pin over 2.8V, after 50ms, will output "H" 101
R MADDR17 GPIO14/PWM3 + C 70 + C 71
B
183
+3.3V R MADDR16
R MADDR15
184
185
ROM_ADDR17
ROM_ADDR16
ROM_ADDR15
GPIO15
69 VOLUME_SW 4.7U 25V 4.7U 25V
B
2
R MADDR14 186 167
R MADDR13 ROM_ADDR14 RESERVED R 35
187 135
+3.3V R 36 ROM_WEn R MADDR12 ROM_ADDR13 RESERVED 10K +3.3V
188 70
R MADDR11 ROM_ADDR12 RESERVED
U5 189
ROM_ADDR11
GND GND
+3.3V 10K R MADDR10 192 206
R MADDR9 ROM_ADDR10 CRVSS
31 193 191
U6 WE ROM_ADDR9 CRVSS
2
AVSS_LV_O
AVSS_LV_O
AVSS_LV_E
AVSS_LV_E
ROM_OEn ROM_WEn ROM_OEn LBADC_RETURN
24 32 6
AVSS_LV
ROM_CSn OE VCC C 74 ROM_CSn ROM_WEn
22 16 7
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
CE GND 0.1U ROM_CSn
VCLK
P M39 LV020-70JC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
R 66 (32-Pin PLCC Socket) G ND
AUDIO_MUTE R 67 10K L4
102
103
106
107
108
109
110
111
112
12
23
25
28
39
52
53
54
104
105
157
158
159
160
161
162
10K G ND
GM5221 AU D IO_SRS R 68 10K C 75 C105,
100P
50V J L12 for
+3.3V Cable_Detect_A
EMI
GND
C 76 0.1U C able_Detect_D G ND
A U7 Key_Mode GND A
R 69 R 70
72.39020.C33 vendor is PMC
1 8 O D_EN
A0 VCC 72.39020.033 vendor is SST
2 7 10K 10K AUDIO_MUTE
A1 WP
Project Code Model Name OEM/ODM Model Name
3
A2 SCL
6 S CL Socket p/n is 22.10025.032 AU D IO_SRS
99.L0Y72.001 Q 7C4 <OEM/ODM>
4 5 S DA
GND SDA Title
IN T ERFACE BOARD
AT24C16N-10SI-1.8
NV RAM Size PC B P/N PC B R ev. D ocument Number R e v.
GND GND
<Size> 1
48.L0Y01.S12 S12 99.L0Y72.000-C3-304-006
5 4 3 2 1
5 4 3 2 1
14
U2E
D 11 10 L5 0 R71 330 D
LED_GREEN
74LVC14A
14 7
U 2F
13 12 L6 0 R72 330
LED_AMBER
74LVC14A +3.3V
7
J4
TP23 1
L7 600 OHM R73 1K TP24 2 KEY_LEFT R74 10K
KEY_PW _SW
L8 600 OHM R75 1K TP25 3 KEY_MENU R76 10K
KEY_RIGHT
L9 600 OHM R77 1K TP26 4 KEY_EXIT R78 10K R81
KEY_LEFT
L10 600 OHM R79 1K TP27 5 KEY_AUTO R80 10K 0
KEY_MENU
L11 600 OHM R82 1K TP28 6 KEY_PW _SW R83 10K
KEY_EXIT
L12 600 OHM R84 1K TP29 7 KEY_RIGHT R85 10K
KEY_AUTO
L13 600 OHM R86 1K TP30 8
KEY_Mode
9 CTRL_GND G ND
10
C77 C78 C79 C80 C81 C82 C83 2060091110
100P 100P 100P 100P 100P 100P 100P C84 C85
50V J 50V J 50V J 50V J 50V J 50V J 50V J 100P 100P
50V J 50V J
C C
CTRL_GND
'
$
%&
TP31 J5
BL_ON 2 1 TP32 BRT_ADJ
4 3 TP33 POW ER_PS R87 0 PS
6 5
8 7 TP34 L14 80 OHM +5V
10 9 TP35 3A L15 80 OHM +3.3V
VOLUME_SW 12 11 TP36 3A VOLUME_ADJ
AUDIO_MUTE 14 13 AUDIO_SRS
2072060207
C92
C86 C87 C88 C89 C90 C91 OPEN(100P) C93 C94 C95 C96
OPEN(100P) 100P 100P
B 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 50V J 0.1U 50V J 50V J 50V J B
1
+ C98 + C99
22U 25V 22U 25V
2
G ND
G ND G ND
+3.3V +1.8V
U8
G952T63U
3 VIN VOUT1 2
1
4
GND
A G ND G ND G ND A
Project Code Model Name OEM/ODM Model Name
G ND
99.L0Y72.001 Q7C4 <OEM/ODM>
Title
INTERFACE BOARD
D D
U9 spec.
Vds=-30V, Vgs=+/-12V
Id=-3.5A when ambient temp.=70 degre
G(1)
D(3)
S(2)
+5V
LCD_5V_POW ER
C R88 LCD_5V_POWER supply: C
100K
1.samsung L02 panel max. 1.05A
1
U9 + C104 C105
2.OD max. ?A
1 ELM13401CA 22U 25V 0.1U 3.samsung 1Mx4 SDRAM max. 1.212A
4. 5v convert to 3.3v regulator ?A
2
---------------------------------------------------
2
3 Total: A
R89 20K 1 Q1
LCD_ON_OFF
2N3904
+5V
2
1
G ND
+ C106 R90
4.7U 25V 10K
2
G ND C107
0.1U
G ND
G ND
B B
Optical Points
1
5 9 5 9 5 9 5 9
4 8 4 8 4 8 4 8
3 7 3 7 3 7 3 7
Fiducial_Mark Fiducial_Mark Fiducial_Mark Fiducial_Mark Fiducial_Mark Fiducial_Mark Fiducial_Mark
A 2 6 2 6 2 6 2 6 A
Project Code Model Name OEM/ODM Model Name
H3 H4 H2 H1 99.L0Y72.001 Q7C4 <OEM/ODM>
Fiducial_Mark Fiducial_Mark Fiducial_Mark Fiducial_Mark Fiducial_Mark Fiducial_Mark Fiducial_Mark Title
HOLE-V8 HOLE-V8 HOLE-V8 HOLE-V8 INTERFACE BOARD
J6
20D2013130
G2
G1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
You can replace it to LD1117-3.3V
G2
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
G1
p/n: 74.01117.03C
TP37
TP38
TP39
TP40
TP41
TP42
TP43
TP44
TP45
TP46
TP47
TP48
TP49
TP50
TP51
TP52
TP53
TP54
TP55
TP56
TP57
TP58
GND GND
R91
R92
Warning: This regulator is 1A
You MUST measure output current when ICs working
TXO0C+
TXE0C+
TXO00+
TXO01+
TXO02+
TXO03+
TXE00+
TXE01+
TXE02+
TXE03+
TXO0C-
TXE0C-
TXO00-
TXO01-
TXO02-
TXO03-
TXE00-
TXE01-
TXE02-
TXE03-
0
D D
3.3V
LCD_5V_POW ER
U 10 G ND
G960T63 GND
3 2
VIN VOUT
Current estimation: Real measurment:
GND
1
OUT
4
Samsung SDRAM 1Mx16 4 SDRAM current= 2x 0.058=0.116A Note: R29, R30 for EG01 panel
+ C108
C 109 22U 25V power consuption:1W VTI03601 current= 0.192+0.136=0.328A
1
0.1U
1W/3.3V=0.303A ------------------------------------------------------------------
2
TP59
0.303*4=1.212A total: 0.444A LCD_5V_POW ER
O D_3.3V
VTI03601 power consuption: unknown
----------------------------------------------------------
G ND
total: 1.212A at least
O_SD2_R7
O_SD2_R6
O_SD2_R5
O_SD2_R4
O_SD2_R3
O_SD2_G7
LVDS_3.3V
3.3V O D_3.3V
L17 80 OHM
1
3A
C111 C 112 C 113 C114 C 115 C 116 C 117 C118 C 119
TXO0C+
TXE0C+
+ C 110
TXO00+
TXO01+
TXO02+
TXO03+
TXE00+
TXE01+
TXE02+
TXE03+
TXO0C-
TXE0C-
TXO00-
TXO01-
TXO02-
TXO03-
TXE00-
TXE01-
TXE02-
TXE03-
22U 25V 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
2
GND
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
LVDS Input
L2=0.136A 0621'04 measure
TXO0-
TXO1-
TXO2-
TXOC-
TXO3-
TXE0-
TXE1-
TXE2-
TXEC-
TXE3-
ODD_SD2_R7
ODD_SD2_R6
ODD_SD2_R5
ODD_SD2_R4
ODD_SD2_R3
ODD_SD2_G7
TXO0+
TXO1+
TXO2+
TXOC+
TXO3+
TXE0+
TXE1+
TXE2+
TXEC+
TXE3+
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
LVDS_GND
LVDS_VCC
RESERVED
LVDS_VCC
LVDS_GND
LVDS_GND
LVDS_VCC
LVDS_GND
LVDS_GND
LVDS_VCC
LVDS_GND
LVDS_VCC
LVDS_GND
LVDS_GND
LVDS_VCC
LVDS_GND
LVDS_GND
LVDS_VCC
LVDS_GND
GND
VCC
3.3V LVDS_3.3V
L18 80 OHM
1
3A 1 156
+ C 120 C 121 C122 C 123 C124 C 125 LVDS_VCC VCC
C 2 155 C
22U 25V 0.1U 0.1U 0.1U 0.1U 0.1U LVDS_VCC GND
3 154 O_SD2_G6
RXO0- LVDS_VCC ODD_SD2_G6
TXO0- 4 Transmitter_ODD Transmitter_EVEN O_SD2_BR 153 O_SD2_G5
RXO0- ODD_SD2_G5
2
Receiver_ODD
TXO1- 6 151 O_SD2_G3
RXO1+ RXO1- ODD_SD2_G3
TXO1+ 7 150 O_SD2_B7
GND RXO2- RXO1+ ODD_SD2_B7
TXO2- 8 149 O_SD2_B6
RXO2+ RXO2- ODD_SD2_B6
9 148
O_SD2_B
TXO2+ RXO2+ ODD_SD2_B5 O_SD2_B5
TXOC- RXOC- 10 147 O_SD2_B4
RXOC+ RXOC- ODD_SD2_B4
TXOC+ 11 146 O_SD2_B3
RXO3- RXOC+ ODD_SD2_B3
TXO3- 12 145 E_SD2_R7
RXO3+ RXO3- EVEN_SD2_R7
TXO3+ 13 144
RXO3+ RESERVED
14 143
LVDS_GND VCC
15 142
E_SD2_R
R 94 R 95 R 96 R 97 R 98 LVDS_GND GND
16 141 E_SD2_R6
100 100 100 100 100 LVDS_GND EVEN_SD2_R6
17 140 E_SD2_R5
LVDS_GND EVEN_SD2_R5
18 139 E_SD2_R4
3.3V LVDS_VCC U3 EVEN_SD2_R4
19 138 E_SD2_R3
LVDS_VCC EVEN_SD2_R3
20 137 E_SD2_G7
RXE0- LVDS_VCC EVEN_SD2_G7
TXE0- 21 136 E_SD2_G6
RXE0+ RXE0- EVEN_SD2_G6
TXE0+ 22 135 E_SD2_G5
RXE1- RXE0+ EVEN_SD2_G5
Receiver_EVEN
TXE1- 23 134 E_SD2_G4
RXE1+ RXE1- EVEN_SD2_G4
24 133
VTIO3601
E_SD2_G
TXE1+ RXE1+ RESERVED
R 99 TXE2- RXE2- 25 132
OPEN(4.7K) RXE2+ RXE2- VCC
U 12 TXE2+ 26 131
RXEC- RXE2+ GND
TXEC- 27 130 E_SD2_G3
RXEC+ RXEC- EVEN_SD2_G3
TXEC+ 28 129 E_SD2_B7
SPI_CS RXE3- RXEC+ EVEN_SD2_B7
1 8 TXE3- 29 128 E_SD2_B6
CS VCC RXE3+ RXE3- EVEN_SD2_B6
30 127
E_SD2_B
TXE3+ RXE3+ EVEN_SD2_B5 E_SD2_B5
SPI_SO 2 7 31 126 E_SD2_B4
SO HOLD LVDS_GND EVEN_SD2_B4
32 125 E_SD2_B3
SPI_I2C_WP SPI_I2C_SCK R 100R 101R102R103R 104 LVDS_GND EVEN_SD2_B3
3 6 33 124 SD2_WE
WP SCK 100 100 100 100 100 LVDS_GND SDRAM_2_WE
34 123
SPI_I2C_SI LVDS_GND RESERVED
4 5 35 122
GND SI RESERVED VCC
36 121
GND RESERVED GND
37 120
3.3V SEL_ROM_1 RESERVED
38 119 SD_A3
AT25F512N-10SI-2.7 RESET SEL_ROM_2 SDRAM_A3
Config
39 118 SD_A2
R 105 OPEN(4.7K) TAB_SEL_1 NRST SDRAM_A2
40 117 SD_A4
R 106 OPEN(4.7K) TAB_SEL_2 TAB_SEL_1 SDRAM_A4
41 116 SD_A1
OPEN(4.7K) N TSC_PAL TAB_SEL_2 SDRAM_A1
SPI EEPROM R 107 42
NTSC_PAL SDRAM_A5
115 SD_A5
B R 108 4.7K OD_EN 43 114 SD_A0
B
SPI_I2C_SCK 44 OD_EN SDRAM_A0
113 SD_A6
SPI_I2C_SI 45 SPI_CLK SDRAM_A6
O D_EN 112 SD_A10
SPI_CS SPI_SI SDRAM_A10
SPI
46 111 SD_A7
GND SPI_SO SPI_CS SDRAM_A7
47 110
SPI_SO SDRAM_BA1
48 109 SD_A8
PAD_TEST E_SD1_B E_SD1_G E_SD1_R O_SD1_B O_SD1_G O_SD1_R SDRAM_A8
49 108 SD_BA0
PAD_TCLK SDRAM_BA0
50 107 SD_A9
RESERVED SDRAM_A9
51 106
SDRAM_DQM_0
SDRAM_DQM_1
VCC VCC
LOW RESET
EVEN_SD1_G3
EVEN_SD1_G4
EVEN_SD1_G5
EVEN_SD1_G6
EVEN_SD1_G7
EVEN_SD1_R3
EVEN_SD1_R4
EVEN_SD1_R5
EVEN_SD1_R6
EVEN_SD1_R7
EVEN_SD1_B3
EVEN_SD1_B4
EVEN_SD1_B5
EVEN_SD1_B6
EVEN_SD1_B7
SDRAM_1_WE
52 105
ODD_SD1_G3
ODD_SD1_G4
ODD_SD1_G5
ODD_SD1_G6
ODD_SD1_G7
ODD_SD1_R3
ODD_SD1_R4
ODD_SD1_R5
ODD_SD1_R6
ODD_SD1_R7
ODD_SD1_B3
ODD_SD1_B4
ODD_SD1_B5
ODD_SD1_B6
ODD_SD1_B7
GND GND
SDRAM_CAS
SDRAM_RAS
SDRAM_CLK
Pin38, 37 are ROM type selection --- internal pull low
SDRAM_CS
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Pin42,41,40 are OD table selection (have 8 choice) --- internal pull low
3.3V
Pin43 (OD_EN) --- internal pull low
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
2
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
D 10
R109 1N4148
10K
1
RESET
C 126
1U Z
E_SD1_B3
E_SD1_B4
E_SD1_B5
E_SD1_B6
E_SD1_B7
E_SD1_G3
E_SD1_G4
E_SD1_G5
E_SD1_G6
E_SD1_G7
E_SD1_R3
E_SD1_R4
E_SD1_R5
E_SD1_R6
E_SD1_R7
O_SD1_B3
O_SD1_B4
O_SD1_B5
O_SD1_B6
O_SD1_B7
O_SD1_G3
O_SD1_G4
O_SD1_G5
O_SD1_G6
O_SD1_G7
O_SD1_R3
O_SD1_R4
O_SD1_R5
O_SD1_R6
O_SD1_R7
SD_DQM0
SD_DQM1
SD1_WE
SD_CAS
SD_RAS
SD_CLK
SD_CS
GND
GND
A A
SDRAM2_3.3V
L3=0.058A 0621'04
3.3V measure SDRAM1_3.3V
L19 80 OHM
SDRAM_CLOCK
1
3A
C128 C129 C130 C131 C132 C133 C134 C135 C136 C137 C138 C139 C140 C141
D_O_SD2_G6
D_O_SD2_G7
D_O_SD2_R3
D_O_SD2_R4
D_O_SD2_R5
D_O_SD2_R6
D_O_SD2_R7
+ C127
22U 25V 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
SD_DQM1
D R N1 0 D
SD_A9
SD_A8
SD_A7
SD_A6
SD_A5
SD_A4
O_SD2_R7 1 8 D_O_SD2_R7
O_SD2_R6 2 7 D_O_SD2_R6
G ND O_SD2_R5 3 6 D_O_SD2_R5
4 5
R N2 0
3.3V L4=0.058A 0621'04 measure SDRAM2_3.3V 1 8 D_O_SD2_R4
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
O_SD2_R4
O_SD2_R3 2 7 D_O_SD2_R3
O_SD2_G7 3 6 D_O_SD2_G7
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
A9
A8
A7
A6
A5
A4
UDQM
VSSQ
VDDQ
VSSQ
VDDQ
NC/RFU
NC
VSS
CLK
CKE
VSS
L20 80 OHM O_SD2_G6 4 5 D_O_SD2_G6
1
3A
+ C142 C143 C144 C145 C146 C147 C148 C149 C150 C151 C152 C153 C154 C155 C156
22U 25V 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U K4S161622E-TC70 U13
R N3 0
A10/AP
2
VDDQ
VDDQ
LDQM
D_O_SD2_G5
VSSQ
VSSQ
O_SD2_G5 1 8
VDD
VDD
CAS
RAS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D_O_SD2_G4
WE
2 7
CS
BA
A0
A1
A2
A3
O_SD2_G4
O_SD2_G3 3 6 D_O_SD2_G3
G ND O_SD2_B7 4 5 D_O_SD2_B7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
R N4 0
D_O_SD2_B6
D_O_SD2_G5
D_O_SD2_G4
1 8
SD_DQM1
O_SD2_B6
SD2_WE
D_O_SD2_B5
D_O_SD2_G3
D_O_SD2_B7
D_O_SD2_B6
D_O_SD2_B5
D_O_SD2_B4
D_O_SD2_B3
SD_CAS
SD_RAS
2 7
SD_BA0
SD_A10
O_SD2_B5
SD_CS
SD_A0
SD_A1
SD_A2
SD_A3
O_SD2_B4 3 6 D_O_SD2_B4
O_SD2_B3 4 5 D_O_SD2_B3 G ND
E_SD1_B3
E_SD1_B4
E_SD1_B5
E_SD1_B6
E_SD1_B7
E_SD1_G3
E_SD1_G4
E_SD1_G5
E_SD1_G6
E_SD1_G7
E_SD1_R3
E_SD1_R4
E_SD1_R5
E_SD1_R6
E_SD1_R7
O_SD1_B3
O_SD1_B4
O_SD1_B5
O_SD1_B6
O_SD1_B7
O_SD1_G3
O_SD1_G4
O_SD1_G5
O_SD1_G6
O_SD1_G7
O_SD1_R3
O_SD1_R4
O_SD1_R5
O_SD1_R6
O_SD1_R7
C C
R N5 0
E_SD2_R7 1 8 D_E_SD2_R7 SDRAM2_3.3V
E_SD2_R6 2 7 D_E_SD2_R6
E_SD2_R5 3 6 D_E_SD2_R5
4 5
SDRAM_CLOCK
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
R N6 R N7 R N8 R N9 RN10 RN11 RN12 RN13 RN14 0
D_E_SD2_R3
D_E_SD2_R4
D_E_SD2_R5
D_E_SD2_R6
D_E_SD2_R7
D_E_SD2_G6
D_E_SD2_G7
0 0 0 0 0 0 0 0 1 8 D_E_SD2_R4
SD_DQM1
E_SD2_R4
E_SD2_R3 2 7 D_E_SD2_R3
SD_A9
SD_A8
SD_A7
SD_A6
SD_A5
SD_A4
E_SD2_G7 3 6 D_E_SD2_G7
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
E_SD2_G6 4 5 D_E_SD2_G6
D_O_SD1_B3
D_O_SD1_B4
D_O_SD1_B5
D_O_SD1_B6
D_O_SD1_B7
D_O_SD1_G3
D_O_SD1_G4
D_O_SD1_G5
D_O_SD1_G6
D_O_SD1_G7
D_O_SD1_R3
D_O_SD1_R4
D_O_SD1_R5
D_O_SD1_R6
D_O_SD1_R7
D_E_SD1_B3
D_E_SD1_B4
D_E_SD1_B5
D_E_SD1_B6
D_E_SD1_B7
D_E_SD1_R3
D_E_SD1_R4
D_E_SD1_R5
D_E_SD1_R6
D_E_SD1_R7
D_E_SD1_G3
D_E_SD1_G4
D_E_SD1_G5
D_E_SD1_G6
D_E_SD1_G7
RN15 0
1 8 D_E_SD2_G5
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
E_SD2_G5
E_SD2_G4 2 7 D_E_SD2_G4
E_SD2_G3 3 6 D_E_SD2_G3
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
A9
A8
A7
A6
A5
A4
UDQM
VSSQ
VDDQ
VSSQ
VDDQ
NC/RFU
NC
VSS
CLK
CKE
VSS
E_SD2_B7 4 5 D_E_SD2_B7
A10/AP
VDDQ
VDDQ
LDQM
D_E_SD2_B5
VSSQ
VSSQ
E_SD2_B5 2 7
VDD
VDD
CAS
RAS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
B D_E_SD2_B4 B
WE
3 6
CS
BA
A0
A1
A2
A3
E_SD2_B4
E_SD2_B3 4 5 D_E_SD2_B3
SDRAM1_3.3V SDRAM1_3.3V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
K4S161622E-TC70 K4S161622E-TC70
SD_DQM1
SD2_WE
SD_CAS
SD_RAS
D_E_SD2_B7
D_E_SD2_B6
D_E_SD2_B5
D_E_SD2_B4
D_E_SD2_B3
D_E_SD2_G5
D_E_SD2_G4
D_E_SD2_G3
SD_BA0
SD_A10
SD_CS
SD_A0
SD_A1
SD_A2
SD_A3
1 VDD VSS 50 1 VDD VSS 50
D_E_SD1_B3 2 49 D_O_SD1_B3 2 49 G ND
D_E_SD1_B4 DQ0 DQ15 D_E_SD1_R7 D_O_SD1_B4 DQ0 DQ15 D_O_SD1_R7
3 DQ1 DQ14 48 3 DQ1 DQ14 48
4 VSSQ VSSQ 47 4 VSSQ VSSQ 47
D_E_SD1_B5 5 46 D_E_SD1_R6 D_O_SD1_B5 5 46 D_O_SD1_R6 If bead array is too small (now is 0805),
D_E_SD1_B6 DQ2 DQ13 D_E_SD1_R5 D_O_SD1_B6 DQ2 DQ13 D_O_SD1_R5
6 DQ3 DQ12 45 6 DQ3 DQ12 45 you can change to 1206 (use p/n:68.12160.AQ1)
7 VDDQ VDDQ 44 7 VDDQ VDDQ 44
D_E_SD1_B7 8 43 D_E_SD1_R4 D_O_SD1_B7 8 43 D_O_SD1_R4
D_E_SD1_G3 DQ4 DQ11 D_E_SD1_R3 D_O_SD1_G3 DQ4 DQ11 D_O_SD1_R3
9 DQ5 DQ10 42 9 DQ5 DQ10 42
10 VSSQ VSSQ 41 10 VSSQ VSSQ 41
D_E_SD1_G4 11 40 D_E_SD1_G7 D_O_SD1_G4 11 40 D_O_SD1_G7
D_E_SD1_G5 DQ6 DQ9 D_E_SD1_G6 D_O_SD1_G5 DQ6 DQ9 D_O_SD1_G6
12 DQ7 DQ8 39 12 DQ7 DQ8 39
13 VDDQ VDDQ 38 13 VDDQ VDDQ 38
SD_DQM0 14 37 SD_DQM0 14 37
SD1_WE LDQM NC/RFU SD_DQM0 SD1_WE LDQM NC/RFU SD_DQM0 R110 0
15 WE UDQM 36 15 WE UDQM 36
SD_CAS 16 35 SDRAM_CLOCK SD_CAS 16 35 SDRAM_CLOCK SD_CLK SDRAM_CLOCK
SD_RAS CAS CLK SD_RAS CAS CLK
17 RAS CKE 34 17 RAS CKE 34
SD_CS 18 33 SD_CS 18 33
SD_BA0 CS NC SD_A9 SD_BA0 CS NC SD_A9
19 BA A9 32 19 BA A9 32 SD2_W E
SD_A10 20 31 SD_A8 SD_A10 20 31 SD_A8
SD_A0 A10/AP A8 SD_A7 SD_A0 A10/AP A8 SD_A7
A 21 A0 A7 30 21 A0 A7 30 SD_A3 SD_CS A
SD_A1 22 29 SD_A6 SD_A1 22 29 SD_A6 SD_A2 Project Code Model Name OEM/ODM Model Name
SD_A2 A1 A6 SD_A5 SD_A2 A1 A6 SD_A5
23 A2 A5 28 23 A2 A5 28 SD_A4 SD_RAS 99.L0Y72.001 Q7C4 <OEM/ODM>
SD_A3 24 27 SD_A4 SD_A3 24 27 SD_A4 SD_A1 SD_CAS
A3 A4 A3 A4
25 VDD VSS 26 25 VDD VSS 26 SD_A5 SD_DQM1 Title
INTERFACE BOARD
SD_A0
SD_A6 SD1_W E
U15 U16 Size PCB P/N P C B R ev. Document Number R e v.
SD_A10 SD_DQM0
SD_A7 <Size> 1
48.L0Y01.S12 S12 99.L0Y72.000-C3-304-006
SD_A8
D ate: Friday, November 19, 2004 Sheet 6 of 6
SD_BA0
G ND G ND Prepared By R eviewed By A pproved By
SD_A9
ANGEL HU LINIX CHENG DAVEN W U
5 4 3 2 1