) Write a verilog code to swap contents of two registers with and without a temporary register?

Difference between blocking and non-blocking?

Tell me about verilog file I/O?

OPEN A FILE

integer file;
file = $fopenr("filename");
file = $fopenw("filename");
file = $fopena("filename");
The function $fopenr opens an existing file for reading. $fopenw opens a new file for writing, and
$fopena opens a new file for writing where any data will be appended to the end of the file. The file
name can be either a quoted string or a reg holding the file name. If the file was successfully opened, it
returns an integer containing the file number (1..MAX_FILES) or NULL (0) if there was an error. Note that
these functions are not the same as the built-in system function $fopen which opens a file for writing by
$fdisplay. The files are opened in C with 'rb', 'wb', and 'ab' which allows reading and writing binary data
on the PC. The 'b' is ignored on Unix.

CLOSE A FILE

integer file, r;
r = $fcloser(file);
r = $fclosew(file);

The function $fcloser closes a file for input. $fclosew closes a file for output. It returns EOF if there was
an error, otherwise 0. Note that these are not the same as $fclose which closes files for writing.

Difference between task and function?

Difference between inter statement and intra statement delay?

What is delta simulation time?

Difference between $monitor,$display & $strobe?

What is difference between Verilog full case and parallel case?

What is meant by inferring latches,how to avoid it?

Tell me how blocking and non blocking statements get executed?

Variable and signal which will be Updated first?

What is sensitivity list?

In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk?

Tell me structure of Verilog code you follow?

What are different styles of Verilog coding I mean gate-level,continuous level and others explain in
detail?

Can you tell me some of system tasks and their purpose?

Can you list out some of enhancements in Verilog 2001?

Write a Verilog code for synchronous and asynchronous reset?

What is pli?why is it used?

There is a triangle and on it there are 3 ants one on each corner and are free to move along sides of
triangle what is probability that they will collide?

)What is difference between freeze deposit and force?

Will case infer priority register if yes how give an example?

Casex,z difference,which is preferable,why?

Given the following Verilog code, what value of "a" is displayed?

What is the difference between the following two lines of Verilog code?

hat is the difference between:

c = foo ? a : b;
and
if (foo) c = a;
else c = b;

What are Intertial and Transport Delays ??

What does `timescale 1 ns/ 1 ps signify in a verilog code?

What is the difference between === and == ?

How to generate sine wav using verilog coding style?

What is the difference between wire and reg?

How do you implement the bi-directional ports in Verilog HDL?

what is verilog case (1) ?

Why is it that "if (2'b01 & 2'b10)..." doesn't run the true case?
What are Different types of Verilog Simulators ?

What is Constrained-Random Verification ?

 What is the difference between $display and $monitor and $write and $strobe?
 What is the difference between code-compiled simulator and normal simulator?
 What is the difference between wire and reg?
 What is the difference between blocking and non-blocking assignments?
 What is the significance Timescale directivbe?
 What is the difference between bit wise, unary and logical operators?
 What is the difference between task and function?
 What is the difference between casex, casez and case statements?
 Which one preferred-casex or casez?
 For what is defparam used?
 What is the difference between “= =” and “= = =” ?
 What is a compiler directive like ‘include’ and ‘ifdef’?
 Write a verilog code to swap contents of two registers with and without a temporary
register?
 What is the difference between inter statement and intra statement delay?
 What is delta simulation time?
 What is difference between Verilog full case and parallel case?
 What you mean by inferring latches?
 How to avoid latches in your design?
 Why latches are not preferred in synthesized design?
 How blocking and non blocking statements get executed?
 Which will be updated first: is it variable or signal?
 What is sensitivity list?
 If you miss sensitivity list what happens?
 In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk?
If yes, why? If not, why?
 In a pure sequential circuit is it necessary to mention all the inputs in sensitivity disk? If
yes, why? If not, why?
 What is general structure of Verilog code you follow?
 What are the difference between Verilog and VHDL?
 What are system tasks?
 List some of system tasks and what are their purposes?
 What are the enhancements in Verilog 2001?
 Write a Verilog code for synchronous and asynchronous reset?
 What is pli? why is it used?
 What is file I/O?
 What is difference between freeze deposit and force?
 Will case always infer priority register? If yes how? Give an example.
 What are inertial and transport delays ?
 What does `timescale 1 ns/ 1 ps’ signify in a verilog code?
 How to generate sine wav using verilog coding style?
 How do you implement the bi-directional ports in Verilog HDL?
 How to write FSM is verilog?
  What is verilog case (1)?
 What are Different types of Verilog simulators available?
 What is Constrained-Random Verification ?
 How can you model a SRAM at RTL Level?

What do we mean by continuous assignment ?

What is meant by inferring latches and how to avoid it?

Inferring latch means to reproduce last value when unknown branch is specified. For example, to
avoid latches make sure that all cases are mentioned in case statements if not case default is
mentioned. In the same way latch is inferred in IF statement if ELSE IF is not specified.
always @(s1 or s0 or i0 or i1 or i2 or i3)
case ({s1,s0})
2'b00 : out = i0;
2'b01 : out = i1;
2'b10 : out = i2;
endcase

What is the difference between $setup and $hold?

$setup and $hold is used to monitor setup and hold time constraints for sequential logic. Setup
time is the minimum time the data must arrive before active edge of clock signal and hold time
is the minimum time the data cannot change after active edge of clock signal. They are specified
under specify block.

Draw following diagram to explain.

These are the types of case statement in which casex represent x and z as don't care while casez
represent z as don't care. Don't cares are not allowed in case statement so casex and casez are used.

10. What is repeat loop in Verilog?

Repeat loop is used to execute loop fixed number of times. It is not used to loop expression like we see
in while loop statement. It contains constant, variable or signal . For example repeat(8)

Variable And Signal Which Will Be Updated First?

What Is Sensitivity List?

Answer :

The sensitivity list indicates that when a change occurs to any one of elements in the list change,
begin…end statement inside that always block will get executed.

In A Pure Combinational Circuit Is It Necessary To Mention All The Inputs In Sensitivity

Answer :

Yes in a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk
other wise it will result in pre and post synthesis mismatch.

Write A Verilog Code For Synchronous And Asynchronous Reset?

here Is A Triangle And On It There Are 3 Ants One On Each Corner And Are Free To Move Along Sides
Of Triangle What Is Probability That They Will Collide?

Will Case Infer Priority Register If Yes How Give An Example?

Answer :

yes case can infer priority register depending on coding style

Given The Following Verilog Code, What Value Of "a" Is Displayed?

Answer :

always @(clk) begin

This is a tricky one! Verilog scheduling semantics basically imply a four-level deep queue for
the current simulation time:

1. Active Events (blocking statements)

Since the "a = 0" is an active event, it is scheduled into the 1st "queue".

The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue.

Finally, the display statement is placed into the 4th queue. Only events in the active queue are
completed this sim cycle, so the "a = 0" happens, and then the display shows a = 0. If we were to
look at the value of a in the next sim cycle, it would show 1.
What Does `timescale 1 Ns/ 1 Ps Signify In A Verilog Code?

Answer :

'timescale directive is a compiler directive.It is used to measure simulation time or delay time.
Usage :`timescale / reference_time_unit : Specifies the unit of measurement for times and delays.
time_precision: specifies the precision to which the delays are rounded off.