Bilayer CVD Graphene Fets
Bilayer CVD Graphene Fets
Bilayer CVD Graphene Fets
Abstract — In this letter, we report on inverters made is yet to be optimized due to technological limitations
from graphene field effect transistors with channels of arti- encountered in its growth using chemical vapor deposi-
ficially stacked bilayer graphene (ASBLG). The materials tion (CVD) [13].
were grown by scalable chemical vapor deposition. The
devices demonstrate enhanced voltage gain (Av ) figures at Even though there have been several reports of large
relatively lower input voltages when compared with devices area growth of Bernal stacked bilayer graphene [14]–[16],
with single layer graphene channels. A gain value as high the device performance obtained from such grown material
as 7.134 is obtained using ASBLG-based inverters without was found to be largely varying [15]. Recently, we have
any applied back-gate voltage. The improved performance reported improved voltage gain in FETs made with channels
is discussed in terms of transconductance and contact
resistance. Our results suggest that ASBLG-based inverters of artificially stacked bilayer graphene (ASBLG), which we
may be useful for future RF circuit applications. attributed to enhanced carrier-carrier scattering under certain
Index Terms — Artificially stacked bilayer graphene, biasing conditions [17]. In this letter, we demonstrate and
chemical vapor deposited graphene, inverters, voltage gain. discuss inverters made from ASBLG fabricated by stacking
two single layers of graphene (SLG), grown in-house using a
I. I NTRODUCTION thermal CVD method [18]. We demonstrate improved voltage
gain at zero back gate voltage conditions in these inverters
A N INVERTER is a complementary NOT gate, typically
consisting of a co-joined pair of p-doped and n-doped
field effect transistors (FET). It is the most fundamental circuit
compared to those based on SLG channels at ambient condi-
tions. Our results suggest possible radio frequency (RF) circuit
building block and it demonstrates the capability of any FET applications of ASBLG inverters.
technology for signal inversion and thus, circuit applications.
Single layer graphene has zero band gap which results in II. D EVICE FABRICATION
poorly saturating output characteristics of graphene field effect
We fabricated graphene based inverters on thermally
transistors (GFETs), and in turn poor intrinsic voltage gain
oxidized Si substrates using optical lithography with gate
values in both transistor [1], [2] and inverter configurations [3].
lengths (Lg ) between 3 and 12 μm. Channel widths (W) in
Improvements have been achieved by enhancing gate control
different cases were 10 μm to 60 μm (in steps of 10 μm). Two
through thin top gate dielectrics [4]–[7]. Alternatively, Bernal
sets of devices were simultaneously prepared, each consisting
stacked bilayer graphene with electrically tunable band gaps
of a co-fabricated pair of SLG & ASBLG CVD graphene
of the order of a few hundred meV have been proposed
devices. For the first set, electron-beam evaporated silicon
and successfully demonstrated to improve current saturation,
dioxide (SiO2 ) and for the second set, ambient oxidized
intrinsic transistor voltage gain and inverter gain [8]–[12].
aluminum (i.e. AlOx , tox ∼ 4 to 8 nm) were used as gate
However, the scalable production of Bernal stacked bilayer
dielectrics [5], [12]. Contact metal in all devices was 100 nm
Manuscript received September 30, 2017; revised October 18, 2017; thick e-beam evaporated gold (Au). Device fabrication details
accepted October 18, 2017. Date of current version November 22, can be found in [17].
2017. This work was supported in part by the German Research
Foundation under Grant LE 2440/1-2, Grant LE 2440/2-1, and
Grant LE 2440/3-1 and in part by the European Commission through III. R ESULTS & D ISCUSSIONS
an ERC starting grant (InteGraDe, 307311). The review of this let-
ter was arranged by Editor D. Akinwande. (Corresponding author: The devices were characterized under ambient and vac-
Max C. Lemme.) uum conditions using a Keithley 4200 SCS Semiconductor
H. Pandey and S. Kataria are with the Chair for Electronic Devices, parameter analyzer. The measurements under vacuum were
RWTH Aachen University, 52074 Aachen, Germany.
A. Gahoi is with Graphene-based Nanotechnology, Universität Siegen, carried out using Lakeshore TTPX probe station connected
57076 Siegen, Germany. to a similar analyzer. Fig. 1 (a) shows a schematic of an
M. C. Lemme is with the Advanced Microelectronic Center Aachen, inverter circuit with ASBLG channels and Fig. 1 (b) shows
AMO GmbH, 52074 Aachen, Germany, and with the Chair for Electronic
Devices, RWTH Aachen University, 52074 Aachen, Germany, and also the optical micrograph of a fabricated ASBLG device in
with the Graphene-based Nanotechnology, Universität Siegen, 57076 co-planar waveguide layout, along with the equivalent circuit
Siegen, Germany (e-mail: lemme@amo.de). diagram for the inversion functionality overlaid to the real
Color versions of one or more of the figures in this letter are available
online at http://ieeexplore.ieee.org. device image for easy reference to the reader. Complementary-
Digital Object Identifier 10.1109/LED.2017.2768076 like inverters are obtained from these co-joined parallel gate
0741-3106 © 2017 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted,
but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1748 IEEE ELECTRON DEVICE LETTERS, VOL. 38, NO. 12, DECEMBER 2017
TABLE I
C OMPARISON W ITH P REVIOUS R EPORTS
IV. C ONCLUSIONS
Artificially stacked bilayer large-area CVD graphene
inverters offer performance improvements over single layer
Fig. 3. (a) The best gain observed in artificially stacked BLG FET
inverters, where also a near perfect input-output matching could be graphene devices irrespective of the top gate dielectric used.
realized at a VDD = 4.7 V in ambient conditions (Lg = 12 µm and An output matched Av > 4 is obtained for several devices
W = 20 µm). This improvement in voltage gain was observed as a trend on the same chip in our experiments, enabling cascading into
in a total of 47 devices characterized in this experiment. (b) Statistical
summary of inverter gain of 47 devices, measured in ambient and at zero more complex circuit architectures in the future. A maximum
back gate voltage. gain of > 7 was observed under input-output matching con-
dition at a supply voltage of 4.7 V. This improvement appears
threshold voltage condition. The threshold voltage or mid- to have its origins in higher transconductance and lower
point voltage (VM ) condition is marked in Fig. 2 as a red contact resistance. The present results indicate the potential of
dotted line along which VIN = VOUT = VM . Generally, large-area artificially stacked bilayer CVD graphene for future
maximum gain in conventional CMOS inverters is obtained device & circuit applications.
at VM = VDD /2 [23]. However, this condition is not fulfilled
if there is asymmetry in hole and electron mobilities, as it is ACKNOWLEDGMENT
often the case in graphene FETs (e.g. Fig. 1 (c) and (d)). The authors would like to acknowledge fruitful discussions
ASBLG inverters show higher Av at lower input voltages with M. Iannazzo, E. Alarcon, S. Fregonese, and T. Zimmer.
for the same VDD . In other words, the maximum gain is
observed closer to the switching threshold in ASBLG inverters. R EFERENCES
This results in improved noise margins and faster switching [1] M. C. Lemme, T. J. Echtermeyer, M. Baus, and H. Kurz, “A graphene
in ASBLG inverters compared to SLG inverters [23]. The field-effect device,” IEEE Electron Device Lett., vol. 28, no. 4,
pp. 282–284, Apr. 2007, doi: 10.1109/LED.2007.891668.
maximum gain of Av = 7.134 was observed in ASBLG [2] F. Schwierz, “Graphene transistors: Status, prospects, and prob-
inverters for VDD = 4.7 V, which occurs around the input- lems,” Proc. IEEE, vol. 101, no. 7, pp. 1567–1584, Jul. 2013,
output matched condition of VM = VIN = VOUT = 3.7 V doi: 10.1109/JPROC.2013.2257633.
[3] F. Traversi, V. Russo, and R. Sordan, “Integrated complementary
under ambient condition (Fig. 3 (a)). In contrast, a maximum graphene inverter,” Appl. Phys. Lett., vol. 94, no. 22, p. 223312, 2009,
of Av = 4 was observed in all fabricated SLG inverters doi: 10.1063/1.3148342.
1750 IEEE ELECTRON DEVICE LETTERS, VOL. 38, NO. 12, DECEMBER 2017
[4] H.-Y. Chen and J. Appenzeller, “Complementary-type graphene inverters [16] X. Chen, R. Xiang, P. Zhao, H. An, T. Inoue, S. Chiashi, and
operating at room-temperature,” in Proc. 69th Annu. Device Res. Conf., S. Maruyama, “Chemical vapor deposition growth of large single-
Jun. 2011, pp. 33–34, doi: 10.1109/DRC.2011.5994408. crystal Bernal-stacked bilayer graphene from ethanol,” Carbon, vol. 107,
[5] L. G. Rizzi, M. Bianchi, A. Behnam, E. Carrion, E. Guerriero, L. Polloni, pp. 852–856, Oct. 2016, doi: 10.1016/j.carbon.2016.06.078.
E. Pop, and R. Sordan, “Cascading wafer-scale integrated graphene [17] H. Pandey, J.-D. Aguirre-Morales, S. Kataria, S. Fregonese, V. Passi,
complementary inverters under ambient conditions,” Nano Lett., vol. 12, M. Iannazzo, T. Zimmer, E. Alarcon, and M. C. Lemme, “Enhanced
no. 8, pp. 3948–3953, Aug. 2012, doi: 10.1021/nl301079r. intrinsic voltage gain in artificially stacked bilayer CVD graphene
[6] D. Schall, M. Otto, D. Neumaier, and H. Kurz, “Integrated ring oscil- field effect transistors,” Ann. Phys., p. 1700106, Sep. 2017,
lators based on high-performance graphene inverters,” Sci. Rep., vol. 3, doi: 10.1002/andp.201700106.
Sep. 2013, Art. no. 2592, doi: 10.1038/srep02592. [18] S. Kataria, S. Wagner, J. Ruhkopf, A. Gahoi, H. Pandey,
[7] E. Guerriero, L. Polloni, M. Bianchi, A. Behnam, E. Carrion, R. Bornemann, S. Vaziri, A. D. Smith, M. Ostling, and M. C. Lemme,
L. G. Rizzi, E. Pop, and R. Sordan, “Gigahertz integrated graphene “Chemical vapor deposited graphene: From synthesis to applications,”
ring oscillators,” ACS Nano, vol. 7, no. 6, pp. 5588–5594, Jun. 2013, Phys. Status Solidi A, vol. 211, no. 11, pp. 2439–2449, Nov. 2014,
doi: 10.1021/nn401933v. doi: 10.1002/pssa.201400049.
[8] B. N. Szafranek, G. Fiori, D. Schall, D. Neumaier, and H. Kurz, “Current [19] S. Rodriguez, S. Vaziri, M. Ostling, A. Rusu, E. Alarcon, and
saturation and voltage gain in bilayer graphene field effect transistors,” M. C. Lemme, “RF performance projections of graphene FETs vs.
Nano Lett., vol. 12, no. 3, pp. 1324–1328, 2012, doi: 10.1021/nl2038634. silicon MOSFETs,” ECS Solid State Lett., vol. 1, no. 5, pp. Q39–Q41,
[9] J. B. Oostinga, H. B. Heersche, X. Liu, A. F. Morpurgo, and Aug. 2012, doi: 10.1149/2.001205ssl.
L. M. K. Vandersypen, “Gate-induced insulating state in bilayer [20] J. M. Yun, S. Park, Y. H. Hwang, E.-S. Lee, U. Maiti, H. Moon,
graphene devices,” Nature Mater., vol. 7, no. 2, pp. 151–157, Feb. 2008, B.-H. Kim, B.-S. Bae, Y.-H. Kim, and S. O. Kim, “Complementary
doi: 10.1038/nmat2082. p- and n-Type polymer doping for ambient stable graphene
[10] Y. Zhang, Y. Zhang, T. Tang, C. Girit, Z. Hao, M. C. Martin, A. Zettl, inverter,” ACS Nano, vol. 8, no. 1, pp. 650–656, Jan. 2014,
M. F. Crommie, Y. R. Shen, and F. Wang, “Direct observation of a widely doi: 10.1021/nn4053099.
tunable bandgap in bilayer graphene,” Nature, vol. 459, pp. 820–823, [21] S. Kim, J. Nah, I. Jo, D. Shahrjerdi, L. Colombo, Z. Yao, E. Tutuc, and
Jun. 2009, doi: 10.1038/nature08105. S. K. Banerjee, “Realization of a high mobility dual-gated graphene
[11] W. Zhang, C.-T. Lin, K.-K. Liu, T. Tite, C.-Y. Su, C.-H. Chang, field-effect transistor with Al2 O3 dielectric,” Appl. Phys. Lett., vol. 94,
Y.-H. Lee, C.-W. Chu, K.-H. Wei, J.-L. Kuo, and L.-J. Li, “Opening no. 6, p. 62107, 2009, doi: 10.1063/1.3077021.
an electrical band gap of bilayer graphene with molecular doping,” ACS [22] T. Cusati, G. Fiori, A. Gahoi, V. Passi, M. C. Lemme, A. Fortunelli,
Nano, vol. 5, no. 9, pp. 7517–7524, Sep. 2011, doi: 10.1021/nn202463g. and G. Iannaccone, “Electrical properties of graphene-metal contacts,”
[12] S.-L. Li, H. Miyazaki, A. Kumatani, A. Kanda, and K. Tsukagoshi, “Low Sci. Rep., vol. 7, Jul. 2017, Art. no. 5109, doi: 10.1038/s41598-
operating bias and matched input–output characteristics in graphene 017-05069-7.
logic inverters,” Nano Lett., vol. 10, no. 7, pp. 2357–2362, Jul. 2010, [23] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, 2nd ed.
doi: 10.1021/nl100031x. Cambridge, U.K.: Cambridge Univ. Press, 2010.
[13] H. Zhou, W. J. Yu, L. Liu, R. Cheng, Y. Chen, X. Huang, Y. Liu, [24] A. D. Smith, K. Elgammal, F. Niklaus, A. Delin, A. C. Fischer, S. Vaziri,
Y. Wang, Y. Huang, and X. Duan, “Chemical vapour deposition growth F. Forsberg, M. Råsander, H. Hugosson, L. Bergqvist, S. Schröder,
of large single crystals of monolayer and bilayer graphene,” Nature S. Kataria, M. Östling, and M. C. Lemme, “Resistive graphene humidity
Commun., vol. 4, Jun. 2013, Art. no. 2096, doi: 10.1038/ncomms3096. sensors with rapid and direct electrical readout,” Nanoscale, vol. 7,
[14] Z. Sun, A.-O. Raji, Y. Zhu, C. Xiang, Z. Yan, C. Kittrell, no. 45, pp. 19099–19109, 2015, doi: 10.1039/C5NR06038A.
E. L. G. Samuel, and J. M. Tour, “Large-area Bernal-stacked Bi-, [25] D. H. Tien, J.-Y. Park, K. B. Kim, N. Lee, and Y. Seo, “Characterization
Tri-, and tetralayer graphene,” ACS Nano, vol. 6, no. 11, pp. 9790–9796, of graphene-based FET fabricated using a shadow mask,” Sci. Rep.,
Nov. 2012, doi: 10.1021/nn303328e. vol. 6, no. 1, Jul. 2016, Art. no. 25050, doi: 10.1038/srep25050.
[15] W. Liu, S. Kraemer, D. Sarkar, H. Li, P. M. Ajayan, and K. Banerjee, [26] A. Gahoi, S. Wagner, A. Bablich, S. Kataria, V. Passi, and M. C. Lemme,
“Controllable and rapid synthesis of high-quality and large-area Bernal “Contact resistance study of various metal electrodes with CVD
stacked bilayer graphene using chemical vapor deposition,” Chem. graphene,” Solid-State Electron., vol. 125, pp. 234–239, Nov. 2016,
Mater., vol. 26, no. 2, pp. 907–915, Jan. 2014, doi: 10.1021/cm4021854. doi: 10.1016/j.sse.2016.07.008.