IMX323lq C
IMX323lq C
IMX323lq C
Preliminary IMX323LQN-C
Description
The IMX323LQN-C is a diagonal 6.23 mm (Type 1/2.9) CMOS active pixel type image sensor with a square pixel
array and approximately 2.12 M active pixels. This chip operates with analog 2.7 V, digital 1.2 V, and interface 1.8 V
triple power supplies. High sensitivity, low dark current and no smear are achieved through the adoption of R, G and
B primary color pigment mosaic filters. This chip features an electronic shutter with variable integration time.
(Applications: Consumer use drive recorder, Consumer use network camera)
Features
Sony reserves the right to change products and specifications without prior notice.
This information does not convey any license by any implication or otherwise under any patents or other right.
Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits.
Rev.0.2
1
IMX323LQN-C
Device Structure
2
IMX323LQN-C
This USE RESTRICTION NOTICE ("Notice") is for customers who are considering or currently using the
image sensor products ("Products") set forth in this specifications book. Sony Corporation ("Sony") may,
at any time, modify this Notice which will be available to you in the latest specifications book for the
Products. You should abide by the latest version of this Notice. If a Sony subsidiary or distributor has its
own use restriction notice on the Products, such a use restriction notice will additionally apply between
you and the subsidiary or distributor. You should consult a sales representative of the subsidiary or
distributor of Sony on such a use restriction notice when you consider using the Products.
Use Restrictions
The Products are intended for incorporation into such general electronic equipment as office products,
communication products, measurement products, and home electronics products in accordance with
the terms and conditions set forth in this specifications book and otherwise notified by Sony from time
to time.
You should not use the Products for critical applications which may pose a life- or injury-threatening
risk or are highly likely to cause significant property damage in the event of failure of the Products. You
should consult your sales representative beforehand when you consider using the Products for such
critical applications. In addition, you should not use the Products in weapon or military equipment.
Sony disclaims and does not assume any liability and damages arising out of misuse, improper use,
modification, use of the Products for the above-mentioned critical applications, weapon and military
equipment, or any deviation from the requirements set forth in this specifications book.
Export Control
If the Products are controlled items under the export control laws or regulations of various countries,
approval may be required for the export of the Products under the said laws or regulations.
You should be responsible for compliance with the said laws or regulations.
No License Implied
The technical information shown in this specifications book is for your reference purposes only. The
availability of this specifications book shall not be construed as giving any indication that Sony and its
licensors will license any intellectual property rights in such information by any implication or otherwise.
Sony will not assume responsibility for any problems in connection with your use of such information or
for any infringement of third-party rights due to the same. It is therefore your sole legal and financial
responsibility to resolve any such problems and infringement.
Governing Law
This Notice shall be governed by and construed in accordance with the laws of Japan, without reference
to principles of conflict of laws or choice of laws. All controversies and disputes arising out of or relating
to this Notice shall be submitted to the exclusive jurisdiction of the Tokyo District Court in Japan as the
court of first instance.
General-0.0.8
3
IMX323LQN-C
CONTENTS
Description -------------------------------------------------------------------------------------------------------------------------------------------- 1
Features ----------------------------------------------------------------------------------------------------------------------------------------------- 1
Device Structure ------------------------------------------------------------------------------------------------------------------------------------- 2
Absolute Maximum Ratings ----------------------------------------------------------------------------------------------------------------------- 2
Recommended Operating Conditions ----------------------------------------------------------------------------------------------------------- 2
USE RESTRICTION NOTICE -------------------------------------------------------------------------------------------------------------------- 3
Chip Center and Optical Center ------------------------------------------------------------------------------------------------------------------ 6
Pixel Arrangement ----------------------------------------------------------------------------------------------------------------------------------- 7
Block Diagram and Pin Configuration ----------------------------------------------------------------------------------------------------------- 8
Pin Description --------------------------------------------------------------------------------------------------------------------------------------- 9
Electrical Characteristics -------------------------------------------------------------------------------------------------------------------------- 11
DC Characteristics ------------------------------------------------------------------------------------------------------------------------------ 11
Current Consumption --------------------------------------------------------------------------------------------------------------------------- 11
AC Characteristics-------------------------------------------------------------------------------------------------------------------------------12
Master clock (INCK) --------------------------------------------------------------------------------------------------------------------------12
XVS and XHS Input Characteristics (In Slave Mode) ---------------------------------------------------------------------------------13
XVS, XHS Output Characteristics (In Master Mode) ----------------------------------------------------------------------------------13
Serial Communication (4-wire Serial)-----------------------------------------------------------------------------------------------------14
2
Serial Communication (I C) -----------------------------------------------------------------------------------------------------------------15
DCK and DO Output Characteristics -----------------------------------------------------------------------------------------------------16
I/O Equivalent Circuit Diagram-------------------------------------------------------------------------------------------------------------------17
Spectral Sensitivity Characteristics -------------------------------------------------------------------------------------------------------------18
Image Sensor Characteristics -------------------------------------------------------------------------------------------------------------------19
Zone Definition of Video Signal Shading ---------------------------------------------------------------------------------------------------19
Image Sensor Characteristics Measurement Method---------------------------------------------------------------------------------------20
Measurement Conditions ----------------------------------------------------------------------------------------------------------------------20
Color Coding of this Image Sensor and Readout -----------------------------------------------------------------------------------------20
Definition of standard imaging conditions --------------------------------------------------------------------------------------------------20
Measurement Method --------------------------------------------------------------------------------------------------------------------------21
Setting Registers with Serial Communication ------------------------------------------------------------------------------------------------22
Description of Setting Registers (4-wire) ---------------------------------------------------------------------------------------------------22
Register Communication Timing--------------------------------------------------------------------------------------------------------------22
Register Write and Read -----------------------------------------------------------------------------------------------------------------------23
Description of Setting Registers (I 2C) -------------------------------------------------------------------------------------------------------24
Register Communication Timing--------------------------------------------------------------------------------------------------------------24
Register Hold Setting ---------------------------------------------------------------------------------------------------------------------------25
Communication Protocol -----------------------------------------------------------------------------------------------------------------------26
Register Write and Read in I2C Communication ------------------------------------------------------------------------------------------27
Register Map ----------------------------------------------------------------------------------------------------------------------------------------30
2
I C only --------------------------------------------------------------------------------------------------------------------------------------------30
Chip ID: 02h --------------------------------------------------------------------------------------------------------------------------------------32
Chip ID: 03h --------------------------------------------------------------------------------------------------------------------------------------39
Readout Drive Mode -------------------------------------------------------------------------------------------------------------------------------40
Sync Code ----------------------------------------------------------------------------------------------------------------------------------------41
Sync Code Output Timing----------------------------------------------------------------------------------------------------------------------42
Image Data Output Format --------------------------------------------------------------------------------------------------------------------43
HD1080p Mode -------------------------------------------------------------------------------------------------------------------------------43
HD720p mode ---------------------------------------------------------------------------------------------------------------------------------46
Description of Various Functions ----------------------------------------------------------------------------------------------------------------48
Standby mode ------------------------------------------------------------------------------------------------------------------------------------48
Slave Mode and Master Mode ----------------------------------------------------------------------------------------------------------------49
Normal Sync mode ---------------------------------------------------------------------------------------------------------------------------50
XHSLNG Selection ---------------------------------------------------------------------------------------------------------------------------50
XVSLNG Selection ---------------------------------------------------------------------------------------------------------------------------50
DCK Sync mode ---------------------------------------------------------------------------------------------------------------------------------51
XHSLNG2 Selection -------------------------------------------------------------------------------------------------------------------------51
XVSLNG Selection ---------------------------------------------------------------------------------------------------------------------------51
Gain Adjustment Function ---------------------------------------------------------------------------------------------------------------------52
Black Level Adjustment Function -------------------------------------------------------------------------------------------------------------54
Horizontal and Vertical - Normal and Inverted Scan -------------------------------------------------------------------------------------55
Shutter and Integration Time Settings -------------------------------------------------------------------------------------------------------56
4
IMX323LQN-C
5
IMX323LQN-C
3.275 ± TBD mm
Package
Outline
V direction
5.75 ± 0.025 mm
Sensor
Scanning V direction
(normal)
Sensor
Scanning H direction
(normal)
7.55 ± 0.025 mm
H1-pin H10-pin
Optical Center
6
IMX323LQN-C
Pixel Arrangement
(Top View)
Reference pin
* Dummy column for horizontal inverted scan
A1.pin A10.pin
Normal scan: 0 pixel / Inverted scan: 1 pixel
G R G R G
B G B 4 Ignored area of Effective pixel side G B
9 Margin for color processing
Margin for color processing
Number of recommended
recording pixels: 1920(H) × 1080(V) = 2.07 M
Vertical scan direction (normal)
Ignored area of
Total number of pixels: 2000(H) × 1121(V) = 2.24 M
1080
16 24 8 1920 8 24
*
8 Vertical OB
4 Ignored area of OB
7
IMX323LQN-C
DO10
DO11
DCK
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
DO9
A4 C5 B5 A5 C6 B6 A6 C7 B7 A7 C8 B8 A8
CDS/Column Circuit
Bias
Drive Circuit
Sensor Control Unit
Sensor
(SCU)
Top View
Block Diagram
Index mark
1 2 3 4 5 6 7 8 9 10
GND GND INCK DCK DO2 DO5 DO8 DO11 TEST1 GND
A
VDDL VDDL GND VDDM DO1 DO4 DO7 DO10 VDDL GND
B
VDDL GND VDDL GND DO0 DO3 DO6 DO9 VDDL GND
C
VDDH GND GND GND VDDM VDDM GND VDDL GND VDDL
D
VDDH GND VDDH GND GND GND GND SDO SDI/SDA XCE
E
GND VDDH GND XCLR TEST2 VDDM VDDH SCK/SCL XMASTER TEST3
F
VCAP1 VCAP2 TEST4 XVS GND VDDL GND TEST5 GND VDDH
G
GND VDDH GND XHS VDDL GND VDDH VRL VCP GND
H
Pin Configuration
8
IMX323LQN-C
Pin Description
Pin Analog
I/O Symbol Description Remarks
No. /Digital
A1 GND D GND GND -
A2 GND D GND GND -
A3 I D INCK Master Clock 37.125MHz
A4 O D DCK Data clock -
A5 O D DO2 CMOS parallel output -
A6 O D DO5 CMOS parallel output -
A7 O D DO8 CMOS parallel output -
A8 O D DO11 CMOS parallel output -
A9 D A TEST1 TEST pin Fixed to Low
A10 GND D GND GND -
B1 Power D VDDL 1.2 V power supply -
B2 Power D VDDL 1.2 V power supply -
B3 GND D GND GND -
B4 Power D VDDM 1.8 V power supply -
B5 O D DO1 CMOS parallel output -
B6 O D DO4 CMOS parallel output -
B7 O D DO7 CMOS parallel output -
B8 O D DO10 CMOS parallel output -
B9 Power D VDDL 1.2 V power supply -
B10 GND D GND GND -
C1 Power D VDDL 1.2 V power supply -
C2 GND D GND GND -
C3 Power D VDDL 1.2 V power supply -
C4 GND D GND GND -
C5 O D DO0 CMOS parallel output -
C6 O D DO3 CMOS parallel output -
C7 O D DO6 CMOS parallel output -
C8 O D DO9 CMOS parallel output -
C9 Power D VDDL 1.2 V power supply -
C10 GND D GND GND -
D1 Power A VDDH 2.7 V power supply -
D2 GND A GND GND -
D3 GND A GND GND -
D4 GND D GND GND -
D5 Power D VDDM 1.8 V power supply -
D6 Power D VDDM 1.8 V power supply -
D7 GND D GND GND -
D8 Power D VDDL 1.2 V power supply -
D9 GND D GND GND -
D10 Power D VDDL 1.2 V power supply -
9
IMX323LQN-C
Pin Analog
I/O Symbol Description Remarks
No. /Digital
E1 Power A VDDH 2.7 V power supply -
E2 GND A GND GND -
E3 Power A VDDH 2.7 V power supply -
E4 GND D GND GND -
E5 GND D GND GND -
E6 GND D GND GND -
E7 GND A GND GND -
(4-wire): Serial I/F (register value input)
E8 O D SDO 2 -
(I C): Open
(4-wire): Serial I/F (register value output)
E9 I/O D SDI/SDA 2 -
(I C): SDA pin
(4-wire): Serial I/F (Chip enable)
E10 I D XCE -
(I2C): Fixed to High
F1 GND A GND GND -
F2 Power A VDDH 2.7 V power supply -
F3 GND A GND GND -
F4 I D XCLR System clear -
Normal sync mode: Open
F5 TEST D TEST2 -
DCK sync mode: Vertical sync signal
F6 Power D VDDM 1.8 V power supply -
F7 Power A VDDH 2.7 V power supply -
(4-wire): Serial I/F (clock input)
F8 I D SCK/SCL -
(I2C): SCL pin
Slave / Master selection High: 1.8V
F9 I D XMASTER
Slave mode: High / Master mode: Low Low: GND
F10 TEST D TEST3 TEST pin Fixed to Low
Connect to an
G1 TEST A VCAP1 Reference pin
external capacitor
Connect to an
G2 TEST A VCAP2 Reference pin
external capacitor
G3 TEST A TEST4 TEST pin Open
G4 I/O D XVS Vertical sync signal -
G5 GND D GND GND -
G6 Power D VDDL 1.2 V power supply -
G7 GND D GND GND -
G8 TEST D TEST5 TEST pin Fixed to High
G9 GND A GND GND -
G10 Power A VDDH 2.7 V power supply -
H1 GND A GND GND -
H2 Power A VDDH 2.7 V power supply -
H3 GND A GND GND -
H4 I/O D XHS Horizontal sync signal -
H5 Power D VDDL 1.2 V power supply -
H6 GND A GND GND -
H7 Power A VDDH 2.7 V power supply -
Connect to an
H8 I A VRL Connect to VCP pin
external capacitor
Connect to an
H9 O A VCP Connect to VRL pin
external capacitor
H10 GND D GND GND -
10
IMX323LQN-C
Electrical Characteristics
DC Characteristics
XHS
XVS VIH 0.8OV DD — — V
XCLR
INCK XVS/XHS:
Digital input voltage
XMASTER In slave mode
XCE
VIL — — 0.2OV DD V
SDI
SCK
OVDD –
VOH — — V
DO [11:0] 0.4
CMOS output
DCK
VOL — — 0.4 V
Digital output voltage
XHS OVDD –
VOH XVS/XHS: In — — V
XVS 0.4
master mode,
TEST2
SDO VOL CMOS output — — 0.4 V
Current Consumption
11
IMX323LQN-C
AC Characteristics
Master clock (INCK)
1/fINCK
0.8 × OVDD
tWHINCK
INCK 0.5 × OVDD
tWLINCK
0.2 × OVDD
tWP
tP
Duty Ratio = tWP / tP × 100
*1
The INCK fluctuation affects the frame rate. The sensor does not operate with specified frame rate except
for typical value.
12
IMX323LQN-C
0.8 × OVDD
INCK
0.2 × OVDD
tVHSU tVHHLD
0.8 × OVDD
XVS
tf tr
XHS 0.2 × OVDD
0.8 × OVDD
XVS tWLXVS
0.2 × OVDD
tVHDLY
0.8 × OVDD
XHS tWLXHS
0.2 × OVDD
13
IMX323LQN-C
0.8 × OVDD
XCLR tWLXCLR
0.2 × OVDD
tENXCE
0.8 × OVDD
XCE tWLXCE
0.2 × OVDD
tSUXCE tHDXCE
0.8 × OVDD
1/fSCK
SCK
0.2 × OVDD
tSUSDI tHDSDI
0.8 × OVDD
SDI DATA DATA
0.2 × OVDD
tSUSDO tHDSDO
0.8 × OVDD
SDO DATA
0.2 × OVDD
14
IMX323LQN-C
VIH/VOH
SDA
VIL/VOL
tf tHD;DAT tSU;STA tBUF
tLOW tSU;DAT tr
VIH
SCL
VIL
tHIGH
tHD;STA tr tHD;STA tSU;STO
(SCL・SDA) Low level input voltage VIL -0.3 -0.2OVDD -0.3 0.2OVDD V
(SCL・SDA) High level input voltage VIH 0.8OVDD 1.9 0.8OVDD 1.9 V
15
IMX323LQN-C
1/fDCK
DCK 0.5×OVDD
(DCKDLY = 0d)
DCK 0.5×OVDD
(DCKDLY = 1d)
tSKMINDOS tSKMAXDOS
The DCK frequency is the same as that of INCK when the FRSEL is set to 1.
16
IMX323LQN-C
: External pin
Symbol Equivalent circuit Symbol Equivalent circuit
VDDM
1 MΩ
Digital
INCK INCK XVS/XHS I/O
GND
VDDM
Digital
XCLR SDO output
XCLR
GND
VDDH
Schmitt
Buffer
TEST4 SDI Digital
Analog
Vcap1 Output SCK input
Vcap2 XCE
GND GND
GND
VDDM VDDM
VRL Pull-up
VCP GND
VRL TEST5
TEST5
VCP
GND GND
VDDM
TEST1
TEST3
TEST3 VDDM
TEST1
Pull-down
GND
GND GND
VDDM
DOx Digital
output
DCK
GND
17
IMX323LQN-C
0.7
Relative response
B
0.6
0.5
0.4
0.3
0.2
0.1
0.0
400 450 500 550 600 650 700 750 800 850 900 950 1000
Wavelength [nm]
18
IMX323LQN-C
(AVDD = 2.7 V, OVDD = 1.8 V, DVDD = 1.2 V, Tj = 60 ˚C, HD1080p 12-bit 30frame/s, Gain: 0 dB)
Measurement
Item Symbol Min. Typ. Max. Unit Remarks
method
Video signal
*3
Zone0-II' SH2D — — TBD % 4 —
shading
*1
Conversion is executed with 1 digit = 0.630 mV for 10-bit output and 1 digit = 0.1575 mV for 12-bit output.
*2
The video signal shading is the measured value in the wafer status (including color filter) and does not
include the seal glass characteristics.
*3
See the Zone Definition of Video Signal Shading (diagram below) for Zone.
1985 (H)
24 24
4
V
H 10 H
8 8
1105 (V)
Zone 0, I
4
Zone II, II’
Ignored region
V
Effective pixel region
10
19
IMX323LQN-C
Measurement Conditions
In the following measurements, the device drive conditions are at the typical values of the bias conditions and
clock voltage conditions.
In the following measurements, spot pixels are excluded and, unless otherwise specified, the optical black
(OB) level is used as the reference for the signal output, which is taken as the value of the Gr/Gb channel signal
output or the R/B channel signal output of the measurement system.
Gb B Gb B
R Gr R Gr
Gb B Gb B
R Gr R Gr
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IMX323LQN-C
Measurement Method
1. Sensitivity
Set the measurement condition to the standard imaging condition I. After setting the electronic shutter mode with a shutter speed of
1/100 s, measure the Gr and Gb signal outputs (VGr, VGb) at the center of the screen, and substitute the values into the following
formula.
2. Sensitivity ratio
Set the measurement condition to the standard imaging condition II. After adjusting the average value of the Gr and Gb signal
outputs to 464 mV, measure the R signal output (VR [mV]), the Gr and Gb signal outputs (VGr, VGb [mV]) and the B signal output
(VB [mV]) at the center of the screen in frame readout mode, and substitute the values into the following formulas.
VG = (VGr + VGb) / 2
Rr = VR / VG
Rb = VB / VG
3. Saturation signal
Set the measurement condition to the standard imaging condition II. After adjusting the luminous intensity to 20 times the intensity
with the average value of the Gr and Gb signal outputs, 464 mV, measure the average values of the Gr, Gb, R and B signal outputs.
21
IMX323LQN-C
This sensor can write and read the setting values of the various registers shown in the Register Map by 4-wire serial
communication and I2C communication. See the Register Map for the addresses and setting values to be set.
Because the two communication systems are judged at the first communication, once they are judged, the
2
communication cannot be switched until sensor reset. The pin for 4-wire serial communication and I C
2
communication is shared, so the external pin XCE must be fixed to power supply side when using I C
communication.
Some functions are set by different register according to communication method (4-wire / I2C).
Type Description
Designate the address according to the Register Map. When using a communication method that
Address designates continuous addresses, the address is automatically incremented from the previously
transmitted address.
XHS
Communication period Communication prohibited period
XVS
XHS
Communication period Communication prohibited period
22
IMX323LQN-C
Note) Even when changing register setting values during imaging, communication should finish within the 6H
communication period. When writing data to multiple registers with discontinuous addresses, access to
undesired registers can be avoided by repeating the above procedure multiple times. The figures on the
following page show examples of transmission.
XCE
SCK
SDI 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
SDO 0 1 2 3 4 5 6 7
XCE
SCK
SDI 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
SDO 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
Chip ID Start address N bytes of data Chip ID Start address N bytes of data
23
IMX323LQN-C
XCE
Slave address
MSB LSB
0 0 1 1 0 1 0 R/W
*R / W is data direction bit
R/W
R/W Data direction
0 Write (Master → Sensor)
1 Read (Sensor → Master)
XHS
XVS
XHS
24
IMX323LQN-C
Register details
Initial value Setting value
Register name Address bit
0h: Invalid
REGHOLD 0104h [0] 1
1h: Valid (register hold)
Communication period
XVS
Register
REGHOLD=1 Register setting A Register setting B Register setting C setting D REGHOLD=0
XHS
25
IMX323LQN-C
Communication Protocol
I2C serial communication supports a 16-bit register address and 8-bit data message type.
Communication protocol
―
Data is transferred serially, MSB first in 8-bit units. After each data byte is transferred, A (Acknowledge) / A
(Negative Acknowledge) is transferred. Data (SDA) is transferred at the clock (SDL) cycle. SDA can change only
while SCL is Low, so the SDA value must be held while SCL is High. The Start condition is defined by SDA changing
from High to Low while SCL is High. When the Stop condition is not generated in the previous communication phase
and Start condition for the next communication is generated, that Start condition is recognized as a Repeated Start
condition.
SCL
Start Condition
SCL
ACK/
SDA D5 D4 D3 D2 D1 D0 R/W NACK
P
SCL
Stop condition
Stop Condition
After transfer of each data byte, the Master or the sensor transmits an Acknowledge / Negative Acknowledge and
release (does not drive) SDA. When Negative Acknowledge is generated, the Master must immediately generate the
Stop Condition and end the communication.
SCL
SCL
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IMX323LQN-C
Index
Previous index value Index M
M+1
Index, value M
Index Index
Previous index value, K
K+1 K+2
Slave Slave
DATA DATA
S Address 1 A A P S Address 1 A A P
[7:0] [7:0]
[7:1] [7:1]
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IMX323LQN-C
Slave
DATA DATA DATA
S Address 1 A A A A A P
[7:0] [7:0] [7:0]
[7:1]
L bytes of data
28
IMX323LQN-C
Index
Previous index value Index M
M+1
Index, value M
29
IMX323LQN-C
Register Map
There are some functions that address is change according to communication method. When described as (I2C), this
function will be enabled by I2C communication. When described as (4-wire), this function will be enabled by 4-wire
communication.
I2C only
Default value
after reset Reflection
Address bit Register name Description
By By timing
register address
0000h [7:0]
to to Do not rewrite. ― ― ―
0007h [7:0]
2
0008h [0] I C BLKLEVEL [8] 2 0h
2 Black level offset value setting (I C) 040h Immediately
0009h [7:0] I C BLKLEVEL [7:0] 40h
000Ah [7:0]
to to Do not rewrite. ― ― -
00FFh [7:0]
Standby control (I2C)
[0] MODE_SEL 0: Standby 0h *1
1: Normal operation
[1] Fixed to 0 0h ―
[2] Fixed to 0 0h ―
0100h 00h
[3] Fixed to 0 0h ―
[4] Fixed to 0 0h ―
[5] Fixed to 0 0h ―
[6] Fixed to 0 0h ―
[7] Fixed to 0 0h ―
Horizontal (H) scanning
direction control (I2C)
[0] IMG_ORIENTATION_H 0h V
0: Normal
1: Inverted
Vertical (V) scanning
direction control (I2C)
[1] IMG_ORIENTATION_V 0h V
0: Normal
0101h 1: Inverted 00h
[2] Fixed to 0 0h ―
[3] Fixed to 0 0h ―
[4] Fixed to 0 0h ―
[5] Fixed to 0 0h ―
[6] Fixed to 0 0h ―
[7] Fixed to 0 0h ―
0102h [7:0]
to to Do not rewrite. ― ― ―
0103h [7:0]
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IMX323LQN-C
Default value
after reset Reflection
Address bit Register name Description
By By timing
register address
Register reflection timing hold
0: Normal communication mode.
[0] REG_HOLD When register setting is hold, 0h Immediately
reflection is applied.
1: Register setting hold
[1] Fixed to 0 0h ―
0104h 00h
[2] Fixed to 0 0h ―
[3] Fixed to 0 0h ―
[4] Fixed to 0 0h ―
[5] Fixed to 0 0h ―
[6] Fixed to 0 0h ―
[7] Fixed to 0 0h ―
0105h [7:0]
to to Do not rewrite. ― ― ―
0111h [7:0]
2
2 AD gradation setting (I C)
0112h [7:0] I C ADRES1 [7:0] 0Ah 0Ah V
0Ah: 10 bits, 0Ch: 12 bits
AD gradation setting (I2C)
0113h [7:0] I2C ADRES2 [7:0] 0Ah 0Ah V
0Ah: 10 bits, 0Ch: 12 bits
0114h [7:0]
to to Do not rewrite. ― ― ―
0201h [7:0]
0202h [7:0] INTEG_TIME [15:8] Integration time adjustment (I2C) 00h
0000h V
0203h [7:0] INTEG_TIME [7:0] Designated in line units 00h
0204h [7:0]
to to Do not rewrite. ― ― ―
033Fh [7:0]
0340h [7:0] FRM_LENGTH [15:8] In master mode. Vertical (V) 04h
direction line number 04E2h V
0341h [7:0] FRM_LENGTH [7:0] designation (I2C) E2h
0342h [7:0] LINE_LENGTH [15:8] In master mode. Horizontal (H) 04h
direction clock number 044Ch V
0343h [7:0] LINE_LENGTH [7:0] designation (I2C) 4Ch
0344h [7:0]
to to Do not rewrite. ― ― ―
2FFFh [7:0]
31
IMX323LQN-C
32
IMX323LQN-C
Default value
Address
after reset Reflection
bit Register name Description
2 By By timing
4-wire IC
register address
[0] LSB
[1]
[2]
[3]
05h 3005h E2h
[4]
[5]
[6] In master mode
[7] Vertical (V) direction line number
VMAX [15:0] 04E2h V
[0] designation
[1] (4-wire)
[2]
[3]
06h 3006h 04h
[4]
[5]
[6]
[7] MSB
07h 3007h [7:0] Fixed to “00h” 00h 00h ―
[0] LSB
[1]
[2]
[3]
08h 3008h 00h
[4]
[5]
[6]
Integration time adjustment
[7]
SHS1[15:0] Designated in line units 0000h V
[0]
(4-wire)
[1]
[2]
[3]
09h 3009h 00h
[4]
[5]
[6]
[7] MSB
0Ah 300Ah [7:0] Fixed to “00h” 00h 00h ―
0Bh 300Bh [7:0] Fixed to “00h” 00h 00h ―
0Ch 300Ch [7:0] Fixed to “00h” 00h 00h ―
0Dh 300Dh [7:0] Fixed to “00h” 00h 00h ―
0Eh 300Eh [7:0] Fixed to “00h” 00h 00h ―
0Fh 300Fh [7:0] Fixed to “00h” 00h 00h ―
10h 3010h [7:0] Fixed to “00h” 00h 00h ―
33
IMX323LQN-C
Default value
Address
after reset Reflection
bit Register name Description
2 By By timing
4-wire IC
register address
[0] Output data rate designation
0: 2 times INCK
[1] FRSEL [2:0] 0h V
1: Equal to INCK
[2] Others: Invalid
11h 3011h [3] Fixed to “0”. 0h 00h ―
[4] Fixed to “0”. 0h ―
[5] Fixed to “0”. 0h ―
[6] Fixed to “0”. 0h ―
[7] Fixed to “0”. 0h ―
Low-speed shutter forcible
[0] SSBRK 0h Immediately
termination
AD gradation setting (4-wire)
[1] ADRES 0h V
0: 10 bits, 1: 12 bits
[2] Fixed to “0”. 0h ―
12h 3012h 80h
[3] Fixed to “0”. 0h ―
[4] Fixed to “0”. 0h ―
[5] Fixed to “0”. 0h ―
[6] Fixed to “0”. 0h ―
[7] Fixed to “1”. 1h ―
13h 3013h [7:0] Fixed to “40h”. 40h 40h Immediately
14h 3014h [7:0] Fixed to “00h” 00h 00h ―
15h 3015h [7:0] Fixed to “00h” 00h 00h ―
HD1080p: 3Ch
16h 3016h [7:0] 00h 00h V
HD720p: F0h
17h 3017h [7:0] Fixed to “00h” 00h 00h ―
18h 3018h [7:0] Fixed to “00h” 00h 00h ―
19h 3019h [7:0] Fixed to “00h” 00h 00h ―
1Ah 301Ah [7:0] Fixed to “00h” 00h 00h ―
1Bh 301Bh [7:0] Fixed to “00h” 00h 00h ―
1Ch 301Ch [7:0] Fixed to “50h” 50h 50h ―
1Dh 301Dh [7:0] Fixed to “00h” 00h 00h ―
34
IMX323LQN-C
Default value
Address
after reset Reflection
bit Register name Description
2 By By timing
4-wire IC
register address
[0] LSB
[1]
[2]
[3]
1Eh 301Eh GAIN [7:0] Gain setting 00h 00h V
[4]
[5]
[6]
[7] MSB
1Fh 301Fh [7:0] Fixed to “73h”.*2 31h 31h ―
[0] LSB
[1]
[2]
[3]
20h 3020h Black level offset value setting 3Ch
[4] BLKLEVEL [8:0] 03Ch Immediately
(4-wire)
[5]
[6]
[7]
[0] MSB
[1] Fixed to “0”. 0h ―
[2] Fixed to “0”. 0h ―
[3] Fixed to “0”. 0h ―
21h 3021h 00h
[4] H sync pulse low level width 0h ―
XHSLNG [1:0]
[5] setting 1. 0h ―
[6] Fixed to “0”. 0h ―
[7] 10BITA Setting registers for 10 bit. 0h Immediately
[0]
V sync pulse low level width
[1] XVSLNG [2:0] 0h Immediately
setting.
[2]
[3] Fixed to “0”. 0h ―
22h 3022h 40h
[4] Fixed to “0”. 0h ―
[5] Fixed to “0”. 0h ―
[6] Fixed to “1”. 1h ―
[7] 720PMODE Fixed to 1 for HD720p mode. 0h V
23h 3023h [7:0]
to to to Do not rewrite. ― ― ―
26h 3026h [7:0]
27h 3027h [7:0] Fixed to “20h”.*2 21h 21h Immediately
28h 3028h [7:0]
to to to Do not rewrite. ― ― ―
2Bh 302Bh [7:0]
35
IMX323LQN-C
Default value
Address
after reset Reflection
bit Register name Description
2 By By timing
4-wire IC
register address
Trigger for master mode operation
start
[0] XMSTA 1h Immediately
0:Master mode operation start
1: Trigger standby
[1] Fixed to “0”. 0h ―
2Ch 302Ch [2] Fixed to “0”. 0h 01h ―
[3] Fixed to “0”. 0h ―
[4] Fixed to “0”. 0h ―
[5] Fixed to “0”. 0h ―
[6] Fixed to “0”. 0h ―
[7] Fixed to “0”. 0h ―
[0] Fixed to “0”. 0h ―
DCK phase delay
[1] DCKDLY For SDR output ... 0: 0°, 1: 180° 0h V
For DDR output... 0: 0°, 1: 90°
[2] Fixed to “0” 0h ―
2Dh 302Dh 10-bit output 2-bit shift 40h
[3] BITSEL 0h V
0: Left justified, 1: Right justified
[4] Fixed to “0”. 0h ―
[5] Fixed to “0”. 0h ―
[6] Fixed to “1”. 1h ―
[7] Fixed to “0”. 0h ―
2Eh 302Eh [7:0]
to to to Do not rewrite. ― ― ―
3Eh 303Eh [7:0]
3Fh 303Fh [7:0] Fixed to “0Ah”.*2 00h 00h Immediately
40h 3040h [7:0]
to to to Do not rewrite. ― ― ―
4Eh 304Eh [7:0]
Sync mode selection
4Fh 304Fh [7:0] SYNC2EN 07h: Normal sync mode 07h 07h Immediately
47h: DCK sync mode
50h 3050h [7:0]
to to to Do not rewrite. ― ― ―
53h 3053h [7:0]
[0]
H sync pulse low level width
[1] XHSLNG2 0 Immediately
setting 2.
[2]
[3] Fixed to “0”. 0 ―
Sync mode selection
54h 3054h 00h
[4] SYNCSEL 0: Normal sync mode 0 Immediately
1: DCK sync mode
[5] Fixed to “0”. 0 ―
[6] Fixed to “0”. 0 ―
[7] Fixed to “0”. 0 ―
55h 3055h [7:0]
to to to Do not rewrite. ― ― ―
79h 3079h [7:0]
36
IMX323LQN-C
Default value
Address
after reset Reflection
bit Register name Description
2 By By timing
4-wire IC
register address
7Ah 307Ah [7:0] 10BITB Setting registers for 10 bit. 00h 00h Immediately
7Bh 307Bh [7:0] 10BITC Setting registers for 10 bit. 00h 00h Immediately
7Ch 307Ch [7:0]
to to to Do not rewrite. ― ― ―
97h 3097h [7:0]
[0] LSB
[1]
[2]
[3]
98h 3098h 26h
[4]
[5] Adjustment registers for each
10B1080 P [11:0] 226h Immediately
[6] operation mode.
[7]
[0]
[1]
[2]
[3] MSB
99h 3099h 02h
[4] Fixed to “0”. 0h ―
[5] Fixed to “0”. 0h ―
[6] Fixed to “0”. 0h ―
[7] Fixed to “0”. 0h ―
[0] LSB
[1]
[2]
[3]
9Ah 309Ah 4Ch
[4]
[5] Adjustment registers for each
12B1080 P [11:0] 44Ch Immediately
[6] operation mode.
[7]
[0]
[1]
[2]
[3] MSB
9Bh 309Bh 04h
[4] Fixed to “0”. 0h ―
[5] Fixed to “0”. 0h ―
[6] Fixed to “0”. 0h ―
[7] Fixed to “0”. 0h ―
9Ch 309Ch [7:0]
to to to Do not rewrite ― ― ―
CDh 30CDh [7:0]
37
IMX323LQN-C
Default value
Address
after reset Reflection
bit Register name Description
2 By By timing
4-wire IC
register address
[0] LSB
[1]
[2]
Adjustment registers for each
[3] PRES[6:0] 16h
CEh 30CEh operation mode. 16h Immediately
[4]
[5]
[6] MSB
[7] Fixed to “0”. 0h
[0] LSB
[1]
[2]
[3]
CFh 30CFh Adjustment registers for each 82h
[4] DRES[8:0] 082h Immediately
operation mode.
[5]
[6]
[7]
[0] MSB
[1] Fixed to “0”. 0h ―
[2] Fixed to “0”. 0h ―
[3] Fixed to “0”. 0h ―
D0h 30D0h 00h
[4] Fixed to “0”. 0h ―
[5] Fixed to “0”. 0h ―
[6] Fixed to “0”. 0h ―
[7] Fixed to “0”. 0h ―
D1h 30D1h [7:0]
to to to Do not rewrite. ― ― ―
FFh 30FFh [7:0]
38
IMX323LQN-C
*1
The STANDBY (Address 00h [0]) register is reflected at the following timings.
•When canceling standby mode: Reflected immediately
•When entering standby mode: Reflected immediately after the end of the frame during which the setting
was made
*2
The values must be changed from the default values, so initial setting after reset is required after power-on.
Subsequent setting by communication is not needed unless the power is turned Off or the system is reset.
*3
“V” in the “Reflection timing” column indicates that the setting value is reflected at the falling edge of the
next XVS after the register communication is performed.
*4
Do not perform communication to addresses not listed in the Register Map. Doing so may result in
malfunction. However, other registers that require communication to addresses not listed above may
be added, so addresses up to FFh should be supported for both CID = 02h and 03h.
39
IMX323LQN-C
The table below lists the operating modes available with this sensor.
Imaging conditions
Number of *1
Drive Frame Output Data Data width 1H
INCK effective pixels
mode rate Resolution Rate Period
[MHz] H V H V
[frame/s] [bit] [Mpixel/s] [µs]
[pixels] [lines] [INCK] [lines]
15.00 10/12 37.125 2200 59.26
HD1080 p 25.00 10/12 74.25 1984 1105 1320 1125 35.56
37.125 30.00 10/12 74.25 1100 29.63
30.00 10/12 37.125 1650 44.44
HD720 p 1344 745 750
60.00 10 74.25 825 22.22
*1
The data width indicates the output sync signal period in master mode. In slave mode the data width is the
input XVS and XHS clock interval.
40
IMX323LQN-C
Sync Code
The sync code is added immediately before and after “dummy signal + OB signal + effective pixel data” and
then output. The sync code is output in order of 1st, 2nd, 3rd and 4th. The fixed value is output for 1st to 3rd.
(BLK: Blanking period)
XHS
SAV EAV
System delay
System delay
System delay
H.BLK
H.BLK
DATA
DATA
DATA
DATA
2nd
2nd
3rd
3rd
4th
4th
1st
1st
… ・・・・・・・ …
XVS
System delay Dummy for communication H.BLK
System delay Dummy for communication H.BLK
System delay SAV Dummy for communication EAV H.BLK
System delay (Invalid line) Dummy for communication (Invalid line) H.BLK
System delay Dummy for communication H.BLK
System delay Dummy for communication H.BLK
System delay Frame information line H.BLK
System delay H.OB/V.OB H.BLK
…
…
System delay SAV H.OB/V.OB EAV H.BLK
System delay (valid line) H.OB/effective pixel (Valid line) H.BLK
System delay H.OB/effective pixel H.BLK
…
…
System delay H.OB/effective pixel H.BLK
System delay V.BLK H.BLK
…
…
System delay Dummy for communication H.BLK
System delay SAV Dummy for communication EAV H.BLK
System delay (Invalid line) Dummy for communication (Invalid line) H.BLK
System delay Dummy for communication H.BLK
System delay Dummy for communication H.BLK
System delay Dummy for communication H.BLK
System delay SAV Frame information line EAV H.BLK
System delay (Valid line) H.OB/V.OB (Valid line) H.BLK
…
41
IMX323LQN-C
XHS
DCK
(DCKDLY=0d)
System delay
SAV EAV
The XVS and XHS fall timings can be changed as shown in figure below by setting to the DCK sync mode. In this
time, the before the change XVS pulse can be output from TEST2 pin (F5 pin)
XHS
DCK
(DCKDLY=0d)
SAV EAV
42
IMX323LQN-C
CFh [7:0]
DRES 082h 082h
D0h [0]
43
IMX323LQN-C
CFh [7:0]
DRES 082h 082h
D0h [0]
44
IMX323LQN-C
Effective margin
Effective margin
G B G B
Ignored area of
Ignored area of
Sync code
Sync code
1080 Recording pixel area
Number of pixels
in horizontal
SD 4 16 24 8 1920 8 (7)* 24 (25)* 4 HB direction:
R G R G
G B G B 2200
Effective margin for
G B 9 color processing
G B
R G R G * (): the number of when
Ignored area of inverted scan mode.
G B 4 effective pixel side
G B
R G R G
1 Vertical blanking period
XHS
Line No. during 1 2 3 4 5 12 13 14 15 16 17 24 25 26 1104 1105 1113 1114 1115 1116 1117
normal scan
Line No. during 1 2 3 4 5 12 1117 1116 1115 1114 1113 1106 1105 1106 26 25 17 16 15 14 13
inverted scan
6 1 4 8 4 8 1080 9 4 1
1 line: 2200 [pixels]
XHS (Normal Sync mode)
System delay
XHS (DCK sync mode)
XHSLNG2 = 1d
DCK
45
IMX323LQN-C
HD720p mode
The sensor signal is cut out with the angle of view for HD720p (1280 × 720) and read.
However, set “1” to the register 720P MODE (Address 22h [7].)
CFh [7:0]
DRES 082h 000h 181h
D0h [0]
46
IMX323LQN-C
Effective margin
Effective margin
G B G B
Ignored area of
Ignored area of
Sync code
Sync code
720 Recording pixel area
Number of pixels
in horizontal
SD 4 16 24 8 1280 8 (7)* 24 (25)* 4 HB direction:
R G R G
G B G B 1650
Effective margin for
G B 5 color processing
G B
R G R G * (): the number of when
Ignored area of inverted scan mode.
G B 2 effective pixel side
G B
R G R G
XHS
Line No. during 1 2 3 4 5 10 199 200 201 202 203 204 205 206 924 925 926 927 928 929 930 931
normal scan
Line No. during 1 2 3 4 5 10 931 930 929 928 927 926 925 924 206 205 204 203 202 201 200 199
inverted scan
6 1 4 6 2 4 720 5 2
1 line: 1650 [pixels]
XHS (Normal Sync mode)
System delay
XHS (DCK sync mode)
XHSLNG2 = 1d
DCK
DO during horizontal 1 16 338 361 362 369 370 1649 1650 1657 1658 1681
normal scan
8 24
DO during horizontal 1 16 1680 1657 1656 1649 1648 369 368 362 361 337
inverted scan
7 25
SD 4 16 24 8 1280 4 HB
1368
47
IMX323LQN-C
Standby mode
This sensor stops its operation and goes into standby mode which reduces the power consumption by writing
“1” to the standby control register STANDBY (address 00h, Bit [0]), in 4-wire communication, writing “0” to the register
MODE_SEL (address 0100h, Bit [0]) (Standby mode immediately after power-on and reset).
Standby mode is reflected after V. OB after the set frame.
Write to register is possible because the serial communication function operates even in standby mode.
Set the STANDBY register to “0” to cancel standby mode. The standby cancel is immediately reflected from
the communication.
1
Stop Stop
4-wire STANDBY 00h [0] 1 (Standby) Register
0 Operate Operate communication
is executed
0 even in standby
Stop Stop
2 (Standby) mode.
IC MODE_SEL 0100h [0] 1
1 Operate Operate
>220 µs
XVS (Normal sync mode)
TEST2 (DCK sync mode)
48
IMX323LQN-C
When a sensor is in slave mode, values set in the registers of the list above are invalid.
49
IMX323LQN-C
XHSLNG Selection
The low level pulse width of horizontal sync signal XHS is set by the XHSLNG register. The output has system
delay from the XHS fall to effective data (sync code) output.
DCK
(DCKDLY=0d)
System delay
SAV EAV
6 clk
XHSLNG = 0h
12 clk
XHSLNG = 1h
XHS
22 clk
XHSLNG = 2h
128 clk
XHSLNG = 3h
XVSLNG Selection
The low level pulse width of vertical sync signal XVS is set.
XHS
1H
XVSLNG = 0h
2H
XVSLNG = 1h
XVS
4H
XVSLNG = 2h
8H
XVSLNG = 3h
50
IMX323LQN-C
XHSLNG2 Selection
Set the low level pulse width of the XHS.
DCK
(DCKDLY=0d)
SAV EAV
2 DATA
XHSLNG2 = 0h
4 DATA
XHSLNG2 = 1h
XHS
8 DATA
XHSLNG2 = 2h
16 DATA
XHSLNG2 = 3h
XHSLNG2 = 5h
Include the sync code
XVSLNG Selection
Set the low level pulse width of the TEST2. The low level pulse width of the XVS is fixed to 1 H period.
XHS
1H
XVSLNG = 0h
2H
XVSLNG = 1h
TEST2
4H
XVSLNG = 2h
8H
XVSLNG = 3h
51
IMX323LQN-C
See the List of Gain Setting Register Value for Each Register.
Analog Gain
Analog + Digital Gain
45.0
42.0
39.0
36.0
33.0
30.0
27.0
Gain [dB]
24.0
21.0
18.0
15.0
12.0
9.0
6.0
3.0
0.0
6h
0h
Ch
2Ah
4Eh
8Ah
1Eh
5Ah
7Eh
12h
30h
36h
48h
54h
72h
78h
90h
96h
18h
24h
42h
60h
66h
84h
6Ch
3Ch
52
IMX323LQN-C
Gain [dB] GAIN [7:0] Gain [dB] GAIN [7:0] Gain [dB] GAIN [7:0]
0.0 0h 15.3 33h 30.6 66h
0.3 1h 15.6 34h 30.9 67h
0.6 2h 15.9 35h 31.2 68h
0.9 3h 16.2 36h 31.5 69h
1.2 4h 16.5 37h 31.8 6Ah
1.5 5h 16.8 38h 32.1 6Bh
1.8 6h 17.1 39h 32.4 6Ch
2.1 7h 17.4 3Ah 32.7 6Dh
2.4 8h 17.7 3Bh 33.0 6Eh
2.7 9h 18.0 3Ch 33.3 6Fh
3.0 Ah 18.3 3Dh 33.6 70h
3.3 Bh 18.6 3Eh 33.9 71h
3.6 Ch 18.9 3Fh 34.2 72h
3.9 Dh 19.2 40h 34.5 73h
4.2 Eh 19.5 41h 34.8 74h
4.5 Fh 19.8 42h 35.1 75h
4.8 10h 20.1 43h 35.4 76h
5.1 11h 20.4 44h 35.7 77h
5.4 12h 20.7 45h 36.0 78h
5.7 13h 21.0 46h 36.3 79h
6.0 14h 21.3 47h 36.6 7Ah
6.3 15h 21.6 48h 36.9 7Bh
6.6 16h 21.9 49h 37.2 7Ch
6.9 17h 22.2 4Ah 37.5 7Dh
7.2 18h 22.5 4Bh 37.8 7Eh
7.5 19h 22.8 4Ch 38.1 7Fh
7.8 1Ah 23.1 4Dh 38.4 80h
8.1 1Bh 23.4 4Eh 38.7 81h
8.4 1Ch 23.7 4Fh 39.0 82h
8.7 1Dh 24.0 50h 39.3 83h
9.0 1Eh 24.3 51h 39.6 84h
9.3 1Fh 24.6 52h 39.9 85h
9.6 20h 24.9 53h 40.2 86h
9.9 21h 25.2 54h 40.5 87h
10.2 22h 25.5 55h 40.8 88h
10.5 23h 25.8 56h 41.1 89h
10.8 24h 26.1 57h 41.4 8Ah
11.1 25h 26.4 58h 41.7 8Bh
11.4 26h 26.7 59h 42.0 8Ch
11.7 27h 27.0 5Ah 42.3 8Dh
12.0 28h 27.3 5Bh 42.6 8Eh
12.3 29h 27.6 5Ch 42.9 8Fh
12.6 2Ah 27.9 5Dh 43.2 90h
12.9 2Bh 28.2 5Eh 43.5 91h
13.2 2Ch 28.5 5Fh 43.8 92h
13.5 2Dh 28.8 60h 44.1 93h
13.8 2Eh 29.1 61h 44.4 94h
14.1 2Fh 29.4 62h 44.7 95h
14.4 30h 29.7 63h 45.0 96h
14.7 31h 30.0 64h
15.0 32h 30.3 65h
53
IMX323LQN-C
2 2
0008h [0]
IC I C BLKLEVEL 040h 03Ch 1FFh
0009h [7:0]
54
IMX323LQN-C
The sensor readout direction (normal/inverted) in vertical direction can be switched by the VREVERSE (address 01h
[0]) / IMG_ORIENTATION (address 0101h [1]) register setting. See the item of “Drive mode” for the order of readout
lines in normal and inverted modes. One invalid frame is generated when reading immediately after the readout
direction change in order to switch the normal operation and inversion between frames.
2
IMG_ORIENTATION_H [0] 0 0 (Horizontal) 1 (Horizontal)
IC 0101h
IMG_ORIENTATION_V [1] 0 0 (Vertical) 1 (Vertical)
A1.pin A1.pin
V Scan direction
V Scan direction
V (+) V (+)
H (+) H (+)
A1.pin A1.pin
V Scan direction
V Scan direction
V (+) V (+)
H (+) H (+)
55
IMX323LQN-C
Note) For integration time control, an image which reflects the setting is output from the frame after the setting
changes.
Note) 1. The frame period is determined by the input XVS when the sensor is operating in slave mode, or the
register VMAX value in master mode. The frame period is designated in 1H units, so the time is
determined by (Number of lines × 1H period).
2. See “Drive Modes” for the 1H period.
In this item, the shutter operation and integration time are shown as in the figure below with the time sequence
on the horizontal axis and the vertical address on the vertical axis. For simplification, shutter and readout
operation are noted in line units.
XHS
Chip Top side
Last line
Last-1 line
Last-2 line
Sensor
4 line
3 line
2 line
1 line
Chip bottom side
Output
Dummy/blanking Effective signal Dummy/blanking Effective signal
56
IMX323LQN-C
Register details
Initial
Communication Register Description
Address Bit value
name
08h [7:0]
SHS1 0000h Sets the shutter sweep time.
09h [7:0]
4-wire Sets the number of lines per frame
05h [7:0]
(only in master mode).
VMAX 04E2h See “Operating Modes” for the setting
06h [7:0] value in each mode.
lines
χ Frame2 α α α
Frame3 Frame4 Frame5 ……
Integration time Integration time Integration time Integration time
Output timing V-BLK Frame1 V-BLK Frame2 V-BLK Frame3 V-BLK Frame4 V-BLK Frame5 V-BLK
57
IMX323LQN-C
Long Exposure Operation (Control by Expanding the Number of Lines per Frame)
Long exposure operation can be performed by lengthening the frame period.
When the sensor is operating in slave mode, this is done by lengthening the input vertical sync signal (XVS) pulse
interval. When the sensor is operating in master mode, it is done by designating a larger register VMAX (address:
05h [7:0], 06h [7:0]) value compared to normal operation.
Likewise, in slave mode the integration time can be increased by lengthening the input XVS signal pulse interval.
When the integration time is extended by increasing the number of lines, the rear V blanking increases by an
equivalent amount.
The maximum VMAX and SHS1 values are 65535d. When the number of lines per frame is set to the maximum
value, the integration time in HD1080p mode at 30 frame/s is approximately 1.9 s. When set to a number of V lines or
more than that noted for each readout drive mode, the imaging characteristics are not guaranteed during long
exposure operation.
lines
Output timing V-BLK Frame1 V-BLK Frame2 V-BLK Frame3 V-BLK Frame4 V-BLK Frame5
Image Drawing of Long Exposure Time Control by Adjusting the Frame Period
58
IMX323LQN-C
59
IMX323LQN-C
The sensor signal is output in sync with the falling edge of the data clock (DCK). (When DCKDLY is set to “0h”)
Output in sync with the rising edge is possible by setting DCKDLY to “1h”.
60
IMX323LQN-C
Output Range
Output range
Output gradation
Minimum value Maximum value
10 bit 000h 3FEh
12 bit 000h FFEh
61
IMX323LQN-C
Mode Transitions
When changing the drive mode during sensor drive operation, an invalid frame is output. Data is output from sensor
during the invalid frame period, but the output values may not reflect the integration time or may not be uniform on
the screen, or a partially saturated image may be output.
Readout timing
HMAX(only in master mode )
Register reflection timing VMAX(only in master mode)
FRSEL
MODE
Time base
lines
*When changing the drive mode also changes the frame period, the number of
invalid frames is counted according to the frame period after the change.
62
IMX323LQN-C
Power-on/off Sequence
Power-on Sequence
Follow the sequence below to turn on the power supplies.
1. Turn on the power supplies so that the power supplies rise in order of 1.2 V power supply (DV DD) →
1.8 V power supply (OVDD) → 2.7 V power supply (AVDD). In addition, all power supplies should finish rising
within 200 ms.
2. Start master clock (INCK) input after turning on the power supplies.
3. The register values are undefined immediately after power-on, so the system must be cleared. Hold XCLR
at Low level for 500 ns or more after all the power supplies have finished rising. (The register values after
a system clear are the default values.)
In addition, hold XCE at High level during this period. The XCE rise timing differs according to the 1.8 V
power supply (OVDD), so hold XCE at High level until INCK is input.
The system clear is applied by setting XCLR to High level. However, the master clock needs to stabilize
before setting the XCLR pin to High level.
4. Make the sensor settings by register communication after the system clear. A period of 100 ns or more
should be provided after setting XCLR High before inputting the communication enable signal XCE in 4-wire
communication.
< 200 ms
2.7 V power supply (AVDD)
> 0 ns > 0 ns
1.8 V power supply (OVDD)
> 0 ns
INCK
tLOW > 500 ns
* In slave mode, hold the high impedance state until the power supplies have finished rising.
XVS
Hi-Z
XHS
Power-on Sequence
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Power-off Sequence
Turn Off the power supplies so that the power supplies fall in order of 2.7 V power supply (AVDD) → 1.8 V power
supply (OVDD) → 1.2 V power supply (DVDD). In addition, all power supplies should finish falling within 200 ms.
Set each digital input pin (INCK, XCE, SCK, SDI, XCLR, XMASTER, XVS, XHS) to 0 V or high impedance
before the 1.8 V power supply (OVDD) falls.
< 200 ms
2.7 V power supply (AVDD)
> 0 ms > 0 ms
1.8 V power supply (OVDD)
Power-off Sequence
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Note) XVS and XHS signals input when XCLR is Low are ignored. At this time the sensor is in standby
mode until the next XVS signal. Register communication is possible in standby mode.
>0 ns
INCK
XVS tVHSU <0 ns
Hi-Z tVHHLD < 5 ns
XHS tVHSU < 0 ns
Hi-Z tVHHLD < 5 ns
1H >220μs
2H 3H 4H 5H 6H
>100 ns
Communication period
tWLXCLR
> 500 ns
XCLR
tENXCE >100 ns
XCE
tSUXCE > 20ns tHDXCE > 20 ns
SCK
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Master mode
In master mode, the HMAX register (address 03h [7:0], 04h [5:0]) initial value is “44Ch” and the VMAX
register (address 05h [7:0], 06h [7:0]) initial value is “4E2h”, so both XVS and XHS are output at these initial
setting V and H widths until the setting values are reflected 6H later. When the VMAX and HMAX registers
are set to arbitrary values by serial communication at the initial setting, and the master mode start register
XMSTA (address 2Ch [0]) setting is changed from “1” to “0”, XVS and XHS start output according to the set
values from the 7th H after the register settings are reflected. However, when VMAX and HMAX are set
during the standby period, XVS and XHS are output according to the set values after standby is canceled.
>0 ns
INCK
XVS tVFDLY < 15 ns
XHS tHFDLY < 15 ns
1H 2H 3H 4H 5H 6H
Communication period
tWLXCLR
> 500 ns
XCLR
tENXCE > 100 ns
XCE
tSUXCE > 20 ns tHDXCE > 20 ns
SCK
XVS and XHS start output when the XMSTA register setting is changed from “1” to “0”.
In addition, the XVS and XHS pulse intervals are set by the VMAX and HMAX registers, respectivery.
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Peripheral Circuit
Power pins
1 0.1
D1 1 0.1
B1 1 0.1
B4
µF µF µF µF µF µF
1 0.1
E1 1 0.1
B2 1 0.1
D5
µF µF µF µF µF µF
1 0.1
E3 1 0.1
B9 1 0.1
D6
µF µF µF µF µF µF
1 0.1
F2 1 0.1
C1 1 0.1
F6
µF µF µF µF µF µF
1 0.1
F7 1 0.1
C3
µF µF µF µF
1 0.1
G10 1 0.1
C9
µF µF µF µF
1 0.1
H2 1 0.1
D8
µF µF µF µF
1 0.1
H7 1 0.1
D10
µF µF µF µF
1 0.1
G6
µF µF
1 0.1
H5
µF µF
Application circuits shown are typical examples illustrating the operation of the devices.
Sony cannot assume responsibility for any problems arising out of the use of these circuits or for
any infringement of third party patent and other right due to same.
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Signal pins
4-wire
IMX323 IMX323 VDDM IMX323
1.8 V
A3 INCK E10 XCE
10
kΩ
VDDM
E9 SDI/SDA G8 TEST5
1.8 V
10 10
F8 SCK/SCL * F5 TEST2
kΩ kΩ
G4 XVS
E8 SDO OPEN G3 TEST4
H4 XHS
A9 TEST1
F4 XCLR
I2C VDDM
F10 TEST3
1.8 V IMX323
F9 XMASTER E10 XCE
10 10
kΩ kΩ
10
µF E9 SDI/SDA * Normal sync mode: open
G1 VCAP1 DCK sync mode: vertical sync signal
0.22
µF F8 SCK/SCL
G2 VCAP2
1
E8 SDO
µF
H8 VRL
H9 VCP
Application circuits shown are typical examples illustrating the operation of the devices.
Sony cannot assume responsibility for any problems arising out of the use of these circuits or for
any infringement of third party patent and other right due to same.
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IMX323LQN-C
IMX323 IMX323
A1 E2 DCK A4
A2 E4 DO0 C5
A10 E5 DO1 B5
B3 E6 DO2 A5
B10 E7 DO3 C6
C2 F1 DO4 B6
C4 F3 DO5 A6
C10 G5 DO6 C7
D2 G7 DO7 B7
D3 G9 DO8 A7
D4 H1 DO9 C8
D7 H3 DO10 B8
D9 H6 DO11 A8
H10
Application circuits shown are typical examples illustrating the operation of the devices.
Sony cannot assume responsibility for any problems arising out of the use of these circuits or for
any infringement of third party patent and other right due to same.
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IMX323LQN-C
(AVDD = 2.7 V, OVDD = 1.8 V, DVDD = 1.2 V, Tj = 60 ˚C, 30 frame/s, Gain: 0 dB)
Black or white
30 % ≤ D TBD No evaluation criteria applied 1
pixels at high light
Black pixels at
D ≤ TBD mV 0 No evaluation criteria applied 3
signal saturated
Zone Definition
(1, 1) 4 OB side ignored area
(41, 5)
8 Vertical (V) direction effective OB (V.OB)
(1976, 12)
4 OB side ignored area (2000, 16)
(17, 17) 0 ZoneIII
(41, 17) 4 ZoneII'
616
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After delivery inspection of CMOS image sensors, cosmic radiation may distort pixels of CMOS image sensors,
and then distorted pixels may cause white point effects in dark signals in picture images. (Such white point
effects shall be hereinafter referred to as "White Pixels".) Unfortunately, it is not possible with current scientific
technology for CMOS image sensors to prevent such White Pixels. It is recommended that when you use CMOS
image sensors, you should consider taking measures against such White Pixels, such as adoption of automatic
compensation systems for White Pixels in dark signals and establishment of quality assurance standards.
Unless the Seller's liability for White Pixels is otherwise set forth in an agreement between you and the Seller,
Sony Corporation or its distributors (hereinafter collectively referred to as the "Seller") will, at the Seller's
expense, replace such CMOS image sensors, in the event the CMOS image sensors delivered by the Seller
are found to be to the Seller's satisfaction, to have over the allowable range of White Pixels as set forth as set
forth above under the heading "Spot Pixels Specifications", within the period of three months after the delivery
date of such CMOS image sensors from the Seller to you; provided that the Seller disclaims and will not
assume any liability after if you have incorporated such CMOS image sensors into other products.
Please be aware that Seller disclaims and will not assume any liability for (1) CMOS image sensors fabricated,
altered or modified after delivery to you, (2) CMOS image sensors incorporated into other products, (3) CMOS
image sensors shipped to a third party in any form whatsoever, or (4) CMOS image sensors delivered to you
over three months ago. Except the above mentioned replacement by Seller, neither Sony Corporation nor its
distributors will assume any liability for White Pixels. Please resolve any problem or trouble arising from or in
connection with White Pixels at your costs and expenses.
Note 1) The above data indicates the average occurrence rate of a single White Pixels that will occur when a
CMOS image sensor is left for a week.
For example, in a case of a device that has a 1 % occurrence rate per week at the 5.6 mV or higher
effect level, this means that if 1,000 devices are left for a week, a total of 10 devices out of the whole
1,000 devices will have a single White Pixels at the 5.6 mV or higher effect level.
Note 2) The occurrence rate of White Pixels fluctuates depending on the CMOS image sensor storage
environment (such as altitude, geomagnetic latitude and building structure), time (solar activity effects)
and so on. Moreover, there may be statistic errors. Please take notice and understand that this is an
example of test data with experiments that have being conducted over a specific time period and in
a specific environment.
Note 3) This data does not guarantee the upper limits of the occurrence rate of White Pixels.
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After setting the measurement condition to the standard imaging condition II, and the device drive conditions
are within the bias and clock voltage conditions. Configure the drive circuit according to the example and
measure.
White pixel
ViK
ViB
Black pixel Vi (I = R, G, B, VG = 464 mV)
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1 Rejected
Allowed
Note) 1. ●: Black circles indicate the positions of spot pixels. The patterns are specified separately for white
pixels, black pixels and bright spots.
(Example: Even when a black pixel and a white pixel are arranged as shown by pattern No. 1, this
is not judged as a defect (Allowed).)
2. Sensors exhibiting one or more patterns indicated as “Rejected” are sorted and removed.
3. Sensors exhibiting patterns indicated as “Allowed” are not subject to sorting and removal, and these
pixels are instead counted in the number of allowable spot pixels by zone.
4. White pixels and black pixels other than the patterns noted in the table above are all counted in the
number of allowable spot pixels by zone.
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CRA Characteristics
The recommended CRA characteristics is 0.0 degrees all over the image height (0 – 100 %),
because the target E.P.D. is infinite.
We assume that the worst case of E.P.D. is -30 mm. The CRA characteristics of -30 mm E.P.D. is
described below. The real CRA should be smaller than the table below.
4 15 0.47 0.89
20 0.62 1.19
3
25 0.78 1.49
2 30 0.93 1.78
35 1.09 2.08
1 40 1.25 2.38
0
45 1.40 2.68
0 10 20 30 40 50 60 70 80 90 100 50 1.56 2.97
55 1.71 3.27
Image height [%]
60 1.87 3.57
65 2.02 3.86
100% 70 2.18 4.16
75 2.34 4.45
Image height
80 2.49 4.75
85 2.65 5.04
1097
0%
90 2.80 5.34
95 2.96 5.63
Optical center 100 3.12 5.93
1936
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Notes On Handling
3. Installing (attaching)
(1) If a load is applied to the entire surface by a hard component, bending stress may be generated
and the package may fracture, etc., depending on the flatness of the bottom of the package.
Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive.
(2) The adhesive may cause the marking on the rear surface to disappear.
(3) If metal, etc., clash or rub against the package surface, the package may chip or fragment and
generate dust.
(4) Acrylate anaerobic adhesives are generally used to attach this product. In addition, cyanoacrylate
instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives to hold
the product in place until the adhesive completely hardens. (Reference)
(5) Note that the sensor may be damaged when using ultraviolet ray and infrared laser for mounting it.
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5. Others
(1) Do not expose to strong light (sun rays) for long periods, as the color filters of color devices will
be discolored.
(2) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage
or use in such conditions.
(3) This product is precision optical parts, so care should be taken not to apply excessive mechanical
shocks or force.
(4) Note that imaging characteristics of the sensor may be affected when approaching strong
electromagnetic wave or magnetic field during operation.
(5) Note that image may be affected by the light leaked to optical black when using an infrared cut
filter that has transparency in near infrared ray area during shooting subjects with high luminance.
Individual-2015.09.18
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Package Outline
(Unit: mm)
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* Exmor is a trademark of Sony Corporation. The Exmor is a version of Sony's high performance CMOS image sensor with
high-speed processing, low noise and low power dissipation by using column-parallel A/D conversion.
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