En DM00039193
En DM00039193
En DM00039193
STM32F051x8
ARM-based 32-bit MCU, 16 to 64 KB Flash, 11 timers, ADC,
DAC and communication interfaces, 2.0-3.6 V
Datasheet - production data
Features )%*$
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 ARM-Cortex-M0 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 14
3.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.2 Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.9 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.9.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 17
3.9.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 17
3.10 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.12 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.13 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.14 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.2 General-purpose timers (TIM2, 3, 14, 15, 16, 17) . . . . . . . . . . . . . . . . . 22
3.14.3 Basic timer TIM6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.14.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.14.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 47
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 48
6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.1 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.2 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.3 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.4 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.5 WLCSP36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.6 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.7 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
7.8.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.8.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 112
List of tables
List of figures
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F051xx microcontrollers.
This document should be read in conjunction with the STM32F0xxxx reference manual
(RM0091). The reference manual is available from the STMicroelectronics website
www.st.com.
For information on the ARM Cortex-M0 core, please refer to the Cortex-M0 Technical
Reference Manual, available from the www.arm.com website.
2 Description
12-bit DAC 1
(number of channels) (1)
Analog comparator 2
25 (on LQFP32)
GPIOs 29 39 55
27 (on UFQFPN32)
13 (on LQFP32)
Capacitive sensing channels 14 17 18
14 (on UFQFPN32)
Max. CPU frequency 48 MHz
Operating voltage 2.0 to 3.6 V
Ambient operating temperature: -40C to 85C / -40C to 105C
Operating temperature
Junction temperature: -40C to 105C / -40C to 125C
LQFP32 LQFP48 LQFP64
Packages WLCSP36
UFQFPN32 UFQFPN48 UFBGA64
1. The SPI1 interface can be used either in SPI mode or in I2S audio mode.
2. SPI2 is not present.
3. I2C2 is not present.
4. USART2 is not present.
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3 Functional overview
3.2 Memories
The device has the following features:
8 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states and featuring embedded parity checking with exception generation for fail-critical
applications.
The non-volatile memory is divided into two arrays:
16 to 64 Kbytes of embedded Flash memory for programs and data
Option bytes
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
Level 0: no readout protection
Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
Level 2: chip readout protection, debug features (Cortex -M0 serial wire) and
boot in RAM selection disabled
In Standby mode, it is put in power down mode. In this mode, the regulator output is in high
impedance and the kernel circuitry is powered down, inducing zero consumption (but the
contents of the registers and SRAM are lost).
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The I/O configuration can be locked if needed following a specific sequence in order to
avoid spurious writing to the I/Os registers.
sensor, voltage reference, VBAT voltage measurement) channels and performs conversions
in single-shot or scan modes. In scan mode, automatic conversion is performed on a
selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
hardware touch sensing controller and only requires few external components to operate.
For operation, one capacitive sensing GPIO in each group is connected to an external
capacitor and cannot be used as effective touch sensing channel.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library, which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
G1 3 3 3 3 3
G2 3 3 3 3 3
G3 3 2 2 2 1
G4 3 3 3 3 3
G5 3 3 3 3 3
G6 3 3 0 0 0
Number of capacitive
18 17 14 14 13
sensing channels
TIM2, TIM3
STM32F051xx devices feature two synchronizable 4-channel general-purpose timers. TIM2
is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based on a
16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent
channels each for input capture/output compare, PWM or one-pulse mode output. This
gives up to 12 input captures/output compares/PWMs on the largest packages.
The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advanced-
control timer via the Timer Link feature for synchronization or event chaining.
TIM2 and TIM3 both have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Their counters can be frozen in debug mode.
TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM14 features one single channel for input capture/output compare, PWM or one-pulse
mode output.
Its counter can be frozen in debug mode.
can be used either as a watchdog to reset the device when a problem occurs, or as a free
running timer for application timeout management. It is hardware or software configurable
through the option bytes. The counter can be frozen in debug mode.
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management. I2C1 also has a clock domain independent
from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address
match.
The I2C peripherals can be served by the DMA controller.
Refer to Table 9 for the differences between I2C1 and I2C2.
SMBus X -
Wakeup from STOP X -
1. X = supported.
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versions.
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Unless otherwise specified in brackets below the pin name, the pin function during and
Pin name
after reset is the same as the actual pin name
S Supply pin
Pin type I Input-only pin
I/O Input / output pin
FT 5 V-tolerant I/O
FTf 5 V-tolerant I/O, FM+ capable
TTa 3.3 V-tolerant I/O directly connected to ADC
I/O structure
TC Standard 3.3 V I/O
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after
Notes
reset.
Alternate
Functions selected through GPIOx_AFR registers
Pin functions
functions Additional
Functions directly selected/enabled through peripheral registers
functions
I/O structure
Pin type
Pin name
UFQFPN32
Notes
WLCSP36
UFBGA64
LQFP64
LQFP32
(function upon
Additional
reset) Alternate functions
functions
I/O structure
Pin type
Pin name
UFQFPN32
Notes
WLCSP36
UFBGA64
LQFP64
I/O structure
Pin type
Pin name
UFQFPN32
Notes
WLCSP36
UFBGA64
LQFP64
SPI1_MISO,
I2S1_MCK,
TIM3_CH1,
TIM1_BKIN,
22 G4 16 E3 12 12 PA6 I/O TTa - ADC_IN6
TIM16_CH1,
COMP1_OUT,
TSC_G2_IO3,
EVENTOUT
SPI1_MOSI,
I2S1_SD,
TIM3_CH2,
TIM14_CH1,
23 H4 17 F4 13 13 PA7 I/O TTa - TIM1_CH1N, ADC_IN7
TIM17_CH1,
COMP2_OUT,
TSC_G2_IO4,
EVENTOUT
24 H5 - - - - PC4 I/O TTa - EVENTOUT ADC_IN14
25 H6 - - - - PC5 I/O TTa - TSC_G3_IO1 ADC_IN15
TIM3_CH3,
TIM1_CH2N,
26 F5 18 F3 14 14 PB0 I/O TTa - ADC_IN8
TSC_G3_IO2,
EVENTOUT
TIM3_CH4,
TIM14_CH1,
27 G5 19 F2 15 15 PB1 I/O TTa - ADC_IN9
TIM1_CH3N,
TSC_G3_IO3
(4)
28 G6 20 D2 - 16 PB2 I/O FT TSC_G3_IO4 -
I2C2_SCL,
(5) CEC,
29 G7 21 - - - PB10 I/O FT -
TIM2_CH3,
TSC_SYNC
I2C2_SDA,
(5) TIM2_CH4,
30 H7 22 - - - PB11 I/O FT -
TSC_G6_IO1,
EVENTOUT
31 D4 23 F1 16 0 VSS S - - Ground
32 E4 24 E1 17 17 VDD S - - Digital power supply
I/O structure
Pin type
Pin name
UFQFPN32
Notes
WLCSP36
UFBGA64
LQFP64
SPI2_NSS,
(5) TIM1_BKIN,
33 H8 25 - - - PB12 I/O FT -
TSC_G6_IO2,
EVENTOUT
SPI2_SCK,
(5)
34 G8 26 - - - PB13 I/O FT TIM1_CH1N, -
TSC_G6_IO3
SPI2_MISO,
(5) TIM1_CH2N,
35 F8 27 - - - PB14 I/O FT -
TIM15_CH1,
TSC_G6_IO4
SPI2_MOSI,
(5) TIM1_CH3N,
36 F7 28 - - - PB15 I/O FT RTC_REFIN
TIM15_CH1N,
TIM15_CH2
37 F6 - - - - PC6 I/O FT - TIM3_CH1 -
38 E7 - - - - PC7 I/O FT - TIM3_CH2 -
39 E8 - - - - PC8 I/O FT - TIM3_CH3 -
40 D8 - - - - PC9 I/O FT - TIM3_CH4 -
USART1_CK,
TIM1_CH1,
41 D7 29 E2 18 18 PA8 I/O FT - -
EVENTOUT,
MCO
USART1_TX,
TIM1_CH2,
42 C7 30 D1 19 19 PA9 I/O FT - -
TIM15_BKIN,
TSC_G4_IO1
USART1_RX,
TIM1_CH3,
43 C6 31 C1 20 20 PA10 I/O FT - -
TIM17_BKIN,
TSC_G4_IO2
USART1_CTS,
TIM1_CH4,
44 C8 32 C2 21 21 PA11 I/O FT - COMP1_OUT, -
TSC_G4_IO3,
EVENTOUT
I/O structure
Pin type
Pin name
UFQFPN32
Notes
WLCSP36
UFBGA64
LQFP64
USART1_RTS,
TIM1_ETR,
45 B8 33 A1 22 22 PA12 I/O FT - COMP2_OUT, -
TSC_G4_IO4,
EVENTOUT
PA13 (6) IR_OUT,
46 A8 34 B1 23 23 I/O FT -
(SWDIO) SWDIO
47 D6 35 - - - PF6 I/O FT - I2C2_SCL -
48 E6 36 - - - PF7 I/O FT - I2C2_SDA -
PA14 (6) USART2_TX,
49 A7 37 B2 24 24 I/O FT -
(SWCLK) SWCLK
SPI1_NSS,
I2S1_WS,
50 A6 38 A2 25 25 PA15 I/O FT - USART2_RX, -
TIM2_CH1_ETR,
EVENTOUT
51 B7 - - - - PC10 I/O FT - -
52 B6 - - - - PC11 I/O FT - -
53 C5 - - - - PC12 I/O FT - -
54 B5 - - - - PD2 I/O FT - TIM3_ETR -
SPI1_SCK,
I2S1_CK,
55 A5 39 B3 26 26 PB3 I/O FT - TIM2_CH2, -
TSC_G5_IO1,
EVENTOUT
SPI1_MISO,
I2S1_MCK,
56 A4 40 A3 27 27 PB4 I/O FT - TIM3_CH1, -
TSC_G5_IO2,
EVENTOUT
SPI1_MOSI,
I2S1_SD,
57 C4 41 E6 28 28 PB5 I/O FT - I2C1_SMBA, -
TIM16_BKIN,
TIM3_CH2
I/O structure
Pin type
Pin name
UFQFPN32
Notes
WLCSP36
UFBGA64
LQFP64
I2C1_SCL,
USART1_TX,
58 D3 42 C4 29 29 PB6 I/O FTf - -
TIM16_CH1N,
TSC_G5_IO3
I2C1_SDA,
USART1_RX,
59 C3 43 A4 30 30 PB7 I/O FTf - -
TIM17_CH1N,
TSC_G5_IO4
60 B4 44 B4 31 31 BOOT0 I B - Boot memory selection
I2C1_SCL,
(4)(5) CEC,
61 B3 45 - - 32 PB8 I/O FTf -
TIM16_CH1,
TSC_SYNC
I2C1_SDA,
(5) IR_OUT,
62 A3 46 - - - PB9 I/O FTf -
TIM17_CH1,
EVENTOUT
63 D5 47 D6 32 0 VSS S - - Ground
64 E5 48 A5 1 1 VDD S - - Digital power supply
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These GPIOs must not be used as current sources (e.g. to drive an LED).
2. After the first RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content
of the RTC registers which are not reset by the main reset. For details on how to manage these GPIOs, refer to the RTC
domain and RTC register descriptions in the reference manual.
3. Distinct VSSA pin is only available on packages with 48 and more pins. For all other packages, the pin number corresponds
to the VSS pin to which VSSA pad of the silicon die is connected.
4. On the LQFP32 package, PB2 and PB8 must be set to defined levels by software, as their corresponding pads on the
silicon die are left unconnected. Apply the same recommendations as for unconnected pins.
5. On the WLCSP36 package, PB8, PB9, PB10, PB11, PB12, PB13, PB14 and PB15 must be set to defined levels by
software, as their corresponding pads on the silicon die are left unconnected. Apply the same recommendations as for
unconnected pins.
6. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on the SWDIO pin
and the internal pull-down on the SWCLK pin are activated.
5 Memory mapping
To the difference of STM32F051x8 memory map in Figure 10, the two bottom code memory
spaces of STM32F051x4/STM32F051x6 end at 0x0000 3FFF/0x0000 7FFF and 0x0800
3FFF/0x0000 7FFF, respectively.
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Figure 11. Pin loading conditions Figure 12. Pin input voltage
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Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
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IVDD Total current into sum of all VDD power lines (source)(1) 120
(1)
IVSS Total current out of sum of all VSS ground lines (sink) -120
(1)
IVDD(PIN) Maximum current into each VDD power pin (source) 100
IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) -100
Output current sunk by any I/O and control pin 25
IIO(PIN)
Output current source by any I/O and control pin -25
(2)
Total output current sunk by sum of all I/Os and control pins 80
IIO(PIN)
Total output current sourced by sum of all I/Os and control pins(2) -80 mA
Injected current on B, FT and FTf pins -5/+0(4)
IINJ(PIN) (3) Injected current on TC and RST pin 5
(5)
Injected current on TTa pins 5
IINJ(PIN) Total injected current (sum of all I/O and control pins)(6) 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
3. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer to Table 17: Voltage characteristics for the maximum allowed input voltage values.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
5. On these I/Os, a positive injection is induced by VIN > VDDA. Negative injection disturbs the analog performance of the
device. See note (2) below Table 54: ADC accuracy.
6. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
VREFINT Internal reference voltage 40 C < TA < +105 C 1.2 1.23 1.25 V
ADC_IN17 buffer startup
tSTART - - - 10(1) s
time
ADC sampling time when
tS_vrefint reading the internal - 4(1) - - s
reference voltage
Internal reference voltage
VREFINT spread over the VDDA = 3 V - - 10(1) mV
temperature range
Table 25. Typical and maximum current consumption from VDD at 3.6 V
All peripherals enabled All peripherals disabled
Table 25. Typical and maximum current consumption from VDD at 3.6 V (continued)
All peripherals enabled All peripherals disabled
Table 26. Typical and maximum current consumption from the VDDA supply
VDDA = 2.4 V VDDA = 3.6 V
Conditions
Symbol Parameter (1) fHCLK Max @ TA(2) Max @ TA(2) Unit
Typ Typ
25 C 85 C 105 C 25 C 85 C 105 C
Table 27. Typical and maximum current consumption in Stop and Standby modes
Typ @VDD (VDD = VDDA) Max(1)
Sym- Para-
Conditions Unit
bol meter TA = TA = TA =
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
25 C 85 C 105 C
Regulator in run
(2) (2)
Supply mode, all oscillators 15 15.1 15.3 15.5 15.7 16
current OFF
in Stop Regulator in low-
mode power mode, all 3.2 3.3 3.4 3.5 3.7 4 (2) (2)
Regulator in run
Supply mode, all 1.9 2 2.2 2.3 2.5 2.6 3.5(2) 3.5 4.5(2)
current oscillators OFF
VDDA monitoring ON
current
in Stop Regulator in low-
mode power mode, all 1.1 1.2 1.2 1.2 1.3 1.4 - - -
oscillators OFF
Supply LSI ON and
1.5 1.6 1.7 1.8 1.9 2.0 - - -
current IWDG ON
in
Standby LSI OFF and
1 1.0 1.1 1.1 1.2 1.2 - - -
mode IWDG OFF
1. Data based on characterization results, not tested in production unless otherwise specified.
2. Data based on characterization results and tested in production (using one common test limit for sum of IDD and IDDA).
Table 28. Typical and maximum current consumption from the VBAT supply
Typ @ VBAT Max(1)
1.65 V
2.7 V
1.8 V
2.4 V
3.3 V
3.6 V
TA = TA = TA =
25 C 85 C 105 C
Table 29. Typical current consumption, code executing from Flash memory,
running from HSE 8 MHz crystal
Typical consumption in Typical consumption in
Run mode Sleep mode
Symbol Parameter fHCLK Unit
Peripherals Peripherals Peripherals Peripherals
enabled disabled enabled disabled
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 31: Peripheral current consumption), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the I/O
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
I SW = V DDIOx f SW C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDIOx is the I/O supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT + CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
4 MHz 0.07
8 MHz 0.15
VDDIOx = 3.3 V
C =CINT 16 MHz 0.31
24 MHz 0.53
48 MHz 0.92
4 MHz 0.18
4 MHz 0.66
VDDIOx = 2.4 V
CEXT = 47 pF 8 MHz 1.43
C = CINT + CEXT+ CS 16 MHz 2.45
C = Cint
24 MHz 4.97
1. CS = 7 pF (estimated value).
BusMatrix(1) 5
DMA1 7
SRAM 1
Flash memory interface 14
CRC 2
GPIOA 9
AHB A/MHz
GPIOB 12
GPIOC 2
GPIOD 1
GPIOF 1
TSC 6
All AHB peripherals 55
Regulator in run
3.2 3.1 2.9 2.9 2.8 5
Wakeup from Stop mode
tWUSTOP
mode Regulator in low
7.0 5.8 5.2 4.9 4.6 9
power mode
s
Wakeup from
tWUSTANDBY - 60.4 55.6 53.5 52 51 -
Standby mode
Wakeup from Sleep
tWUSLEEP - 4 SYSCLK cycles -
mode
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For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (Typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 17). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 Oscillator
design guide for ST microcontrollers available from the ST website www.st.com.
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design guide for ST microcontrollers available from the ST website www.st.com.
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Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
Figure 19. HSI oscillator accuracy characterization results for soldered parts
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Software recommendations
The software flowchart must include the management of runaway conditions such as:
Corrupted program counter
Unexpected reset
Critical Data corruption (for example control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
0.1 to 30 MHz -3
VDD = 3.6 V, TA = 25 C,
LQFP64 package 30 to 130 MHz 28 dBV
SEMI Peak level
compliant with 130 MHz to 1 GHz 23
IEC 61967-2
EMI Level 4 -
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Weak pull-down
RPD equivalent VIN = - VDDIOx 25 40 55 k
resistor(3)
CIO I/O pin capacitance - - 5 - pF
1. Data based on design simulation only. Not tested in production.
2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 47:
I/O current injection susceptibility.
3. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 21 for standard I/Os, and in Figure 22 for
5 V-tolerant I/Os. The following curves are design simulation results, not tested in
production.
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VOL Output low level voltage for an I/O pin CMOS port(2) - 0.4
|IIO| = 8 mA V
VOH Output high level voltage for an I/O pin VDDIOx 2.7 V VDDIOx0.4 -
VOL Output low level voltage for an I/O pin TTL port(2) - 0.4
|IIO| = 8 mA V
VOH Output high level voltage for an I/O pin VDDIOx 2.7 V 2.4 -
VOL(3) Output low level voltage for an I/O pin |IIO| = 20 mA - 1.3
V
VOH(3) Output high level voltage for an I/O pin VDDIOx 2.7 V VDDIOx1.3 -
VOL(3) Output low level voltage for an I/O pin - 0.4
|IIO| = 6 mA V
VOH(3) Output high level voltage for an I/O pin VDDIOx0.4 -
|IIO| = 20 mA
Output low level voltage for an FTf I/O pin in - 0.4 V
VOLFm+(3) VDDIOx 2.7 V
Fm+ mode
|IIO| = 10 mA - 0.4 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 17:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings IIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Data based on characterization results. Not tested in production.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 23 and
Table 50, respectively. Unless otherwise specified, the parameters given are derived from
tests performed under the ambient temperature and supply voltage conditions summarized
in Table 20: General operating conditions.
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The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
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1. Refer to Table 52: ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
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1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
No hysteresis
- - 0 -
(COMPxHYST[1:0]=00)
High speed mode 3 13
Low hysteresis
8
(COMPxHYST[1:0]=01) All other power 5 10
modes
Vhys Comparator hysteresis High speed mode 7 26 mV
Medium hysteresis
15
(COMPxHYST[1:0]=10) All other power 9 19
modes
High speed mode 18 49
High hysteresis
31
(COMPxHYST[1:0]=11) All other power 19 40
modes
1. Data based on characterization results, not tested in production.
2. For more details and conditions see Figure 28: Maximum VREFINT scaler startup time from power down.
Figure 28. Maximum VREFINT scaler startup time from power down
ss s
ss s
ss s
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d
- - 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 48 MHz - 20.8 - ns
Timer external clock - - fTIMxCLK/2 - MHz
fEXT frequency on CH1 to
CH4 fTIMxCLK = 48 MHz - 24 - MHz
/4 0 0.1 409.6
/8 1 0.2 819.2
/16 2 0.4 1638.4
/32 3 0.8 3276.8 ms
/64 4 1.6 6553.6
/128 5 3.2 13107.2
/256 6 or 7 6.4 26214.4
1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
1 0 0.0853 5.4613
2 1 0.1706 10.9226
ms
4 2 0.3413 21.8453
8 3 0.6826 43.6906
SPI/I2S characteristics
Unless otherwise specified, the parameters given in Table 63 for SPI or in Table 64 for I2S
are derived from tests performed under the ambient temperature, fPCLKx frequency and
supply voltage conditions summarized in Table 20: General operating conditions.
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
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2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
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chain operations, are not indicated below.
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samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
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b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
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E - 12.000 - - 0.4724 -
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The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
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chain operations, are not indicated below.
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usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
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D3 - 5.500 - - 0.2165 -
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Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
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samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
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The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
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chain operations, are not indicated below.
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usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
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1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Back side coating.
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
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'VP 069
Pitch 0.4 mm
260 m max. (circular)
Dpad
220 m recommended
Dsm 300 m min. (for 260 m diameter pad)
PCB pad design Non-solder mask defined via underbump allowed
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
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b 0.300 0.370 0.450 0.0118 0.0146 0.0177
c 0.090 - 0.200 0.0035 - 0.0079
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D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.600 - - 0.2205 -
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1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
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usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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8 Ordering information
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, please contact your nearest ST sales office.
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = General-purpose
Sub-family
051 = STM32F051xx
Pin count
K = 32 pins
T = 36 pins
C = 48 pins
R = 64 pins
Package
H = UFBGA
T = LQFP
U = UFQFPN
Y = WLCSP
Temperature range
6 = 40 C to +85 C
7 = 40 C to +105 C
Options
xxx = code ID of programmed parts (includes packing type)
TR = tape and reel packing
blank = tray packing
9 Revision history
STMicroelectronics NV and its subsidiaries (ST) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to STs terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers products.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.