MM74HC595 8-Bit Shift Registers with Output Latches

September 1983
Revised February 1999

MM74HC595
8-Bit Shift Registers with Output Latches
General Description The 74HC logic family is speed, function, and pin-out com-
patible with the standard 74LS logic family. All inputs are
The MM74HC595 high speed shift register utilizes protected from damage due to static discharge by internal
advanced silicon-gate CMOS technology. This device pos- diode clamps to VCC and ground.
sesses the high noise immunity and low power consump-
tion of standard CMOS integrated circuits, as well as the
ability to drive 15 LS-TTL loads. Features
This device contains an 8-bit serial-in, parallel-out shift reg- ■ Low quiescent current: 80 µA maximum (74HC Series)
ister that feeds an 8-bit D-type storage register. The stor- ■ Low input current: 1 µA maximum
age register has 8 3-STATE outputs. Separate clocks are ■ 8-bit serial-in, parallel-out shift register with storage
provided for both the shift register and the storage register.
■ Wide operating voltage range: 2V–6V
The shift register has a direct-overriding clear, serial input,
and serial output (standard) pins for cascading. Both the ■ Cascadable
shift register and storage register use positive-edge trig- ■ Shift register has direct clear
gered clocks. If both clocks are connected together, the ■ Guaranteed shift frequency: DC to 30 MHz
shift register state will always be one clock pulse ahead of
the storage register.

Ordering Code:
Order Number Package Number Package Description
MM74HC595M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC595WM M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HC595SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC595MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC595N N16E 16-Lead Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram Truth Table

Pin Assignments for DIP, SOIC, SOP and TSSOP RCK SCK SCLR G Function
X X X H QA thru QH = 3-STATE
X X L L Shift Register cleared
QH = 0
X ↑ H L Shift Register clocked
QN = Qn-1, Q0 = SER
↑ X H L Contents of Shift
Register transferred
to output latches

Top View

© 1999 Fairchild Semiconductor Corporation DS005342.prf www.fairchildsemi.com

MM74HC595
Logic Diagram
(positive logic)

www.fairchildsemi.com 2
 MM74HC595
Absolute Maximum Ratings(Note 1) Recommended Operating
(Note 2) Conditions
Supply Voltage (VCC) −0.5 to +7.0V Min Max Units
DC Input Voltage (VIN) −1.5 to VCC +1.5V Supply Voltage (VCC) 2 6 V
DC Output Voltage (VOUT) −0.5 to VCC +0.5V DC Input or Output Voltage
Clamp Diode Current (IIK, IOK) ±20 mA (VIN, VOUT) 0 VCC V
DC Output Current, per pin (IOUT) ±35 mA Operating Temperature Range (TA) −40 +85 °C
DC VCC or GND Current, Input Rise or Fall Times
per pin (ICC) ±70 mA (tr, tf) VCC = 2.0V 1000 ns
Storage Temperature Range (TSTG) −65°C to +150°C VCC = 4.5V 500 ns
Power Dissipation (PD) VCC = 6.0V 400 ns
(Note 3) 600 mW Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
S.O. Package only 500 mW
Note 2: Unless otherwise specified all voltages are referenced to ground.
Lead Temperature (TL)
Note 3: Power Dissipation temperature derating — plastic “N” package: −
(Soldering 10 seconds) 260°C 12 mW/°C from 65°C to 85°C.

DC Electrical Characteristics (Note 4)

TA = 25°C TA = −40 to 85°C TA = −55 to 125°C

Symbol Parameter Conditions VCC Units
Typ Guaranteed Limits
VIH Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
VIL Maximum LOW Level 2.0V 0.5 0.5 0.5 V
Input Voltage 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
VOH Minimum HIGH Level VIN = VIH or VIL
Output Voltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
QH VIN = VIH or VIL
|IOUT| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
|IOUT| ≤ 5.2 mA 6.0V 5.2 5.48 5.34 5.2 V
QA thru QH VIN = VIH or VIL
|IOUT| ≤ 6.0 mA 4.5V 4.2 3.98 3.84 3.7 V
|IOUT| ≤ 7.8 mA 6.0V 5.7 5.48 5.34 5.2 V
VOL Maximum LOW Level VIN = VIH or VIL
Output Voltage |IOUT| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
QH VIN = VIH or VIL
|IOUT| ≤ 4 mA 4.5V 0.2 0.26 0.33 0.4 V
|IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
QA thru QH VIN = VIH or VIL
|IOUT| ≤ 6.0 mA 4.5V 0.2 0.26 0.33 0.4 V
|IOUT| ≤ 7.8 mA 6.0V 0.2 0.26 0.33 0.4 V
IIN Maximum Input VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA
Current
IOZ Maximum 3-STATE VOUT = VCC or GND 6.0V ±0.5 ±5.0 ±10 µA
Output Leakage G = V IH
ICC Maximum Quiescent VIN = VCC or GND 6.0V 8.0 80 160 µA
Supply Current IOUT = 0 µA
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-
rent (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.

3 www.fairchildsemi.com
MM74HC595
AC Electrical Characteristics
VCC = 5V, TA = 25°C, tr = tf = 6 ns
Guaranteed
Symbol Parameter Conditions Typ Units
Limit
fMAX Maximum Operating 50 30 MHz
Frequency of SCK
tPHL, tPLH Maximum Propagation CL = 45 pF 12 20 ns
Delay, SCK to QH’
tPHL, tPLH Maximum Propagation CL = 45 pF 18 30 ns
Delay, RCK to QA thru QH
tPZH, tPZL Maximum Output Enable RL = 1 kΩ
Time from G to QA thru QH CL = 45 pF 17 28 ns
tPHZ, tPLZ Maximum Output Disable RL = kΩ 15 25 ns
Time from G to QA thru QH CL = 5 pF
tS Minimum Setup Time 20 ns
from SER to SCK
tS Minimum Setup Time 20 ns
from SCLR to SCK
tS Minimum Setup Time 40 ns
from SCK to RCK
(Note 5)
tH Minimum Hold Time 0 ns
from SER to SCK
tW Minimum Pulse Width 16 ns
of SCK or RCK
Note 5: This setup time ensures the register will see stable data from the shift-register outputs. The clocks may be connected together in which case the stor-
age register state will be one clock pulse behind the shift register.

AC Electrical Characteristics
VCC = 2.0−6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
TA = 25°C TA = −40 to 85°C TA = −55 to 125°C
Symbol Parameter Conditions VCC Units
Typ Guaranteed Limits
fMAX Maximum Operating CL = 50 pF 2.0V 10 6 4.8 4.0 MHz
Frequency 4.5V 45 30 24 20 MHz
6.0V 50 35 28 24 MHz
tPHL, tPLH Maximum Propagation CL = 50 pF 2.0V 58 210 265 315 ns
Delay from SCK to QH CL = 150 pF 2.0V 83 294 367 441 ns
CL = 50 pF 4.5V 14 42 53 63 ns
CL = 150 pF 4.5V 17 58 74 88 ns
CL = 50 pF 6.0V 10 36 45 54 ns
CL = 150 pF 6.0V 14 50 63 76 ns
tPHL, tPLH Maximum Propagation CL = 50 pF 2.0V 70 175 220 265 ns
Delay from RCK to QA thru QH CL = 150 pF 2.0V 105 245 306 368 ns
CL = 50 pF 4.5V 21 35 44 53 ns
CL = 150 pF 4.5V 28 49 61 74 ns
CL = 50 pF 6.0V 18 30 37 45 ns
CL = 150 pF 6.0V 26 42 53 63 ns
tPHL, tPLH Maximum Propagation 2.0V 175 221 261 ns
Delay from SCLR to QH 4.5V 35 44 52 ns
6.0V 30 37 44 ns

www.fairchildsemi.com 4
 MM74HC595
AC Electrical Characteristics (Continued)

TA = 25°C TA = −40 to 85°C TA = −55 to 125°C

Symbol Parameter Conditions VCC Units
Typ Guaranteed Limits
tPZH, tPZL Maximum Output Enable RL = 1 kΩ
from G to QA thru QH CL = 50 pF 2.0V 75 175 220 265 ns
CL = 150 pF 2.0V 100 245 306 368 ns
CL = 50 pF 4.5V 15 35 44 53 ns
CL = 150 pF 4.5V 20 49 61 74 ns
CL = 50 pF 6.0V 13 30 37 45 ns
CL = 150 pF 6.0V 17 42 53 63 ns
tPHZ, tPLZ Maximum Output Disable RL = 1 kΩ 2.0V 75 175 220 265 ns
Time from G to QA thru QH CL = 50 pF 4.5V 15 35 44 53 ns
6.0V 13 30 37 45 ns
tS Minimum Setup Time 2.0V 100 125 150 ns
from SER to SCK 4.5V 20 25 30 ns
6.0V 17 21 25 ns
tR Minimum Removal Time 2.0V 50 63 75 ns
from SCLR to SCK 4.5V 10 13 15 ns
6.0V 9 11 13 ns
tS Minimum Setup Time 2.0V 100 125 150 ns
from SCK to RCK 4.5V 20 25 30 ns
6.0V 17 21 26 ns
tH Minimum Hold Time 2.0V 5 5 5 ns
SER to SCK 4.5V 5 5 5 ns
6.0V 5 5 5 ns
tW Minimum Pulse Width 2.0V 30 80 100 120 ns
of SCK or SCLR 4.5V 9 16 20 24 ns
6.0V 8 14 18 22 ns
tr , tf Maximum Input Rise and 2.0V 1000 1000 1000 ns
Fall Time, Clock 4.5V 500 500 500 ns
6.0V 400 400 400 ns
tTHL, tTLH Maximum Output 2.0V 25 60 75 90 ns
Rise and Fall Time 4.5V 7 12 15 18 ns
QA–QH 6.0V 6 10 13 15 ns
tTHL, tTLH Maximum Output 2.0V 75 95 110 ns
Rise & Fall Time 4.5V 15 19 22 ns
QH 6.0V 13 16 19 ns
CPD Power Dissipation G = VCC 90 pF
Capacitance, Outputs G = GND 150 pF
Enabled (Note 6)
CIN Maximum Input 5 10 10 10 pF
Capacitance
COUT Maximum Output 15 20 20 20 pF
Capacitance
Note 6: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption,
IS = CPD VCC f + ICC.

5 www.fairchildsemi.com
MM74HC595
Timing Diagram

www.fairchildsemi.com 6
 MM74HC595
Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M16B

7 www.fairchildsemi.com
MM74HC595
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D

www.fairchildsemi.com 8
 MM74HC595
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16

9 www.fairchildsemi.com
MM74HC595 8-Bit Shift Registers with Output Latches
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual--Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N16E

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support
which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea-
body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support
to perform when properly used in accordance with device or system, or to affect its safety or effectiveness.
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the www.fairchildsemi.com
user.

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.