ElektorPost Project No.

30

Mini Noise Generator

Check that frequency response

A simple audio-band noise gener- By

Wilfried Wtzig
ator is a useful tool for testing
(Germany)
amplifiers. In days gone by,
you would use a diode or the
base-emitter junction of a transis-
tor as the (analog) noise source, in the age
of the binary digit there are other solutions

To make a noise generator using digital tech- A noise generator based on this principle was
nology you can start with a long shift register described in an old Elektor article [2]. It used
made up of a chain of D-type flip flops. The a 16-bit long shift register with XNOR gates
logic value of the last flip flop in the reg- to generate the feedback signal using a poly-
ister together with some selected flip flops nomial of 1+V2+V3+V5+V16. Testing this
along the chain (taps) are then logically gated design it was apparent that the noise charac-
together to produce the (feedback) signal teristics across the audio spectrum were not
which forms the input to the shift register. very linear; with audible rumbles and chirps.
Figure1 shows the basic configuration of a In an effort to improve the characteristics two
typical Linear Feedback Shift Register (LFSR) versions of the LFSR named after the Ital-
using XOR logic gates to generate the feed- ian mathematician Leonardo Fibonacci were
back logic signal. implemented.

A Linear Feedback Shift Register 16 bit Fibonacci-LFSR : feedback 1 + V11

The registers output waveform looks like a + V13 + V14 + V16 with XOR and
random sequence of ones and zeroes, but in
truth (since there is no truly chaotic behav- 24 bit Fibonacci-LFSR: feedback 1 + V20
ior like the noise generated in a base-emit- + V21 + V23 + V24 with XOR.
ter junction) the sequence is deterministic.
The bit sequence generator also has uses as Both of these examples were shown to gen-
a pseudo-random number generator or for erate a consistently flat output across the
encrypted stream ciphers. The bit sequence audio spectrum.
is made up of many discrete frequencies
which extend to one half of the clock fre- A Controller and Filter
quency. When a chain of n=8 cells is used The LFSR can of course be built using a ded-
with a primitive feedback polynomial (here icated shift register IC such as a 74HCT174
1+V8+V6+V5+V4), it generates a total of plus some additional logic [2] but all those
28-1 different frequencies. A large value of n naked digital gates look so 20th century.
is important for noise generator applications Surely a more elegant and contemporary solu-
because it creates a flat noise characteristic tion is to use a small 8-pin Atmel ATtiny13
across the spectrum. More information on the microcontroller and emulate the feedback
theory and math behind this technique can register function in an (Assembler) program
be found at [1]. (Figure2). Jumper JP3 shown on the cir-

elektor post | Project No. 30 | 1

ElektorPost Project No. 30

+5V

R1 C3 R5 JP1 1
C1
10k

10k
IC1 +5V
820p C4
8 ATTINY13-20PU 100n
VCC
R2 R3 100n
5 3
PB0/PCINT0/AIN0/OC0A/MOSI 10k 10k R4 8
6 1 5
PB1/PCINT1/AIN1/OC0B/INT0/MISO
7 2
IC2a 47k
7
C5
PB2/PCINT2/SCK/ADC1/T0
2
IC2b
6
PB3/PCINT3/CLKI/ADC3 47u
3 16V
PB4/PCINT4/ADC2 4 JP4 1
1 PROGRAM
PB5/PCINT5/RESET/ADC0/DW +5V
JP3 1 1 2 OUT
GND 3 4
5 6
C2 IC2 = TS912 R6 R7
4

10k

1k
820p
JP2
130312-11

cuit connects to the controller pin PB4 and IC2A is configured as a simple Sallen-Key low- Figure 1.
allows the register length to be changed from pass filter with a cut off frequency of 19.4kHz The noise generator uses an
16 memory cells (jumper fitted) to 24 cells [4], all frequency components above the audio ATtiny to produce the LFSR
(jumper removed). band (including the 100KHz clock frequency) function in software.
will be attenuated by its 12dB/Octave char-
The microcontroller is clocked at 9.6MHz by acteristic. The signal is then simply buffered
its built-in clock generator and produces a by IC2B and because the opamp is powered
new value in the LFSR every 10s (100kHz). from a single +5V supply any DC compo-
The distance between the generated frequen- nent in the signal is decoupled by C5 and
cies is either 100kHz/216115.5Hz or the resulting output signal taken to JP4. IC2
100kHz/22410.006Hz, the upper fre- is a dual opamp type TS912 with rail-to-rail
quency limit is fClk/2=50kHz. The output capability. The complete circuit is so small it
signal from V1 (the shift register output) is fits neatly onto a small square of breadboard.
at pin PD0 of the ATtiny microcontroller. In (130312)
24-cell mode the sequence takes almost 3
minutes!
Web Links
The assembler program for this project can be [1] http://en.wikipedia.org/wiki/
downloaded from [3]. The Atmel AVR-Studio6 Linear_feedback_shift_register
was used for program development. Fuses
[2] Noise Generator, Elektor December 2002,
should be set to HIGH 0xFF and LOW 0x7A.
ref. no. 014118
The circuit diagram shows the connection of Figure 2.
a standard-layout ISP connector for program- [3] www.elektor-magazine.com/130312
The 8-memory element
ming but if a ready-programmed controller is [4] https://en.wikipedia.org/wiki/ Fibonacci linear feedback
used [3] J2 can be left out. Sallen%E2%80%93Key_topology shift register.

D Q D Q D Q D Q D Q D Q D Q D Q Y
1 2 3 4 5 6 7 8

CLK
X8 + X6 + X5 + X4 + 1 130312-12

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