MSP 430 FR 5969
MSP 430 FR 5969
MSP 430 FR 5969
1.1
1
Features
Embedded Microcontroller Accessible Bit-, Byte-, and Word-Wise (in Pairs)
16-Bit RISC Architecture up to 16MHz Clock Edge-Selectable Wake From LPM on All Ports
Wide Supply Voltage Range Programmable Pullup and Pulldown on All Ports
(1.8 V to 3.6 V) (1) Code Security and Encryption
Optimized Ultra-Low-Power Modes 128-Bit or 256-Bit AES Security Encryption and
Active Mode: Approximately 100 A/MHz Decryption Coprocessor
Standby (LPM3 With VLO): 0.4 A (Typical) Random Number Seed for Random Number
Real-Time Clock (LPM3.5): 0.25 A (Typical) (2) Generation Algorithms
Shutdown (LPM4.5): 0.02 A (Typical) Enhanced Serial Communication
Ultra-Low-Power Ferroelectric RAM (FRAM) eUSCI_A0 and eUSCI_A1 Support
Up to 64KB of Nonvolatile Memory UART With Automatic Baud-Rate Detection
Ultra-Low-Power Writes IrDA Encode and Decode
Fast Write at 125 ns Per Word (64KB in 4 ms) SPI
Unified Memory = Program + Data + Storage in eUSCI_B0 Supports
One Single Space I2C With Multiple Slave Addressing
1015 Write Cycle Endurance SPI
Radiation Resistant and Nonmagnetic Hardware UART and I2C Bootloader (BSL)
Intelligent Digital Peripherals Flexible Clock System
32-Bit Hardware Multiplier (MPY) Fixed-Frequency DCO With 10 Selectable
3-Channel Internal DMA Factory-Trimmed Frequencies
Real-Time Clock (RTC) With Calendar and Low-Power Low-Frequency Internal Clock
Alarm Functions Source (VLO)
Five 16-Bit Timers With up to Seven 32-kHz Crystals (LFXT)
Capture/Compare Registers Each High-Frequency Crystals (HFXT)
16-Bit Cyclic Redundancy Checker (CRC) Development Tools and Software
High-Performance Analog Free Professional Development Environments
16-Channel Analog Comparator With EnergyTrace++ Technology
12-Bit Analog-to-Digital Converter (ADC) Development Kit (MSP-TS430RGZ48C)
With Internal Reference and Sample-and-Hold Family Members
and up to 16 External Input Channels Device Comparison Summarizes the Available
Multifunction Input/Output Ports Device Variants and Package Types
All Pins Support Capacitive Touch Capability For Complete Module Descriptions, See the
With No Need for External Components MSP430FR58xx, MSP430FR59xx,
(1) Minimum supply voltage is restricted by SVS levels. MSP430FR68xx, and MSP430FR69xx Family
(2) RTC is clocked by a 3.7-pF crystal. User's Guide
1.2 Applications
Metering Sensor Management
Energy Harvested Sensor Nodes Data Logging
Wearable Electronics
1.3 Description
The MSP430 ultra-low-power (ULP) FRAM platform combines uniquely embedded FRAM and a holistic
ultra-low-power system architecture, allowing innovators to increase performance at lowered energy
budgets. FRAM technology combines the speed, flexibility, and endurance of SRAM with the stability and
reliability of flash at much lower power.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704F OCTOBER 2012 REVISED MARCH 2017 www.ti.com
The MSP430 ULP FRAM portfolio consists of a diverse set of devices featuring FRAM, the ULP 16-bit
MSP430 CPU, and intelligent peripherals targeted for various applications. The ULP architecture
showcases seven low-power modes, optimized to achieve extended battery life in energy-challenged
applications.
ADC12_B
I/O Ports I/O Ports I/O Port
MCLK ACLK Comp_E (up to 16 REF_A P1, P2 P3, P4 PJ
Clock standard 2x8 I/Os 2x8 I/Os 1x8 I/Os
System (up to 16 inputs, Voltage
SMCLK inputs) up to 8 Reference PA PB
differential
DMA inputs)
1x16 I/Os 1x16 I/Os
Controller
3 Channel
MAB
Bus
Control MDB
Logic
CPUXV2
incl. 16
Registers MPU TA2
IP Encap Power AES256
TA3
FRAM RAM Mgmt
Security
CRC16 MPY32 Watchdog Timer_A
LDO Encryption,
EEM 64KB 2KB 2 CC
SVS Decryption
(S: 3 + 1) 48KB 1KB Registers
Brownout (128, 256)
32KB (int. only)
EnergyTrace++
MDB
JTAG
Interface MAB
Spy-Bi-Wire
TB0 TA0 TA1
eUSCI_A0 eUSCI_B0
eUSCI_A1
2
Timer_B Timer_A Timer_A (I C, RTC_B
7 CC 3 CC 3 CC (UART, SPI)
Registers Registers Registers IrDA,
(int, ext) (int, ext) (int, ext) SPI)
LPM3.5 Domain
Table of Contents
1 Device Overview ......................................... 1 5.13 Emulation and Debug ............................... 52
1.1 Features .............................................. 1 6 Detailed Description ................................... 53
1.2 Applications ........................................... 1 6.1 Overview ............................................ 53
1.3 Description ............................................ 1 6.2 CPU ................................................. 53
1.4 Functional Block Diagram ............................ 2 6.3 Operating Modes .................................... 54
2 Revision History ......................................... 4 6.4 Interrupt Vector Table and Signatures .............. 57
3 Device Comparison ..................................... 5 6.5 Memory Organization ............................... 60
3.1 Related Products ..................................... 6 6.6 Bootloader (BSL) .................................... 60
4 Terminal Configuration and Functions .............. 7 6.7 JTAG Operation ..................................... 61
4.1 Pin Diagrams ......................................... 7 6.8 FRAM................................................ 62
4.2 Signal Descriptions .................................. 12 6.9 Memory Protection Unit Including IP Encapsulation 62
4.3 .....................................
Pin Multiplexing 16 6.10 Peripherals .......................................... 63
4.4 Connection of Unused Pins ......................... 16 6.11 Input/Output Diagrams ............................. 84
5 Specifications ........................................... 17 6.12 Device Descriptor (TLV) ........................... 112
5.1 Absolute Maximum Ratings ......................... 17 6.13 Identification........................................ 114
5.2 ESD Ratings ........................................ 17 7 Applications, Implementation, and Layout ...... 115
5.3 Recommended Operating Conditions ............... 17 7.1 Device Connection and Layout Fundamentals .... 115
5.4 Active Mode Supply Current Into VCC Excluding 7.2 Peripheral- and Interface-Specific Design
External Current .................................... 18 Information ......................................... 119
5.5 Typical Characteristics Active Mode Supply 8 Device and Documentation Support .............. 121
Currents ............................................. 19 8.1 Getting Started and Next Steps ................... 121
5.6 Low-Power Mode (LPM0, LPM1) Supply Currents
8.2 Device Nomenclature .............................. 121
Into VCC Excluding External Current ................ 19
8.3 Tools and Software ................................ 123
5.7 Low-Power Mode (LPM2, LPM3, LPM4) Supply
Currents (Into VCC) Excluding External Current .... 20 8.4 Documentation Support ............................ 125
5.8 Low-Power Mode (LPM3.5, LPM4.5) Supply 8.5 Related Links ...................................... 126
Currents (Into VCC) Excluding External Current .... 21 8.6 Community Resources............................. 127
5.9 Typical Characteristics, Low-Power Mode Supply 8.7 Trademarks ........................................ 127
Currents ............................................. 22
8.8 Electrostatic Discharge Caution ................... 127
5.10 Typical Characteristics, Current Consumption per
8.9 Export Control Notice .............................. 127
Module .............................................. 23
8.10 Glossary............................................ 127
5.11 Thermal Resistance Characteristics ................ 23
5.12 Timing and Switching Characteristics ............... 24
9 Mechanical, Packaging, and Orderable
Information ............................................. 128
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Removed "at Rates up to 10 Mbps" from SPI features list item ................................................................ 1
Added Section 3.1, Related Products ............................................................................................. 6
Updated the requirements for the capacitor on the RST/NMI pin in Table 4-2, Connection of Unused Pins ........... 16
Added second row to tSample parameter in Table 5-23, 12-Bit ADC, Timing Parameters .................................. 45
Removed ADC12DIV from the formula for the tCONVERT TYP time, because ADC12CLK is after division............... 45
Added "RS < 10 k" to the note that starts "Approximately 10 Tau () are needed..." on Table 5-23, 12-Bit ADC,
Timing Parameters .................................................................................................................. 45
Changed the note that starts "Tools that access the Spy-Bi-Wire and BSL interfaces..." ................................. 52
Changed Updated Section 6.3, Operating Modes, and its subsections...................................................... 54
Changed description in Section 6.4, Interrupt Vector Table and Signatures ................................................ 57
Added Figure 6-1 .................................................................................................................... 57
Changed Table 6-4, Interrupt Sources, Flags, and Vectors: removed Reserved vectors and moved Signatures to
Table 6-5 ............................................................................................................................. 58
Added Table 6-5, Signatures, and moved contents from Table 6-4 .......................................................... 59
Throughout document, changed "bootstrap loader" to "bootloader".......................................................... 60
Corrected spelling of NMIIFG in Table 6-11, System Module Interrupt Vector Registers ................................. 66
Added AESACTL1 register in Table 6-48, AES Accelerator Registers ...................................................... 83
Corrected value in "x" column for PJ.7/HFXOUT row......................................................................... 109
Changed the requirements for the capacitor on the RST/NMI pin in Section 7.1.4, Reset .............................. 118
Replaced former section Development Tools Support with Section 8.3, Tools and Software ........................... 123
Updated Section 8.4, Documentation Support ................................................................................. 125
3 Device Comparison
Table 3-1 summarizes the available family members.
14 ext, 2 int
33 40 RHA
DCO ch. 3, 3 (7)
MSP430FR5949 64 2 16 ch. 7 2 1 yes UART
LFXT 12 ext, 2, 2 (8)
31 38 DA
2 int ch.
14 ext,
33 40 RHA
DCO 2 int ch. 3, 3 (7)
MSP430FR5948 48 2 16 ch. 7 2 1 yes UART
LFXT 12 ext, 2, 2 (8)
31 38 DA
2 int ch.
14 ext,
33 40 RHA
DCO 2 int ch. 3, 3 (7)
MSP430FR5947 32 1 16 ch. 7 2 1 yes UART
LFXT 12 ext, 2, 2 (8)
31 38 DA
2 int ch.
(7)
DCO 14 ext, 3, 3
MSP430FR59471 32 1 16 ch. 7 2 1 yes I2C 33 40 RHA
LFXT 2 int ch. 2, 2 (8)
14 ext,
33 40 RHA
DCO 2 int ch. 3, 3 (7)
MSP430FR5959 64 2 16 ch. 7 2 1 yes UART
HFXT 12 ext, 2, 2 (8)
31 38 DA
2 int ch.
14 ext,
33 40 RHA
DCO 2 int ch. 3, 3 (7)
MSP430FR5958 48 2 16 ch. 7 2 1 yes UART
HFXT 12 ext, 2, 2 (8)
31 38 DA
2 int ch.
14 ext,
33 40 RHA
DCO 2 int ch. 3, 3 (7)
MSP430FR5957 32 1 16 ch. 7 2 1 yes UART
HFXT 12 ext, 2, 2 (8)
31 38 DA
2 int ch.
(1) For the most current device, package, and ordering information for all available devices, see the Package Option Addendum in
Section 9, or see the TI website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 capture/compare registers and PWM output generators and the second instantiation having 5 capture/compare
registers and PWM output generators, respectively.
(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 capture/compare registers and PWM output generators and the second instantiation having 5 capture/compare
registers and PWM output generators, respectively.
(5) eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.
(6) eUSCI_B supports I2C with multiple slave addresses, and SPI.
(7) Timers TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.
(8) Timers TA2 and TA3 provide only internal capture/compare inputs and only internal PWM outputs (if any).
P2.3/TA0.0/UCA1STE/A6/C10
P2.4/TA1.0/UCA1CLK/A7/C11
PJ.7/HFXOUT
PJ.5/LFXOUT
PJ.6/HFXIN
PJ.4/LFXIN
DVCC
AVCC
AVSS
AVSS
AVSS
P2.7
48 47 46 45 44 43 42 41 40 39 38 37
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF- 1 36 DVSS
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+ 2 35 P4.6
P1.2/TA1.1/TA0CLK/COUT/A2/C2 3 34 P4.5
P3.0/A12/C12 4 33 P4.4/TB0.5
P3.1/A13/C13 5 32 P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
P3.2/A14/C14 6 31 P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
P3.3/A15/C15 7 30 P3.7/TB0.6
P4.7 8 29 P3.6/TB0.5
P1.3/TA1.2/UCB0STE/A3/C3 9 28 P3.5/TB0.4/COUT
P1.4/TB0.1/UCA0STE/A4/C4 10 27 P3.4/TB0.3/SMCLK
P1.5/TB0.2/UCA0CLK/A5/C5 11 26 P2.2/TB0.2/UCB0CLK
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6 12 25 P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0
13 14 15 16 17 18 19 20 21 22 23 24
PJ.1/TDI/TCLK/MCLK/SRSCG0/C7
PJ.2/TMS/ACLK/SROSCOFF/C8
PJ.3/TCK/SRCPUOFF/C9
P4.0/A8
P4.1/A9
P4.2/A10
P4.3/A11
P2.5/TB0.0/UCA1TXD/UCA1SIMO
RST/NMI/SBWTDIO
P2.6/TB0.1/UCA1RXD/UCA1SOMI
TEST/SBWTCK
P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
Figure 4-1. 48-Pin RGZ Package (Top View) MSP430FR596x and MSP430FR596x1
Figure 4-2 shows the 40-pin RHA package for the MSP430FR594x and MSP430FR594x1 MCUs (LFXT
only).
P2.3/TA0.0/UCA1STE/A6/C10
P2.4/TA1.0/UCA1CLK/A7/C11
PJ.5/LFXOUT
PJ.4/LFXIN
DVCC
DVSS
AVCC
AVSS
AVSS
P2.7
40 39 38 37 36 35 34 33 32 31
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF- 1 30 P4.4/TB0.5
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+ 2 29 P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
P1.2/TA1.1/TA0CLK/COUT/A2/C2 3 28 P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
P3.0/A12/C12 4 27 P3.7/TB0.6
P3.1/A13/C13 5 26 P3.6/TB0.5
P3.2/A14/C14 6 25 P3.5/TB0.4/COUT
P3.3/A15/C15 7 24 P3.4/TB0.3/SMCLK
P1.3/TA1.2/UCB0STE/A3/C3 8 23 P2.2/TB0.2/UCB0CLK
P1.4/TB0.1/UCA0STE/A4/C4 9 22 P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0
P1.5/TB0.2/UCA0CLK/A5/C5 10 21 P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
11 12 13 14 15 16 17 18 19 20
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6
PJ.1/TDI/TCLK/MCLK/SRSCG0/C7
PJ.2/TMS/ACLK/SROSCOFF/C8
PJ.3/TCK/SRCPUOFF/C9
P4.0/A8
P4.1/A9
P2.5/TB0.0/UCA1TXD/UCA1SIMO
TEST/SBWTCK
RST/NMI/SBWTDIO
P2.6/TB0.1/UCA1RXD/UCA1SOMI
Figure 4-2. 40-Pin RHA Package (Top View) MSP430FR594x and MSP430FR594x1
Figure 4-3 shows the 38-pin DA package for the MSP430FR594x MCUs (LFXT only).
PJ.4/LFXIN 1 38 AVSS
PJ.5/LFXOUT 2 37 P2.4/TA1.0/UCA1CLK/A7/C11
AVSS 3 36 P2.3/TA0.0/UCA1STE/A6/C10
AVCC 4 35 P2.7
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF- 5 34 DVCC
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+ 6 33 DVSS
P1.2/TA1.1/TA0CLK/COUT/A2/C2 7 32 P4.4/TB0.5
P3.0/A12/C12 8 31 P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
P3.1/A13/C13 9 30 P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
P3.2/A14/C14 10 29 P3.7/TB0.6
P3.3/A15/C15 11 28 P3.6/TB0.5
P1.3/TA1.2/UCB0STE/A3/C3 12 27 P3.5/TB0.4/COUT
P1.4/TB0.1/UCA0STE/A4/C4 13 26 P3.4/TB0.3/SMCLK
P1.5/TB0.2/UCA0CLK/A5/C5 14 25 P2.2/TB0.2/UCB0CLK
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6 15 24 P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0
PJ.1/TDI/TCLK/MCLK/SRSCG0/C7 16 23 P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
PJ.2/TMS/ACLK/SROSCOFF/C8 17 22 RST/NMI/SBWTDIO
PJ.3/TCK/SRCPUOFF/C9 18 21 TEST/SBWTCK
P2.5/TB0.0/UCA1TXD/UCA1SIMO 19 20 P2.6/TB0.1/UCA1RXD/UCA1SOMI
Figure 4-4 shows the 40-pin RHA package for the MSP430FR595x MCUs (HFXT only).
P2.3/TA0.0/UCA1STE/A6/C10
P2.4/TA1.0/UCA1CLK/A7/C11
PJ.7/HFXOUT
PJ.6/HFXIN
DVCC
DVSS
AVCC
AVSS
AVSS
P2.7
40 39 38 37 36 35 34 33 32 31
P1.0/TA0.1/DMAE0/A0/C0/VREF-/VeREF- 1 30 P4.4/TB0.5
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+ 2 29 P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
P1.2/TA1.1/TA0CLK/COUT/A2/C2 3 28 P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
P3.0/A12/C12 4 27 P3.7/TB0.6
P3.1/A13/C13 5 26 P3.6/TB0.5
P3.2/A14/C14 6 25 P3.5/TB0.4/COUT
P3.3/A15/C15 7 24 P3.4/TB0.3/SMCLK
P1.3/TA1.2/UCB0STE/A3/C3 8 23 P2.2/TB0.2/UCB0CLK
P1.4/TB0.1/UCA0STE/A4/C4 9 22 P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0
P1.5/TB0.2/UCA0CLK/A5/C5 10 21 P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
11 12 13 14 15 16 17 18 19 20
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6
PJ.1/TDI/TCLK/MCLK/SRSCG0/C7
PJ.2/TMS/ACLK/SROSCOFF/C8
PJ.3/TCK/SRCPUOFF/C9
P4.0/A8
P4.1/A9
P2.5/TB0.0/UCA1TXD/UCA1SIMO
P2.6/TB0.1/UCA1RXD/UCA1SOMI
TEST/SBWTCK
RST/NMI/SBWTDIO
Figure 4-5 shows the 38-pin DA package for the MSP430FR595x MCUs (HFXT only).
PJ.6/HFXIN 1 38 AVSS
PJ.7/HFXOUT 2 37 P2.4/TA1.0/UCA1CLK/A7/C11
AVSS 3 36 P2.3/TA0.0/UCA1STE/A6/C10
AVCC 4 35 P2.7
P1.0/TA0.1/DMAE0/A0/C0/VREF-/VeREF- 5 34 DVCC
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+ 6 33 DVSS
P1.2/TA1.1/TA0CLK/COUT/A2/C2 7 32 P4.4/TB0.5
P3.0/A12/C12 8 31 P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
P3.1/A13/C13 9 30 P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
P3.2/A14/C14 10 29 P3.7/TB0.6
P3.3/A15/C15 11 28 P3.6/TB0.5
P1.3/TA1.2/UCB0STE/A3/C3 12 27 P3.5/TB0.4/COUT
P1.4/TB0.1/UCA0STE/A4/C4 13 26 P3.4/TB0.3/SMCLK
P1.5/TB0.2/UCA0CLK/A5/C5 14 25 P2.2/TB0.2/UCB0CLK
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6 15 24 P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0
PJ.1/TDI/TCLK/MCLK/SRSCG0/C7 16 23 P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
PJ.2/TMS/ACLK/SROSCOFF/C8 17 22 RST/NMI/SBWTDIO
PJ.3/TCK/SRCPUOFF/C9 18 21 TEST/SBWTCK
P2.5/TB0.0/UCA1TXD/UCA1SIMO 19 20 P2.6/TB0.1/UCA1RXD/UCA1SOMI
(1) Any unused pin with a secondary function that is shared with general-purpose I/O should follow the
Px.0 to Px.7 unused pin connection guidelines.
(2) The pulldown capacitor should not exceed 2.2 nF when using devices in Spy-Bi-Wire mode or in 4-
wire JTAG mode with TI tools like FET interfaces or GANG programmers. If JTAG or Spy-Bi-Wire
access is not needed, up to a 10-nF pulldown capacitor may be used.
5 Specifications
5.4 Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1) (2)
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Characterized with program executing typical data processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency, except for 12 MHz. For 12 MHz, fDCO= 24 MHz and
fMCLK = fSMCLK = fDCO/2.
At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency
(fMCLK,eff) decreases. The effective MCLK frequency also depends on the cache hit ratio. SMCLK is not affected by the number of wait
states or the cache hit ratio.
The following equation can be used to compute fMCLK,eff:
fMCLK,eff = fMCLK / [wait states (1 cache hit ratio) + 1]
For example, with 1 wait state and 75% cache hit ratio, fMCKL,eff = fMCLK / [1 (1 0.75) + 1] = fMCLK / 1.25.
(3) Represents typical program execution. Program and data reside entirely in FRAM. All execution is from FRAM.
(4) Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit
ratio represents number cache accesses divided by the total number of FRAM accesses. For example, a 75% ratio implies three of
every four accesses is from cache, and the remaining are FRAM accesses.
(5) See Figure 5-1 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best
linear fit using the typical data from Section 5.4.
(6) Program and data reside entirely in RAM. All execution is from RAM.
(7) Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
1500
1000
500
0
0 1 2 3 4 5 6 7 8 9
MCLK Frequency (MHz)
C001
NOTE: I(AM, cache hit ratio): Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with
cache hit-to-miss ratio as specified. Cache hit ratio represents number cache accesses divided by the total number of
FRAM accesses. For example, a 75% ratio implies three of every four accesses is from cache, and the remaining are
FRAM accesses.
NOTE: I(AM, RAMonly): Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
Figure 5-1. Typical Active Mode Supply Currents vs MCLK frequency, No Wait States
5.6 Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1) (2)
FREQUENCY (fSMCLK)
PARAMETER VCC 1 MHz 4 MHz 8 MHz 12 MHz 16 MHz UNIT
TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX
2.2 V 70 95 150 250 215
ILPM0 A
3.0 V 80 115 105 160 260 225 260
2.2 V 35 60 115 215 180
ILPM1 A
3.0 V 35 60 60 115 215 180 205
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Current for watchdog timer clocked by SMCLK included.
fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO at specified frequency, except for 12 MHz. For 12 MHz, fDCO = 24 MHz and fSMCLK =
fDCO / 2.
5.7 Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External
Current
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
40C 25C 60C 85C
PARAMETER VCC UNIT
TYP MAX TYP MAX TYP MAX TYP MAX
Low-power mode 2, 12-pF 2.2 V 0.5 0.9 2.2 6.1
ILPM2,XT12 A
crystal (2) (3) (4) 3.0 V 0.5 0.9 1.8 2.2 6.1 17
Low-power mode 2, 3.7-pF 2.2 V 0.5 0.9 2.2 6.0
ILPM2,XT3.7 A
cyrstal (2) (5) (4) 3.0 V 0.5 0.9 2.2 6.0
Low-power mode 2, VLO, 2.2 V 0.3 0.7 1.9 5.8
ILPM2,VLO A
includes SVS (6) 3.0 V 0.3 0.7 1.6 1.9 5.8 16.7
Low-power mode 3, 12-pF 2.2 V 0.5 0.6 0.9 1.85
ILPM3,XT12 crystal, excludes SVS (2) (3) A
(7) 3.0 V 0.5 0.6 0.9 0.9 1.85 4.9
Low-power mode 3, 3.7-pF 2.2 V 0.4 0.5 0.8 1.7
cyrstal, excludes SVS (2) (5)
ILPM3,XT3.7 (8) A
3.0 V 0.4 0.5 0.8 1.7
(also see Figure 5-2)
Low-power mode 3, 2.2 V 0.3 0.4 0.7 1.6
ILPM3,VLO A
VLO, excludes SVS (9) 3.0 V 0.3 0.4 0.7 0.7 1.6 4.7
Low-power mode 4, includes 2.2 V 0.4 0.5 0.8 1.7
ILPM4,SVS SVS (10) A
(also see Figure 5-3) 3.0 V 0.4 0.5 0.8 0.8 1.7 4.8
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Not applicable for devices with HF crystal oscillator only.
(3) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5-pF load.
(4) Low-power mode 2, crystal oscillator test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 are included. Current for brownout and SVS are included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(5) Characterized with a SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are chosen
to closely match the required 3.7-pF load.
(6) Low-power mode 2, VLO test conditions:
Current for watchdog timer clocked by ACLK is included. RTC disabled (RTCHOLD = 1). Current for brownout and SVS are included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
(7) Low-power mode 3, 12-pF crystal, excludes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 are included. Current for brownout is included. SVS disabled
(SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(8) Low-power mode 3, 3.7-pF crystal, excludes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 are included. Current for brownout is included. SVS disabled
(SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(9) Low-power mode 3, VLO, excludes SVS test conditions:
Current for watchdog timer clocked by ACLK is included. RTC disabled (RTCHOLD = 1). Current for brownout is included. SVS is
disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
(10) Low-power mode 4, includes SVS test conditions:
Current for brownout and SVS are included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
(11) Low-power mode 4, excludes SVS test conditions:
Current for brownout is included. SVS is disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
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MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
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www.ti.com SLAS704F OCTOBER 2012 REVISED MARCH 2017
Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External
Current (continued)
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
40C 25C 60C 85C
PARAMETER VCC UNIT
TYP MAX TYP MAX TYP MAX TYP MAX
Additional idle current if one
or more modules from Group
IIDLE,GroupA 3.0V 0.02 0.33 1.3 A
A (see Table 6-3) are
activated in LPM3 or LPM4.
Additional idle current if one
or more modules from Group
IIDLE,GroupB 3.0V 0.015 0.25 1.0 A
B (see Table 6-3) are
activated in LPM3 or LPM4
5.8 Low-Power Mode (LPM3.5, LPM4.5) Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
40C 25C 60C 85C
PARAMETER VCC UNIT
TYP MAX TYP MAX TYP MAX TYP MAX
Low-power mode 3.5, 12-pF 2.2 V 0.4 0.45 0.5 0.7
ILPM3.5,XT12 A
crystal, includes SVS (2) (3) (4) 3.0 V 0.4 0.45 0.7 0.5 0.7 1.2
Low-power mode 3.5, 3.7-pF 2.2 V 0.2 0.25 0.3 0.45
ILPM3.5,XT3.7 cyrstal, excludes SVS (2) (5) (6) A
(also see Figure 5-4) 3.0 V 0.2 0.25 0.3 0.5
Low-power mode 4.5, 2.2 V 0.2 0.2 0.2 0.3
ILPM4.5,SVS includes SVS (7) A
(also see Figure 5-5) 3.0 V 0.2 0.2 0.4 0.2 0.3 0.55
Low-power mode 4.5, 2.2 V 0.02 0.02 0.02 0.08
ILPM4.5 excludes SVS (8) A
(also see Figure 5-5) 3.0 V 0.02 0.02 0.02 0.08 0.35
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Not applicable for devices with HF crystal oscillator only.
(3) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5-pF load.
(4) Low-power mode 3.5, 12-pF crystal, includes SVS test conditions:
Current for RTC clocked by XT1 is included. Current for brownout and SVS are included (SVSHE = 1). Core regulator is disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(5) Characterized with a SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are chosen
to closely match the required 3.7-pF load.
(6) Low-power mode 3.5, 3.7-pF crystal, excludes SVS test conditions:
Current for RTC clocked by XT1 is included. Current for brownout is included. SVS is disabled (SVSHE = 0). Core regulator isdisabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(7) Low-power mode 4.5, includes SVS test conditions:
Current for brownout and SVS are included (SVSHE = 1). Core regulator is disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
(8) Low-power mode 4.5, excludes SVS test conditions:
Current for brownout is included. SVS is disabled (SVSHE = 0). Core regulator is disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
2 2
3.0 V, SVS on 3.0 V, SVS on
1.8 2.2 V, SVS on 1.8 2.2 V, SVS on
3.0 V, SVS off
1.6 2.2 V, SVS off 1.6
LPM3 Supply Current (A)
1.2 1.2
1 1
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0 0
-50.00 0.00 50.00 100.00 -50.00 0.00 50.00 100.00
Temperature (C) Temperature (C)
C003 C001
Figure 5-2. LPM3,XT3.7 Supply Current vs Temperature Figure 5-3. LPM4,SVS Supply Current vs Temperature
0.5 0.5
3.0 V, SVS off 3.0 V, SVS on
2.2 V, SVS on
2.2 V, SVS off
3.0 V, SVS off
0.4 0.4 2.2 V, SVS off
LPM4.5 Supply Current (A)
LPM3.5 Supply Current (A)
0.3 0.3
0.2 0.2
0.1 0.1
0 0
-50.00 0.00 50.00 100.00 -50.00 0.00 50.00 100.00
Temperature (C) Temperature (C)
C003 C004
Figure 5-4. LPM3.5,XT3.7 Supply Current vs Temperature Figure 5-5. LPM4.5 Supply Current vs Temperature
1.5
Brownout Power-Down Level (V)
Typical
1
Process-Temperature Corner Case 2
MIN Limit
0.5
0
1 10 100 1000 10000 100000
Supply Voltage Power-Down Slope (V/s)
(1) To improve EMI on the LFXT oscillator, observe the following guidelines.
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins LFXIN and LFXOUT.
Avoid running PCB traces underneath or adjacent to the LFXIN and LFXOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator LFXIN and LFXOUT pins.
If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
For LFXTDRIVE = {0}, CL,eff = 3.7 pF.
For LFXTDRIVE = {1}, CL,eff = 6 pF
For LFXTDRIVE = {2}, 6 pF CL,eff 9 pF
For LFXTDRIVE = {3}, 9 pF CL,eff 12.5 pF
(5) This represents all the parasitic capacitance present at the LFXIN and LFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN COUT / (CIN + COUT), where CIN and COUT are the
total capacitance at the LFXIN and LFXOUT terminals, respectively.
(6) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF. The PCB adds
additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance
of the selected crystal is met.
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MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
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(1) To improve EMI on the HFXT oscillator, observe the following guidelines.
Keep the traces between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins HFXIN and HFXOUT.
Avoid running PCB traces underneath or adjacent to the HFXIN and HFXOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator HFXIN and HFXOUT pins.
If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) HFFREQ = {0} is not supported for HFXT crystal mode of operation.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) When HFXTBYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCHFXT, SW.
Copyright 20122017, Texas Instruments Incorporated Specifications 27
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MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471
MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704F OCTOBER 2012 REVISED MARCH 2017 www.ti.com
Integrated load
capacitance at
CHFXOUT 2 pF
HFXOUT
terminaI (6) (7)
Oscillator fault
fFault,HFXT 0 800 kHz
frequency (8) (9)
(5) Includes start-up counter of 1024 clock cycles.
(6) This represents all the parasitic capacitance present at the HFXIN and HFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN COUT / (CIN + COUT), where CIN and COUT are the
total capacitance at the HFXIN and HFXOUT terminals, respectively.
(7) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF. The PCB adds
additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance
of the selected crystal is met.
(8) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX might set the flag. A static
condition or stuck at fault condition set the flag.
(9) Measured with logic-level input frequency but also applies to operation with crystals.
10000.00
LPM0
LPM1
1000.00 LPM2,XT12
Average Wake-up Current (A)
LPM3,XT12
LPM3.5,XT12
100.00
10.00
1.00
0.10
0.001 0.01 0.1 1 10 100 1000 10000 100000
Wake-up Frequency (Hz)
NOTE: The average wakeup current does not include the energy required in active mode; for example, for an interrupt
service routine or to reconfigure the device.
10000.00
LPM0
LPM1
1000.00 LPM2,XT12
Average Wake-up Current (A)
LPM3,XT12
LPM3.5,XT12
100.00
10.00
1.00
0.10
0.001 0.01 0.1 1 10 100 1000 10000 100000
Wake-up Frequency (Hz)
NOTE: The average wakeup current does not include the energy required in active mode; for example, for an interrupt
service routine or to reconfigure the device.
15 30
25C 25C
85C 85C
Low-Level Output Current (mA)
5 10
P1.1 P1.1
0 0
0 0.5 1 1.5 2 0 0.5 1 1.5 2 2.5 3
Low-Level Output Voltage (V) Low-Level Output Voltage (V)
C001 C001
0 0
25C 25C
85C 85C
High-Level Output Current (mA)
High-Level Output Current (mA)
-5 -10
-10 -20
P1.1 P1.1
-15 -30
0 0.5 1 1.5 2 0 0.5 1 1.5 2 2.5 3
High-Level Output Voltage (V) High-Level Output Voltage (V)
C001 C001
Fitted Fitted
25C 25C
100 100
10 100 10 100
External Load Capacitance (pF) (Including Board) External Load Capacitance (pF) (Including Board)
C002 C002
VCC = 2.2 V One output active at a time. VCC = 3.0 V One output active at a time.
Figure 5-13. Typical Oscillation Frequency vs Load Capacitance Figure 5-14. Typical Oscillation Frequency vs Load Capacitance
5.12.7 eUSCI
Table 5-16 lists the supported clock frequencies of the eUSCI in UART mode.
Table 5-17 lists the deglitch times of the eUSCI in UART mode.
Table 5-18 lists the supported clock frequencies of the eUSCI in SPI master mode.
Table 5-19 lists the characteristics of the eUSCI in SPI master mode.
UCMODEx = 01
STE tSTE,LEAD tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tHD,MO
tSTE,ACC tVALID,MO tSTE,DIS
SIMO
UCMODEx = 01
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH tLOW/HIGH
tHD,MI
tSU,MI
SOMI
tHD,MO
tSTE,ACC tVALID,MO tSTE,DIS
SIMO
Table 5-20 lists the characteristics of the eUSCI in SPI slave mode.
UCMODEx = 01
STE tSTE,LEAD tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
SIMO
tHD,SO
tSTE,ACC tVALID,SO tSTE,DIS
SOMI
UCMODEx = 01
STE tSTE,LEAD tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tHD,SO
tSTE,ACC tVALID,SO tSTE,DIS
SOMI
SDA
tSU,DAT tSU,STO
tHD,DAT
5.12.8 ADC
Table 5-22 lists the input requirements of the ADC.
Table 5-22. 12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT
(1)
V(Ax) Analog input voltage range All ADC12 analog input pins Ax 0 AVCC V
fADC12CLK = MODCLK, ADC12ON = 1, 3.0 V 145 185
I(ADC12_B)
Operating supply current into ADC12PWRMD = 0, ADC12DIF = 0,
single- A
AVCC plus DVCC terminals (2) (3)
REFON = 0, ADC12SHTx = 0, 2.2 V 140 180
ended mode
ADC12DIV = 0
fADC12CLK = MODCLK, ADC12ON = 1, 3.0 V 175 225
I(ADC12_B)
Operating supply current into ADC12PWRMD = 0, ADC12DIF = 1,
differential A
AVCC plus DVCC terminals (2) (3)
REFON = 0, ADC12SHTx= 0, 2.2 V 170 220
mode
ADC12DIV = 0
Only one terminal Ax can be selected
CI Input capacitance 2.2 V 10 15 pF
at one time
>2 V 0.5 4 k
RI Input MUX ON resistance 0 V V(Ax) AVCC
<2 V 1 10 k
(1) The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion results.
(2) The internal reference supply current is not included in current consumption parameter I(ADC12_B).
(3) Approximately 60% (typical) of the total current into the AVCC and DVCC terminals is from AVCC.
Table 5-24 lists the linearity parameters of the ADC when using an external reference.
Table 5-24. 12-Bit ADC, Linearity Parameters With External Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Number of no missing code
Resolution 12 bits
output-code bits
Integral linearity error (INL) for
EI 1.2 V VR+ VR AVCC 1.8 LSB
differential input
Integral linearity error (INL) for
EI 1.2 V VR+ VR AVCC 2.2 LSB
single ended inputs
ED Differential linearity error (DNL) 0.99 +1.0 LSB
ADC12VRSEL = 0x2 or 0x4 without TLV calibration,
EO Offset error (2) (3)
TLV calibration data can be used to improve the 0.5 1.5 mV
parameter (4)
With external voltage reference without internal
buffer (ADC12VRSEL = 0x2 or 0x4) without TLV
calibration,
0.8 2.5
TLV calibration data can be used to improve the
EG,ext Gain error parameter (4), LSB
VR+ = 2.5 V, VR = AVSS
With external voltage reference with internal buffer
(ADC12VRSEL = 0x3), 1 20
VR+ = 2.5 V, VR = AVSS
With external voltage reference without internal
buffer (ADC12VRSEL = 0x2 or 0x4) without TLV
calibration,
1.4 3.5
TLV calibration data can be used to improve the
ET,ext Total unadjusted error parameter (4), LSB
VR+ = 2.5 V, VR = AVSS
With external voltage reference with internal buffer
(ADC12VRSEL = 0x3), 1.4 21.0
VR+ = 2.5 V, VR = AVSS
(1) See Table 5-26 and Table 5-32 for more information on internal reference performance, and see Designing With the MSP430FR59xx
and MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal or external
reference.
(2) Offset is measured as the input voltage (at which ADC output transitions from 0 to 1) minus 0.5 LSB.
(3) Offset increases as IR drop increases when VR is AVSS.
(4) For details, see the device descriptor in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's
Guide.
Table 5-25 lists the dynamic performance characteristics of the ADC with differential inputs and an
external reference.
Table 5-25. 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SNR Signal-to-noise VR+ = 2.5 V, VR = AVSS 68 71 dB
(2)
ENOB Effective number of bits VR+ = 2.5 V, VR = AVSS 10.7 11.2 bits
(1) See Table 5-26 and Table 5-32 for more information on internal reference performance, and see Designing With the MSP430FR59xx
and MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal or external
reference.
(2) ENOB = (SINAD 1.76) / 6.02
Table 5-26 lists the dynamic performance characteristics of the ADC with differential inputs and an internal
reference.
Table 5-26. 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ENOB Effective number of bits (2) VR+ = 2.5 V, VR = AVSS 10.3 10.7 Bits
(1) See Table 5-32 for more information on internal reference performance, and see Designing With the MSP430FR59xx and
MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal or external reference.
(2) ENOB = (SINAD 1.76) / 6.02
Table 5-27 lists the dynamic performance characteristics of the ADC with single-ended inputs and an
external reference.
Table 5-27. 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SNR Signal-to-noise VR+ = 2.5 V, VR = AVSS 64 68 dB
ENOB Effective number of bits (2) VR+ = 2.5 V, VR = AVSS 10.2 10.7 bits
(1) See Table 5-28 and Table 5-32 for more information on internal reference performance, and see Designing With the MSP430FR59xx
and MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal or external
reference.
(2) ENOB = (SINAD 1.76) / 6.02
Table 5-28 lists the dynamic performance characteristics of the ADC with single-ended inputs and an
internal reference.
Table 5-28. 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(2)
ENOB Effective number of bits VR+ = 2.5 V, VR = AVSS 9.4 10.4 bits
(1) See Table 5-32 for more information on internal reference performance, and see Designing With the MSP430FR59xx and
MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal or external reference.
(2) ENOB = (SINAD 1.76) / 6.02
Table 5-29 lists the dynamic performance characteristics of the ADC using a 32.678-kHz clock.
Table 5-30 lists the characteristics of the temperature sensor and built-in V1/2 of the ADC.
950
Typical Temperature Sensor Voltage (mV)
900
850
800
750
700
650
600
550
500
40 20 0 20 40 60 80
Ambient Temperature (C)
Table 5-31 lists the external reference requirements for the ADC.
5.12.9 Reference
Table 5-32 lists the characteristics of the built-in voltage reference.
5.12.10 Comparator
Table 5-33 lists the characteristics of the comparator.
5.12.11 FRAM
Table 5-34 lists the characteristics of the FRAM.
6 Detailed Description
6.1 Overview
The Texas Instruments MSP430FR59xx family of ultra-low-power microcontrollers consists of several
devices featuring different sets of peripherals. The architecture, combined with seven low-power modes is
optimized to achieve extended battery life for example in portable measurement applications. The devices
features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to
maximum code efficiency.
The MSP430FR59xx devices are microcontroller configurations with up to five 16-bit timers, Comparator,
universal serial communication interfaces (eUSCI) supporting UART, SPI, and I2C, hardware multiplier,
AES accelerator, DMA, real-time clock module with alarm capabilities, up to 40 I/O pins, and an high-
performance 12-bit analog-to-digital converter (ADC).
6.2 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-
register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data.
(7) Activated SVS (SVSHE = 1) results in higher current consumption. SVS is not included in typical current consumption.
(8) SVSHE = 1
(9) SVSHE = 0
BSL Password
Interrupt
Vectors
0FFE0h
Signatures 0FF88h
0FF80h
The power-up start address or reset vector is at 0FFFFh to 0FFFEh. It contains a 16-bit address that
points to the start address of the application program.
The interrupt vectors start at 0FFFDh and extend to lower addresses. Each vector contains the 16-bit
address of the appropriate interrupt-handler instruction sequence. Table 6-4 lists the device specific
interrupt vector locations.
The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as BSL password (if
enabled by the corresponding signature).
The signatures are located at 0FF80h extending to higher addresses. Signatures are evaluated during
device start-up. Table 6-5 lists the device specific signature locations.
A JTAG password can be programmed starting from address 0FF88h and extending to higher addresses.
The password can extend into the interrupt vector locations using the interrupt vector addresses as
additional bits for the password. The length of the JTAG password depends on the JTAG signature.
See the System Resets, Interrupts, and Operating Modes, System Control Module (SYS) chapter in the
MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide for details.
System Reset
SVSHIFG
Power up, Brownout, Supply Supervisor
PMMRSTIFG
External Reset RST
WDTIFG
Watchdog Time-out (Watchdog mode)
WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW
WDT, FRCTL MPU, CS, PMM Password
UBDIFG Reset 0FFFEh highest
Violation
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
FRAM uncorrectable bit error detection
MPUSEG3IFG
MPU segment violation
ACCTEIFG
FRAM access time error
PMMPORIFG, PMMBORIFG
Software POR, BOR
(SYSRSTIV) (1) (2)
6.8 FRAM
The FRAM can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. Features of the FRAM include:
Ultra-low-power ultra-fast-write nonvolatile memory
Byte and word access capability
Programmable wait state generation
Error correction coding (ECC)
NOTE
Wait States
For MCLK frequencies > 8 MHz, wait states must be configured following the flow described
in the Wait State Control section of the FRAM Controller (FRCTRL) chapter in the
MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide.
For important software design information regarding FRAM including but not limited to partitioning the
memory layout according to application-specific code, constant, and data space requirements, the use of
FRAM to optimize application energy consumption, and the use of the Memory Protection Unit (MPU) to
maximize application robustness by protecting the program code against unintended write accesses, see
MSP430 FRAM Technology How To and Best Practices.
6.10 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
handled using all instructions. For complete module descriptions, see the MSP430FR58xx,
MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide.
NOTE
Configuration of Digital I/Os After BOR Reset
To prevent any cross currents during start-up of the device, all port pins are high-impedance
with Schmitt triggers, and their module functions disabled. To enable the I/O functionality
after a BOR reset, the ports must be configured first and then the LOCKLPM5 bit must be
cleared. For details, see the Configuration After Reset section of the Digital I/O chapter in the
MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide.
6.10.12 TB0
TB0 is a 16-bit timer and counter (Timer_B type) with seven capture/compare registers. TB0 can support
multiple captures or compares, PWM outputs, and interval timing (see Table 6-17). TB0 has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers.
6.10.13 ADC12_B
The ADC12_B module supports fast 12-bit analog-to-digital conversions with differential and single-ended
inputs. The module implements a 12-bit SAR core, sample select control, reference generator, and a
conversion result buffer. A window comparator with lower and upper limits allows CPU-independent result
monitoring with three window comparator interrupt flags.
Table 6-18 lists the external trigger sources.
Table 6-19 lists the available multiplexing between internal and external analog inputs.
6.10.14 Comparator_E
The primary function of the Comparator_E module is to support precision slope analog-to-digital
conversions, battery voltage supervision, and monitoring of external analog signals.
6.10.15 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking. The CRC16 module signature is based on the CRC-CCITT standard.
Table 6-40. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h) (continued)
REGISTER DESCRIPTION REGISTER OFFSET
16 16 sum extension SUMEXT 0Eh
32-bit operand 1 multiply low word MPY32L 10h
32-bit operand 1 multiply high word MPY32H 12h
32-bit operand 1 signed multiply low word MPYS32L 14h
32-bit operand 1 signed multiply high word MPYS32H 16h
32-bit operand 1 multiply accumulate low word MAC32L 18h
32-bit operand 1 multiply accumulate high word MAC32H 1Ah
32-bit operand 1 signed multiply accumulate low word MACS32L 1Ch
32-bit operand 1 signed multiply accumulate high word MACS32H 1Eh
32-bit operand 2 low word OP2L 20h
32-bit operand 2 high word OP2H 22h
32 32 result 0 least significant word RES0 24h
32 32 result 1 RES1 26h
32 32 result 2 RES2 28h
32 32 result 3 most significant word RES3 2Ah
MPY32 control 0 MPY32CTL0 2Ch
Table 6-41. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)
REGISTER DESCRIPTION REGISTER OFFSET
DMA channel 0 control DMA0CTL 00h
DMA channel 0 source address low DMA0SAL 02h
DMA channel 0 source address high DMA0SAH 04h
DMA channel 0 destination address low DMA0DAL 06h
DMA channel 0 destination address high DMA0DAH 08h
DMA channel 0 transfer size DMA0SZ 0Ah
DMA channel 1 control DMA1CTL 00h
DMA channel 1 source address low DMA1SAL 02h
DMA channel 1 source address high DMA1SAH 04h
DMA channel 1 destination address low DMA1DAL 06h
DMA channel 1 destination address high DMA1DAH 08h
DMA channel 1 transfer size DMA1SZ 0Ah
DMA channel 2 control DMA2CTL 00h
DMA channel 2 source address low DMA2SAL 02h
DMA channel 2 source address high DMA2SAH 04h
DMA channel 2 destination address low DMA2DAL 06h
DMA channel 2 destination address high DMA2DAH 08h
DMA channel 2 transfer size DMA2SZ 0Ah
DMA module control 0 DMACTL0 00h
DMA module control 1 DMACTL1 02h
DMA module control 2 DMACTL2 04h
DMA module control 3 DMACTL3 06h
DMA module control 4 DMACTL4 08h
DMA interrupt vector DMAIV 0Eh
6.11.1 Capacitive Touch Functionality Ports P1, P2, P3, P4, and PJ
All port pins provide the Capacitive Touch I/O functionality as shown in Figure 6-2. The Capacitive Touch
I/O functionality is controlled using the Capacitive Touch I/O control registers CAPTIO0CTL and
CAPTIO1CTL as described in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx
Family User's Guide. The Capacitive Touch I/O functionality is not shown in the individual pin diagrams in
the following sections.
Analog Enable
PxREN.y
Capacitive Touch Enable 0
Capacitive Touch Enable 1
DVSS 0
DVCC 1 1
Direction Control
PxOUT.y 0
Output Signal
Px.y
Input Signal Q D
EN
Pad Logic
(ADC) Reference
(P1.0, P1.1)
To ADC
From ADC
To Comparator
From Comparator
CEPDx
P1REN.x
P1DIR.x 00
01 DVSS 0
10 Direction DVCC 1 1
0: Input
11
1: Output
P1OUT.x 00
From module 1 01
From module 2 10
DVSS 11
P1.0/TA0.1/DMAE0/RTCCLK/
P1SEL1.x A0/C0/VREF-/VeREF-
P1.1/TA0.2/TA1CLK/COUT/
P1SEL0.x A1/C1VREF+/VeREF+
P1IN.x P1.2/TA1.1/TA0CLK/COUT/A2/C2
EN Bus
Keeper
To modules D
Pad Logic
To ADC
From ADC
To Comparator
From Comparator
CEPDx
P1REN.x
P1DIR.x 00
01 DVSS 0
From module 2 10 Direction DVCC 1 1
0: Input
11
1: Output
P1OUT.x 00
From module 1 01
From module 2 10
DVSS 11 P1.3/TA1.2/UCB0STE/A3/C3
P1.4/TB0.1/UCA0STE/A4/C4
P1SEL1.x P1.5/TB0.2/UCA0CLK/A5/C5
P1SEL0.x
P1IN.x
EN Bus
Keeper
To modules D
Pad Logic
P1REN.x
P1DIR.x 00
01 DVSS 0
From module 2 10 Direction
DVCC 1 1
0: Input
11 1: Output
P1OUT.x 00
From module 1 01
From module 2 10
From module 3 11 P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
P1SEL1.x
P1SEL0.x
P1IN.x
EN
To modules D
Pad Logic
P2REN.x
P2DIR.x 00
01 DVSS 0
From module 2 10 Direction
DVCC 1 1
0: Input
11 1: Output
P2OUT.x 00
From module 1 01
From module 2 10
From module 3 11 P2.0/TB0.6/UCA0TXD/UCA0SIMO/
TB0CLK/ACLK
P2SEL1.x P2.1/TB0.0/UCA0RXD/UCA0SOMI/
TB0.0
P2SEL0.x P2.2/TB0.2/UCB0CLK
P2IN.x
EN
To modules D
Pad Logic
To ADC
From ADC
To Comparator
From Comparator
CEPDx
P2REN.x
P2DIR.x 00
01 DVSS 0
From module 2 10 Direction DVCC 1 1
0: Input
11
1: Output
P2OUT.x 00
From module 1 01
From module 2 10
DVSS 11 P2.3/TA0.0/UCA1STE/A6/C10
P2.4/TA1.0/UCA1CLK/A7/C11
P2SEL1.x
P2SEL0.x
P2IN.x
EN Bus
Keeper
To modules D
Pad Logic
P2REN.x
P2DIR.x 00
01 DVSS 0
Direction
From module 2 10 DVCC 1 1
0: Input
11 1: Output
P2OUT.x 00
From module 1 01
From module 2 10
DVSS 11 P2.5/TB0.0/UCA1TXD/UCA1SIMO
P2.6/TB0.1/UCA1RXD/UCA1SOMI
P2SEL1.x
P2SEL0.x
P2IN.x
EN
To modules D
Pad Logic
P2REN.x
P2DIR.x 00
01 DVSS 0
10 Direction DVCC 1 1
0: Input
11
1: Output
P2OUT.x 00
DVSS 01
DVSS 10
P2.7
DVSS 11
P2SEL1.x
P2SEL0.x
P2IN.x
EN Bus
Keeper
To modules D
Pad Logic
To ADC
From ADC
To Comparator
From Comparator
CEPDx
P3REN.x
P3DIR.x 00
01 DVSS 0
10 Direction DVCC 1 1
0: Input
11
1: Output
P3OUT.x 00
DVSS 01
DVSS 10
DVSS 11
P3.0/A12/C12
P3SEL1.x P3.1/A13/C13
P3.2/A14/C14
P3SEL0.x P3.3/A15/C15
P3IN.x
EN Bus
Keeper
To modules D
Pad Logic
P3REN.x
P3DIR.x 00
01 DVSS 0
10 Direction
DVCC 1 1
0: Input
11 1: Output
P3OUT.x 00
From module 1 01
From module 2 10
From module 3 11 P3.4/TB0.3/SMCLK
P3.5/TB0.4/CBOUT
P3SEL1.x P3.6/TB0.5
P3.7/TB0.6
P3SEL0.x
P3IN.x
EN
To modules D
Pad Logic
To ADC
From ADC
P4REN.x
P4DIR.x 00
01 DVSS 0
10 Direction DVCC 1 1
0: Input
11
1: Output
P4OUT.x 00
DVSS 01
DVSS 10
DVSS 11 P4.0/A8
P4.1/A9
P4SEL1.x P4.2/A10
P4.3/A11
P4SEL0.x
P4IN.x
EN Bus
Keeper
To modules D
Pad Logic
P4REN.x
P4DIR.x 00
01 DVSS 0
Direction
10 DVCC 1 1
0: Input
11 1: Output
P4OUT.x 00
From module 1 01
DVSS 10
DVSS 11 P4.4/TB0.5
P4.5
P4SEL1.x P4.6
P4.7
P4SEL0.x
P4IN.x
EN
To modules D
6.11.13 Port PJ, PJ.4 and PJ.5 Input/Output With Schmitt Trigger
Figure 6-14 and Figure 6-15 show the port diagrams. Table 6-60 summarizes the selection of the pin
function.
Pad Logic
To LFXT XIN
PJREN.4
PJDIR.4 00
01 DVSS 0
10 Direction DVCC 1 1
0: Input
11
1: Output
PJOUT.4 00
DVSS 01
DVSS 10
DVSS 11
PJ.4/LFXIN
PJSEL1.4
PJSEL0.4
PJIN.4
EN Bus
Keeper
To modules D
Pad Logic
To LFXT XOUT
PJSEL0.4
PJSEL1.4
LFXTBYPASS
PJREN.5
PJDIR.5 00
01 DVSS 0
10 Direction DVCC 1 1
0: Input
11
1: Output
PJOUT.5 00
DVSS 01
DVSS 10
PJ.5/LFXOUT
DVSS 11
PJSEL1.5
PJSEL0.5
PJIN.5
EN Bus
Keeper
To modules D
Pad Logic
To HFXT XIN
PJREN.6
PJDIR.6 00
01 DVSS 0
10 Direction DVCC 1 1
0: Input
11
1: Output
PJOUT.6 00
DVSS 01
DVSS 10
DVSS 11
PJ.6/HFXIN
PJSEL1.6
PJSEL0.6
PJIN.6
EN Bus
Keeper
To modules D
Pad Logic
To HFXT XOUT
PJSEL0.6
PJSEL1.6
HFXTBYPASS
PJREN.7
PJDIR.7 00
01 DVSS 0
10 Direction DVCC 1 1
0: Input
11
1: Output
PJOUT.7 00
DVSS 01
DVSS 10
DVSS 11
PJ.7/HFXOUT
PJSEL1.7
PJSEL0.7
PJIN.7
EN Bus
Keeper
To modules D
6.11.15 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With
Schmitt Trigger
Figure 6-18 shows the port diagram. Table 6-62 summarizes the selection of the pin function.
To Comparator
From Comparator
JTAG enable
From JTAG
From JTAG
PJREN.x
PJDIR.x 00
1
01 DVSS 0
0
10 Direction DVCC 1 1
0: Input
11
1: Output
PJOUT.x 00
From module 1 01 1
From Status Register (SR) 10 0
DVSS 11
PJ.0/TDO/TB0OUTH/SMCLK/
PJSEL1.x SRSCG1/C6
PJ.1/TDI/TCLK/MCLK/
PJSEL0.x SRSCG0/C7
PJIN.x PJ.2/TMS/ACLK/
SROSCOFF/C8
Bus PJ.3/TCK/
EN
Keeper SRCPUOFF/C9
To modules D
and JTAG
(1) NA = Not applicable, Per unit = content can differ from device to device
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(2) ADC gain: the gain correction factor is measured at room temperature using a 2.5-V external voltage reference without internal buffer
(ADC12VRSEL=0x2, 0x4, or 0xE). Other settings (for example, using internal reference) can result in different correction factors.
(3) ADC offset: the offset correction factor is measured at room temperature using ADC12VRSEL= 0x2 or 0x4, an external reference,
VR+ = external 2.5 V, VR- = AVSS.
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6.13 Identification
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
DVCC
Digital
+
Power Supply 1 F 100 nF
Decoupling
DVSS
AVCC
Analog
Power Supply +
1 F 100 nF
Decoupling
AVSS
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MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
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LFXIN LFXOUT
or or
HFXIN HFXOUT
CL1 CL2
See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal
oscillator with the MSP430 devices.
7.1.3 JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or
MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the
connections also support the MSP-GANG production programmers, thus providing an easy way to
program prototype boards, if desired. Figure 7-3 shows the connections between the 14-pin JTAG
connector and the target device required to support in-system programming and debugging for 4-wire
JTAG communication. Figure 7-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are
identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSP-
FET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an
alternate connection (pin 4 instead of pin 2). The VCC-sense feature senses the local VCC present on the
target board (that is, a battery or other local power supply) and adjusts the output signals accordingly.
Figure 7-3 and Figure 7-4 show a jumper block that supports both scenarios of supplying VCC to the
target board. If this flexibility is not required, the desired VCC connections may be hard-wired to eliminate
the jumper block. Pins 2 and 4 must not be connected at the same time.
For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools Users
Guide.
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J1 (see Note A)
AVCC/DVCC
J2 (see Note A)
R1
47 kW
JTAG
RST/NMI/SBWTDIO
VCC TOOL TDO/TDI TDO/TDI
2 1
VCC TARGET TDI TDI
4 3
TMS
6 5 TMS
TEST TCK
8 7 TCK
GND
10 9
RST
12 11
14 13
TEST/SBWTCK
C1 AVSS/DVSS
2.2 nF
(see Note B)
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MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
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J1 (see Note A)
AVCC/DVCC
J2 (see Note A)
R1
47 k
(See Note B)
JTAG
TEST/SBWTCK
C1
2.2 nF AVSS/DVSS
(See Note B)
7.1.4 Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function
Register (SFR), SFRRPCR.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing
specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is
edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the
external NMI. When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either
pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.
If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an
external 47-k pullup resistor to the RST/NMI pin with a 2.2-nF pulldown capacitor. The pulldown
capacitor should not exceed 2.2 nF when using devices in Spy-Bi-Wire mode or in 4-wire JTAG mode with
TI tools like FET interfaces or GANG programmers. If JTAG or Spy-Bi-Wire access is not needed, up to a
10-nF pulldown capacitor may be used.
See the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide for
more information on the referenced control registers and bits.
AVSS
VREF+/VEREF+
Using an
External +
Positive
Reference
10 F 4.7 F
VEREF-
Using an
External +
Negative
Reference
10 F 4.7 F
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Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used. The
internal reference module has a maximum drive current as specified in the Reference module's IO(VREF+)
specification.
The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are
selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage
enters the device. In this case, the 10-F capacitor is used to buffer the reference pin and filter any low-
frequency ripple. A bypass capacitor of 4.7 F is used to filter out any high-frequency noise.
120 Applications, Implementation, and Layout Copyright 20122017, Texas Instruments Incorporated
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MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471
MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
www.ti.com SLAS704F OCTOBER 2012 REVISED MARCH 2017
Copyright 20122017, Texas Instruments Incorporated Device and Documentation Support 121
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Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959
MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471
MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704F OCTOBER 2012 REVISED MARCH 2017 www.ti.com
NOTE: This figure does not represent a complete list of the available features and options, and it does not indicate that all of
these features and options are available for a given device or family.
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MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471
MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
www.ti.com SLAS704F OCTOBER 2012 REVISED MARCH 2017
EnergyTrace technology is supported with Code Composer Studio version 6.0 and newer. EnergyTrace
technology requires specialized debugger circuitry, which is supported with the second-generation
onboard eZ-FET flash emulation tool and second-generation stand-alone MSP-FET JTAG emulator. See
Advanced Debugging Using the Enhanced Emulation Module (EEM) With Code Composer Studio Version
6 and MSP430 Advanced Power Optimizations: ULP Advisor and EnergyTrace Technology for
additional information.
Design Kits and Evaluation Modules
MSP430FR5969 LaunchPad Development Kit The MSP-EXP430FR5969 LaunchPad Development
Kit is an easy-to-use microcontroller development board for the MSP430FR5969 MCU. It
contains everything needed to start developing quickly on the MSP430FRxx FRAM platform,
including onboard emulation for programming, debugging, and energy measurements.
48-pin Target Development Board and MSP-FET Programmer Bundle for MSP430FRxx FRAM
MCUs
The MSP-FET430U48C is a powerful design kit for quick application development on the
MSP microcontroller. It includes a USB debugging interface used to program and debug the
MSP MCU in system through the JTAG interface or the pin-saving Spy-Bi-Wire (2-wire
JTAG) protocol. The FRAM can be erased and programmed in seconds with only a few
keystrokes, and because the MSP FRAM consumes very little power, no external supply is
required.
MSP-TS430RGZ48C - 48-pin Target Development Board for MSP430FRxx FRAM MCUs The MSP-
TS430RGZ48C is a stand-alone 48-pin ZIF socket target board used to program and debug
the MSP430 MCU in system through the JTAG interface or the Spy-Bi-Wire (2-wire JTAG)
protocol.
Software
MSP430Ware Software MSP430Ware software is a collection of code examples, data sheets, and
other design resources for all MSP430 devices delivered in a convenient package. In
addition to providing a complete collection of existing MSP430 MCU design resources,
MSP430Ware software also includes a high-level API called MSP Driver Library. This library
makes it easy to program MSP430 hardware. MSP430Ware software is available as a
component of CCS or as a stand-alone package.
MSP430FR59xx, MSP430FR58xx Code Examples C Code examples are available for every MSP
device that configures each of the integrated peripherals for various application needs.
FRAM Embedded Software Utilities for MSP Ultra-Low-Power Microcontrollers The TI FRAM Utilities
software is designed to grow as a collection of embedded software utilities that leverage the
ultra-low-power and virtually unlimited write endurance of FRAM. The utilities are available
for MSP430FRxx FRAM microcontrollers and provide example code to help start application
development.
Capacitive Touch Software Library Free C libraries for enabling capacitive touch capabilities on
MSP430 MCUs. The MSP430 MCU version of the library features several capacitive touch
implementations including the RO and RC method.
Copyright 20122017, Texas Instruments Incorporated Device and Documentation Support 123
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Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959
MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471
MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704F OCTOBER 2012 REVISED MARCH 2017 www.ti.com
MSP Driver Library The abstracted API of MSP Driver Library provides easy-to-use function calls that
free you from directly manipulating the bits and bytes of the MSP430 hardware. Thorough
documentation is delivered through a helpful API Guide, which includes details on each
function call and the recognized parameters. Developers can use Driver Library functions to
write complete projects with minimal overhead.
MSP EnergyTrace Technology EnergyTrace technology for MSP430 microcontrollers is an energy-
based code analysis tool that measures and displays the energy profile of the application
and helps to optimize it for ultra-low-power consumption.
ULP (Ultra-Low Power) Advisor ULP Advisor software is a tool for guiding developers to write more
efficient code to fully use the unique ultra-low-power features of MSP and MSP432
microcontrollers. Aimed at both experienced and new microcontroller developers, ULP
Advisor checks your code against a thorough ULP checklist to help minimize the energy
consumption of your application. At build time, ULP Advisor provides notifications and
remarks to highlight areas of your code that can be further optimized for lower power.
IEC60730 Software Package The IEC60730 MSP430 software package was developed to help
customers comply with IEC 60730-1:2010 (Automatic Electrical Controls for Household and
Similar Use Part 1: General Requirements) for up to Class B products, which includes
home appliances, arc detectors, power converters, power tools, e-bikes, and many others.
The IEC60730 MSP430 software package can be embedded in customer applications
running on MSP430s to help simplify the customers certification efforts of functional safety-
compliant consumer devices to IEC 60730-1:2010 Class B.
Fixed Point Math Library for MSP The MSP IQmath and Qmath Libraries are a collection of highly
optimized and high-precision mathematical functions for C programmers to seamlessly port a
floating-point algorithm into fixed-point code on MSP430 and MSP432 devices. These
routines are typically used in computationally intensive real-time applications where optimal
execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and
Qmath libraries, it is possible to achieve execution speeds considerably faster and energy
consumption considerably lower than equivalent code written using floating-point math.
Floating Point Math Library for MSP430 Continuing to innovate in the low-power and low-cost
microcontroller space, TI provides MSPMATHLIB. Leveraging the intelligent peripherals of
our devices, this floating-point math library of scalar functions that are up to 26 times faster
than the standard MSP430 math functions. Mathlib is easy to integrate into your designs.
This library is free and is integrated in both Code Composer Studio IDE and IAR Embedded
Workbench IDE.
Development Tools
Code Composer Studio Integrated Development Environment for MSP Microcontrollers Code
Composer Studio (CCS) integrated development environment (IDE) supports all MSP
microcontroller devices. CCS comprises a suite of embedded software utilities used to
develop and debug embedded applications. CCS includes an optimizing C/C++ compiler,
source code editor, project build environment, debugger, profiler, and many other features.
Command-Line Programmer MSP Flasher is an open-source shell-based interface for programming
MSP microcontrollers through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire
(SBW) communication. MSP Flasher can download binary files (.txt or .hex) directly to the
MSP microcontroller without an IDE.
MSP MCU Programmer and Debugger The MSP-FET is a powerful emulation development tool often
called a debug probe which lets users quickly begin application development on MSP low-
power MCUs. Creating MCU software usually requires downloading the resulting binary
program to the MSP device for validation and debugging.
MSP-GANG Production Programmer The MSP Gang Programmer is an MSP430 or MSP432 device
programmer that can program up to eight identical MSP430 or MSP432 flash or FRAM
devices at the same time. The MSP Gang Programmer connects to a host PC using a
standard RS-232 or USB connection and provides flexible programming options that let the
user fully customize the process.
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Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959
MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471
MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
www.ti.com SLAS704F OCTOBER 2012 REVISED MARCH 2017
Copyright 20122017, Texas Instruments Incorporated Device and Documentation Support 125
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Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959
MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471
MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704F OCTOBER 2012 REVISED MARCH 2017 www.ti.com
Application Reports
MSP430 FRAM Technology How To and Best Practices FRAM is a nonvolatile memory technology
that behaves similar to SRAM while enabling a whole host of new applications, but also
changing the way firmware should be designed. This application report outlines the how to
and best practices of using FRAM technology in MSP430 from an embedded software
development perspective. It discusses how to implement a memory layout according to
application-specific code, constant, data space requirements, and the use of FRAM to
optimize application energy consumption.
MSP430 32-kHz Crystal Oscillators Selection of the right crystal, correct load circuit, and proper board
layout are important for a stable crystal oscillator. This application report summarizes crystal
oscillator function and explains the parameters to select the correct crystal for MSP430 ultra-
low-power operation. In addition, hints and examples for correct board layout are given. The
document also contains detailed information on the possible oscillator tests to ensure stable
oscillator operation in mass production.
MSP430 System-Level ESD Considerations System-Level ESD has become increasingly demanding
with silicon technology scaling towards lower voltages and the need for designing cost-
effective and ultra-low-power components. This application report addresses three different
ESD topics to help board designers and OEMs understand and design robust system-level
designs.
126 Device and Documentation Support Copyright 20122017, Texas Instruments Incorporated
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Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959
MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471
MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
www.ti.com SLAS704F OCTOBER 2012 REVISED MARCH 2017
8.7 Trademarks
EnergyTrace++, MSP430, EnergyTrace, LaunchPad, MSP430Ware, ULP Advisor, Code Composer
Studio, E2E are trademarks of Texas Instruments.
Microsoft is a registered trademark of Microsoft Corporation.
All other trademarks are the property of their respective owners.
8.10 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
Copyright 20122017, Texas Instruments Incorporated Device and Documentation Support 127
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Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959
MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471
MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704F OCTOBER 2012 REVISED MARCH 2017 www.ti.com
128 Mechanical, Packaging, and Orderable Information Copyright 20122017, Texas Instruments Incorporated
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Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959
MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471
PACKAGE OPTION ADDENDUM
www.ti.com 22-Apr-2015
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
MSP430FR59471IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR59471
& no Sb/Br)
MSP430FR59471IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR59471
& no Sb/Br)
MSP430FR5947IDA ACTIVE TSSOP DA 38 40 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5947
& no Sb/Br)
MSP430FR5947IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5947
& no Sb/Br)
MSP430FR5947IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5947
& no Sb/Br)
MSP430FR5947IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5947
& no Sb/Br)
MSP430FR5948IDA ACTIVE TSSOP DA 38 40 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5948
& no Sb/Br)
MSP430FR5948IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5948
& no Sb/Br)
MSP430FR5948IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5948
& no Sb/Br)
MSP430FR5948IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5948
& no Sb/Br)
MSP430FR5949IDA ACTIVE TSSOP DA 38 40 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5949
& no Sb/Br)
MSP430FR5949IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5949
& no Sb/Br)
MSP430FR5949IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5949
& no Sb/Br)
MSP430FR5949IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5949
& no Sb/Br)
MSP430FR5957IDA ACTIVE TSSOP DA 38 40 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5957
& no Sb/Br)
MSP430FR5957IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5957
& no Sb/Br)
MSP430FR5957IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5957
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 22-Apr-2015
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
MSP430FR5957IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5957
& no Sb/Br)
MSP430FR5958IDA ACTIVE TSSOP DA 38 40 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5958
& no Sb/Br)
MSP430FR5958IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5958
& no Sb/Br)
MSP430FR5958IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5958
& no Sb/Br)
MSP430FR5958IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5958
& no Sb/Br)
MSP430FR5959IDA ACTIVE TSSOP DA 38 40 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5959
& no Sb/Br)
MSP430FR5959IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5959
& no Sb/Br)
MSP430FR5959IRHAR ACTIVE VQFN RHA 40 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5959
& no Sb/Br)
MSP430FR5959IRHAT ACTIVE VQFN RHA 40 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5959
& no Sb/Br)
MSP430FR5967IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5967
& no Sb/Br)
MSP430FR5967IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5967
& no Sb/Br)
MSP430FR5968IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5968
& no Sb/Br)
MSP430FR5968IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5968
& no Sb/Br)
MSP430FR59691IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR59691
& no Sb/Br)
MSP430FR59691IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR59691
& no Sb/Br)
MSP430FR5969IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5969
& no Sb/Br)
MSP430FR5969IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 FR5969
& no Sb/Br)
(1)
The marketing status values are defined as follows:
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com 22-Apr-2015
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Apr-2015
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Apr-2015
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Apr-2015
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MSP430FR5948IRHAT VQFN RHA 40 250 210.0 185.0 35.0
MSP430FR5949IDAR TSSOP DA 38 2000 367.0 367.0 45.0
MSP430FR5949IRHAR VQFN RHA 40 2500 367.0 367.0 38.0
MSP430FR5949IRHAT VQFN RHA 40 250 210.0 185.0 35.0
MSP430FR5957IDAR TSSOP DA 38 2000 367.0 367.0 45.0
MSP430FR5957IRHAR VQFN RHA 40 2500 367.0 367.0 38.0
MSP430FR5957IRHAT VQFN RHA 40 250 210.0 185.0 35.0
MSP430FR5958IDAR TSSOP DA 38 2000 367.0 367.0 45.0
MSP430FR5958IRHAR VQFN RHA 40 2500 367.0 367.0 38.0
MSP430FR5958IRHAT VQFN RHA 40 250 210.0 185.0 35.0
MSP430FR5959IDAR TSSOP DA 38 2000 367.0 367.0 45.0
MSP430FR5959IRHAR VQFN RHA 40 2500 367.0 367.0 38.0
MSP430FR5959IRHAT VQFN RHA 40 250 210.0 185.0 35.0
MSP430FR5967IRGZR VQFN RGZ 48 2500 367.0 367.0 38.0
MSP430FR5967IRGZT VQFN RGZ 48 250 210.0 185.0 35.0
MSP430FR5968IRGZR VQFN RGZ 48 2500 367.0 367.0 38.0
MSP430FR5968IRGZT VQFN RGZ 48 250 210.0 185.0 35.0
MSP430FR59691IRGZR VQFN RGZ 48 2500 367.0 367.0 38.0
MSP430FR59691IRGZT VQFN RGZ 48 250 210.0 185.0 35.0
MSP430FR5969IRGZR VQFN RGZ 48 2500 367.0 367.0 38.0
MSP430FR5969IRGZT VQFN RGZ 48 250 210.0 185.0 35.0
Pack Materials-Page 3
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