INTEGRATED CIRCUITS

DATA SHEET

TDA10045H
DVB-T channel receiver
Product specification 2001 Nov 08
Supersedes data of 2000 Jun 21
File under Integrated Circuits, IC02
Philips Semiconductors Product specification

DVB-T channel receiver TDA10045H

FEATURES
2 and 8 kbytes Coded Orthogonal Frequency Division
Multiplexer (COFDM) demodulator (fully DVB-T
compliant: ETSI 300-744)
All modes supported, including hierarchical modes
Fully automatic transmission parameters detection
(including Fast Fourier Transformer (FFT) size and GENERAL DESCRIPTION
guard interval)
The TDA10045H is a single-chip channel receiver for
Digital Signal Processor (DSP) based synchronization
2 and 8 kbytes COFDM modulated signals based on the
(software can be upgraded on the fly)
ETSI specification (ETSI 300-744). The device interfaces
No extra-host software required directly to an IF signal, which could be either 1st or 2nd IF
On-chip 10-bit Analog-to-Digital Converter (ADC) and integrates a 10-bit Analog-to-Digital Converter (ADC),
a Numerically Controlled Oscillator (NCO) and a
2nd or 1st IF variable analog input
Phase-Locked Loop (PLL), simplifying external logic
Only fundamental crystal oscillator required (4 MHz requirements and limiting system costs.
typical 100 ppm)
The TDA10045H performs all the COFDM demodulation
6, 7 and 8 MHz channels with the same crystal
tasks from IF signal to the MPEG-2 transport stream. An
Pulse killer algorithm to protect against impulse noise internal DSP core manages the synchronization and the
Digital frequency correction (90 kHz) control of the demodulation process, and implements
specially developed software for robustness against
Frequency offset (1/6 MHz) automatic estimator to
speed-up the scan co-channel and adjacent channel interference, to deal with
Single Frequency Network (SFN) echo situations, and to
RF tuner input power measurement assist in a very fast scan of the bandwidth. After baseband
Parallel or serial transport stream interface conversion and FFT demodulation, the channel frequency
BER measurement (before and after Viterbi decoder) response is estimated, which is based on the scattered
pilots, and filtered in both time and frequency domains.
Signal-to noise ratio estimation
This estimation is used as a correction on the signal,
Constellation, CSI and channel frequency response carrier by carrier. A common phase error and estimator is
outputs used to deal with the tuner phase noise. The Forward Error
TPS bits I2C-bus readable (including spare ones) Correction (FEC) decoder is automatically synchronized
by the frame synchronization algorithm that uses the TPS
Controllable dedicated I2C-bus for the tuner
information included in the modulation. An embedded
(5 V tolerant)
pulse killer algorithm enables the bad effects of short and
3 low frequency spare DACs and 2 spare inputs strong impulsive noise interference that could be caused
CMOS 0.2 m technology. by electrical domestic devices and/or car traffic to be
greatly reduced.
APPLICATIONS This device is controlled via an I2C-bus (master). The chip
provides 2 switchable I2C-buses derived from the master:
DVB-T fully compatible
a tuner I2C-bus to be disconnected from the I2C-bus
Digital data transmission using COFDM modulation. master when not necessary and an EEPROM I2C-bus.
The DSP software code can be fed to the chip via the
master I2C-bus or via the dedicated EEPROM I2C-bus.
Designed in 0.2 m CMOS technology and housed in a
100 pin QFP package, the TDA10045H operates over the
commercial temperature range.

2001 Nov 08 2
Philips Semiconductors Product specification

DVB-T channel receiver TDA10045H

ORDERING INFORMATION

TYPE PACKAGE
VERSION
NUMBER NAME DESCRIPTION
TDA10045H QFP100 plastic quad flat package; 100 leads (lead length 1.95 mm); SOT317-2
body 14 20 2.8 mm

2001 Nov 08 3
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2001 Nov 08

BLOCK DIAGRAM

Philips Semiconductors
DVB-T channel receiver
VAGC

DIGITAL FRONT-END CHANNEL ESTIMATION

digital IF 10 AGC AND COFDM AND CORRECTION
FI (9:0) DEMODULATION
COFDM
TIME CARRIER spectrum CPE
BASEBAND
A RECOVERY FFT
analog IF 10 CONVERSION RECOVERY CALCULATION
D (NCO)
(VIM, VIP)
C
fs COARSE
PARTIAL CHANNEL
TIME
SACLK 2fs ESTIMATION
ESTIMATOR

XIN PLL TIME

INTERPOLATION
spare inputs
SP_IN(1:0)
DSP CORE
3* 10 FREQUENCY
3 SPARE
4

DS_SPARE(3:1) SYNCHRONIZATION INTERPOLATION

SCL_EEP optional
FREQUENCY, TIME, FRAME, RECOVERY
SDA_EEP FFT WINDOW POSITIONING
SCL I2C-BUS TPS DECODING
SDA INTERFACE CONFIDENCE CHANNEL
CALCULATION CORRECTION

confidence (I,Q)
SCL_TUN TDA10045H constellation
frequency response
SDA_TUN

INNER
MPEG-2 OUTER
RS VITERBI BIT FREQUENCY
OUTPUT DESCRAMBLER FORNEY
DECODER DECODER DE-INTERLEAVER DE-INTERLEAVER
INTERFACE DE-INTERLEAVER
AND DE-MAPPER
CPT_UNCOR VBER CBER
CHANNEL DECODER

TDA10045H

Product specification
MGU414
handbook, full pagewidth

Fig.1 Block diagram.

Philips Semiconductors Product specification

DVB-T channel receiver TDA10045H

PINNING

SYMBOL PIN TYPE DESCRIPTION

VDDD33 1 digital supply voltage for the pads (3.3 V typ.)
VSSD 2 digital ground supply (0 V
DS_SPARE3 3 O spare delta-sigma output; managed by the DSP to generate an analog level
(after a RC low-pass filter)
VAGC 4 O output value from the Delta-Sigma modulator, used to control a log-scaled
amplifier (after analog filtering)
SCL_EEP 5 O extra I2C-bus clock to download DSP code from an external EEPROM (optional
mode); can be connected to the master I2C-bus
VDDD33 6 digital supply voltage for the pads (3.3 V typ.)
VSSD 7 digital ground supply (0 V)
SDA_EEP 8 I/OD extra I2C-bus data bus to download DSP code from an external EEPROM
(optional mode). It can be connected to the master I2C-bus; this pin is
open-drain which requires an external pull-up resistor (to VDDD33 or VDDD50),
even if not used.
SCL_TUN 9 OD(1) tuner I2C-bus serial clock signal; this signal is derived from the master SCL and
is open-drain which requires an external pull-up resistor (to VDDD33 or VDDD50),
even if not used
SDA_TUN 10 I/OD tuner I2C-bus serial data signal; this signal is derived from the master SDA and
is open-drain which requires an external pull-up resistor (to VDDD33 or VDDD50),
even if not used
SCL 11 I(2) I2C-bus master serial clock; up to 700 kbit/s
SDA 12 I/OD I2C-bus master serial data input/output, open-drain I/O pad, which requires an
external pull-up resistor (to VDDD33 or VDDD50)
n.c. 13 not connected
CLR# 14 I(2) asynchronous reset signal; active LOW
EEPADDR 15 I(2) EEPADDR is the LSB of the I2C-bus address of the EEPROM. The MSBs are
internally set to 101000. Therefore the complete I2C-bus address of the
EEPROM is (MSB to LSB): 1, 0, 1, 0, 0, 0, EEPADDR.
SADDR[1:0] 16 and 17 I(2) SADDR[1:0] are the 2 LSBs of the I2C-bus address of the TDA10045; the MSBs
are internally set to 00010; therefore the complete I2C-bus address of the
TDA10045 is (MSB to LSB): 0, 0, 0, 1, 0, SADDR[1] and SADDR[0]
VDDD18 18 digital supply voltage for the core (1.8 V typ.)
VSSD 19 digital ground supply (0 V)
TM[3:0] 20 to 23 I(2) test mode bus; for test purpose; must be set to 0000
SCAN_EN 24 I(2) scan enable for production test; connected to GND
VDDD50 25 digital supply voltage (5 V typ.); can be set to 3.3 V (with caution) if the 5 V
tolerant I/O is not required
VSSD 26 digital ground supply (0 V)
DWNLOAD 27 I(2) processor control, boot mode; if set to logic 0, the DSP downloads the software
from an external EEPROM on the dedicated I2C-bus (pins SDA_EEP and
SCL_EEP). If set to logic 1 the software is downloaded in the I2C-bus register
CODE_IN from the host; in this case the external EEPROM is not needed.
SP_IN[1:0] 28 and 29 I(2) spare inputs

2001 Nov 08 5
Philips Semiconductors Product specification

DVB-T channel receiver TDA10045H

SYMBOL PIN TYPE DESCRIPTION

FFT_WIN 30 I/O output or input signal indicating the start of the active data; equals 1 during
complex sample 0 of the active FFT block; can be used to synchronize 2 chips
VDDD33 31 digital supply voltage for the pads (3.3 V typ.)
VSSD 32 digital ground supply (0 V)
SACLK 33 O sampling frequency output; this output clock can be fed to an external (10-bit)
ADC as a sampling clock; SACLK can also provide twice the sampling clock
FI[9:5] 34 to 38 I/O input data from an external ADC, FI must be tied to ground when unused,
positive notation (from 0 to 1023) or twos complement notation (from
512 to +511). In internal ADC mode, these outputs can be used to monitor
extra demodulator output signals (constellation or frequency response).
VDDD18 39 digital supply voltage for the core (1.8 V typ.)
VSSD 40 digital ground supply (0 V)
FI[4:0] 41 to 45 IO input data from an external ADC, FI must be tied to ground when unused,
positive notation (from 0 to 1023) or twos complement notation (from
512 to +511). In internal ADC mode, these outputs can be used to monitor
extra demodulator output signals (constellation or frequency response).
VDDD50 46 digital supply voltage (5 V typ.); can be set to 3.3 V (with caution) if 5 V tolerant
I/O is not required
VSSD 47 digital ground supply (0 V)
IT 48 OD(1) interrupt line; this output interrupt line can be configured by the I2C-bus
interface. This pin is an open-drain output and therefore requires an external
pull-up resistor (to VDDD33 or VDDD50).
FEL 49 OD(1) front-end lock; FEL is an open-drain output and therefore requires an external
pull-up resistor (to VDDD33 or VDDD50)
n.c. 50 not connected
n.c. 51 not connected
TRSTN 52 I(2) asynchronous reset signal for boundary scan; connected to GND if not used
TMS 53 I(2) mode programming signal for boundary scan; connected to GND if not used
TDI 54 I(2) input port for boundary scan; connected to GND if not used
TCK 55 I(2) clock signal for boundary scan; connected to GND if not used)
TDO 56 O output port for boundary scan; not connected if not used
VDDD18 57 digital supply voltage for the core (1.8 V typ.)
VSSD 58 digital ground supply (0 V)
DS_SPARE2 59 O spare delta-sigma output; managed by the DSP or by an I2C-bus register to
generate an analog level (after a RC low-pass filter)
DS_SPARE1 60 O spare delta-sigma output; managed by the DSP to handle a low frequency DAC
(automatic first stage tuner AGC measurement or 2nd AGC loop control as
examples)
VDDD33 61 digital supply voltage for the pads (3.3 V typ.)
VSSD 62 digital ground supply (0 V)
UNCOR 63 O RS error flag, active HIGH on one RS packet if the RS decoder fails to correct
the errors
PSYNC 64 O pulse synchro; this output signal goes HIGH on a rising edge of OCLK when a
synchro byte is provided, then goes LOW until the next synchro byte

2001 Nov 08 6
Philips Semiconductors Product specification

DVB-T channel receiver TDA10045H

SYMBOL PIN TYPE DESCRIPTION

DEN 65 O output data validation signal; active HIGH during the valid and regular data bytes
OCLK 66 O output clock; OCLK is the output clock for the parallel DO[7:0] outputs
DO[7:5] 67 to 69 O output data carrying the current sample of the current MPEG2 packet
(188 bytes), delivered on the rising edge of OCLK by default when the serial
mode is selected. The output data is delivered by DO[0].
VDDD18 70 digital supply voltage for the core (1.8 V typ.)
VSSD 71 digital ground supply (0 V)
DO[4:0] 72 to 76 O output data carrying the current sample of the current MPEG2 packet
(188 bytes), delivered on the rising edge of OCLK by default when the serial
mode is selected. The output data is delivered by DO[0].
VDDD33 77 digital supply voltage for the pads (3.3 V typ.)
VSSD 78 digital ground supply (0 V)
XIN 79 I(2) crystal oscillator input pin
XOUT 80 O crystal oscillator output pin; typically a fundamental crystal oscillator is
connected between pins XIN and XOUT
VDDD18 81 digital supply voltage for the core (1.8 V typ.)
VSSD 82 digital ground supply (0 V)
n.c. 83 not connected
VCCD(PLL) 84 power supply input for the digital circuits of the PLL module (1.8 V typ.)
DGND 85 ground return for the digital circuits of the PLL module
n.c. 86 not connected
PPLGND 87 ground return for the analog circuits of the PLL module
VCCA(PLL) 88 power supply input for the analog circuits of the PLL module (3.3 V typ.)
VSSA3 89 ground return for the analog circuits
VDDA3 90 power supply input for the analog circuits; the DC voltage should be 3.3 V
VIP 91 positive input to the ADC; this pin is DC biased to half supply through an internal
resistor divider (2 20 k resistors). In order to remain in the range of the ADC,
the voltage difference between pins VIP and VIM should be between 0.5 and
+0.5 V.
VIM 92 negative input to the ADC; this pin is DC biased to half supply to remain in the
range of the ADC, the voltage difference between pins VIP and VIM should be
between 0.5 and +0.5 V through an internal resistor divider (2 20 k
resistors)
Vref(neg) 93 negative reference voltage for the ADC
Vref(pos) 94 positive reference voltage for the ADC
VDDA3 95 power supply input for the analog circuits; the DC voltage should be 3.3 V
VSSA3 96 ground return for analog circuits
VSSA2 97 ground return for the analog clock drivers
VDDA2 98 power supply input for the analog clock drivers; the DC voltage should be 3.3 V
VSSA1 99 ground return for the digital switching circuitry
VDDD1 100 power supply input for the digital switching circuitry; sensitive to the supply
noise; the DC voltage should be 1.8 V

2001 Nov 08 7
Philips Semiconductors Product specification

DVB-T channel receiver TDA10045H

Notes
1. OD are open-drain outputs, so they must be connected to a pull-up resistor to either VDDD33 or VDDD50
2. All inputs (I) are TTL, 5 V tolerant, (if VDD50 is set to 5 V).
3. Foundry test I/O inputs must be connected to GND.

84 VCCD(PLL)
88 VCCA(PLL)
93 Vref(neg)
94 Vref(pos)

87 PPLGND

81 VDDD18
100 VDDD1

98 VDDA2

95 VDDA3

90 VDDA3
99 VSSA1

97 VSSA2
96 VSSA3

89 VSSA3

85 DGND

82 VSSD
92 VIM
91 VIP

86 n.c.

83 n.c.
handbook, full pagewidth

VDDD33 1 80 XOUT
VSSD 2 79 XIN
DS_SPARE3 3 78 VSSD
VAGC 4 77 VDDD33
SCL_EEP 5 76 DO[0]
VDDD33 6 75 DO[1]
VSSD 7 74 DO[2]
SDA_EEP 8 73 DO[3]
SCL_TUN 9 72 DO[4]
SDA_TUN 10 71 VSSD
SCL 11 70 VDDD18
SDA 12 69 DO[5]
n.c. 13 68 DO[6]
CLR# 14 67 DO[7]
EEPADDR 15 66 OCLK
TDA10045H
SADDR[1] 16 65 DEN
SADDR[0] 17 64 PSYNC
VDDD18 18 63 UNCOR
VSSD 19 62 VSSD
TM[3] 20 61 VDDD33
TM[2] 21 60 DS_SPARE1
TM[1] 22 59 DS_SPARE2
TM[0] 23 58 VSSD
SCAN_EN 24 57 VDDD18
VDDD50 25 56 TDO
VSSD 26 55 TCK
DWNLOAD 27 54 TDI
SP_IN[1] 28 53 TMS
SP_IN[0] 29 52 TRSTN
FFT_WIN 30 51 n.c.
VDDD33 31
VSSD 32
SACLK 33
FI[9] 34
FI[8] 35
FI[7] 36
FI[6] 37
FI[5] 38
VDDD18 39
VSSD 40
FI[4] 41
FI[3] 42
FI[2] 43
FI[1] 44
FI[0] 45
VDDD50 46
VSSD 47
IT 48
FEL 49
n.c. 50

MGU413

Fig.2 Pin configuration.

2001 Nov 08 8
Philips Semiconductors Product specification

DVB-T channel receiver TDA10045H

LIMITING VALUES
In accordance with the Absolute Maximum Rate System (IEC 60134); note 1.
SYMBOL PARAMETER MIN. MAX. UNIT
VDDD18 digital supply voltage for the core 0.5 +2.1 V
VDDD33 digital supply voltage for the pads 0.5 +3.8 V
VI DC input voltage 0.5 +5.5 V
II DC input current 20 mA
Tlead lead temperature 300 C
Tstg storage temperature 65 +150 C
Tj junction temperature 150 C
Tamb ambient temperature 0 70 C

Note
1. Stresses above the Absolute Maximum Ratings may cause permanent damage to the device. Exposure to Absolute
Maximum Ratings conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth(j-a) thermal resistance from junction to ambient in free air tbf K/W

2001 Nov 08 9
Philips Semiconductors Product specification

DVB-T channel receiver TDA10045H

CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Core and pads
VDDD33 digital supply voltage for the VDDD = 3.3 V 10% 2.97 3.3 3.63 V
pads
VDDD18 digital supply voltage for the VDDD = 1.8 V 5% 1.7 1.8 1.9 V
core
VDDD50 5 V supply voltage only for 5 V 4.75 5.0 5.25 V
requirements; note 1
Tamb ambient temperature 0 70 C
VIH HIGH-level input voltage TTL input; note 2 2 VDDD50 V
VIL LOW-level input voltage TTL input 0 0.8 V
VOH HIGH-level output voltage IOH = 2 mA 2.4 V
VOL LOW-level output voltage IOL = 2 mA 0.4 V
Ci input capacitance 5 pF
Co output capacitance 5 pF
PLL
VCCD(PLL) digital PLL supply voltage VCCD = 1.8 V 5% 1.7 1.8 1.9 V
VCCA(PLL) analog PLL supply voltage VCCA = 3.3 V 10% 2.97 3.3 3.63 V
ADC
VDDD1 digital ADC supply voltage VDDD = 1.8 V 5% 1.7 1.8 1.9 V
VDDA2, VDDA3 analog ADC supply voltage VDDA = 3.3 V 10% 2.97 3.3 3.63 V
Vi(ADC) analog ADC inputs pins VIP 0.5 VDDD3 + 0.5 V
and VIM
Vi signal input IR = VIP VIM; 0.5 to 1.0 +0.5 to +1.0 V
depending on SW
register
Vref(pos) positive reference voltage with SW register = 11 1.95 2.15 2.35 V
Vref(neg) negative reference voltage with SW register = 11 0.95 1.15 1.35 V
Vi(offset) input offset voltage 25 +25 mV
Ri input resistance pin VIP or 10 k
VIM
Ci input capacitance pin VIP or 5 10 pF
VIM
BW input full power bandwidth 3 dB bandwidth 40 50 MHz

2001 Nov 08 10
Philips Semiconductors Product specification

DVB-T channel receiver TDA10045H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Power consumption
IDDD digital supply current on fs = 29 Mhz; direct IF
pins: application
VDDD18 and VDDD1 140 160 mA
VDDD33 3 mA
VCCD(PLL), VDDA2 and VDDA3 35 mA
VDDD50 5 mA
Ptot total power dissipation 400 470 mW
Notes
1. The voltage level of the 5 V supply must always exceed, or at least equal, the voltage level of the 3.3 V supply during
power-up and down in order to guarantee protection against latch-up.
2. All inputs are 5 V tolerant.

2001 Nov 08 11
Philips Semiconductors Product specification

DVB-T channel receiver TDA10045H

APPLICATION INFORMATION

handbook, full pagewidth

I2C-BUS
RC
EEPROM

optinal

IF1 or VAGC XIN XOUT SDA_EEP

IF1 IF2 SCL_EEP
IF_AGC VIP A
RF TUNER + 10
SAWs IF D
INTERFACE VIM C PSYNC
SCL
RF_AGC SDA UNCOR
optional IF2
downconversion DEN
TDA10045H
reference OCLK
frequency 8
RC SACLK DO[7:0]

SDA_TUN
SCL_TUN
RC DS_SPARE_1
SP_IN(0) SCL, SDA

optional ADC
I2C-bus
MGU415

Fig.3 DVB-T front-end receiver.

handbook, full pagewidth VDDD50 VDDD33 VDDD18 VSSD

XIN XOUT VAGC

SDA_TUN
10
FI[9:0] SCL_TUN
IT

TDA10045H FEL
CLR# PSYNC
VIP UNCOR
VIM DEN
OCLK
I2C-BUS
8
INTERFACE DSP INTERFACE JTAG DO[7:0]

MGU416
SADDR(1:0) SDA SDA_EEP SP_IN TDI TDO
TCK
SCL SCL_EEP BS_SPARE TMS
TRST

Fig.4 Application diagram.

2001 Nov 08 12
Philips Semiconductors Product specification

DVB-T channel receiver TDA10045H

Tuner TDA10045H
A RF tracking filter tracks the RF wanted frequency and The chip is controlled by an I2C-bus and driven by an
suppresses the image external low-cost crystal oscillator
A first local wideband AGC is usually done at RF level, The software of the embedded DSP can be downloaded
the AGC level information could be provided externally from the main I2C-bus or from a dedicated I2C-bus
and the chip offers facilities to measure this level by the connected to an external slave I2C-bus EEPROM
optional ADC (this measurement is automatically made An internal bidirectional switch enables the tuner to be
by the DSP, the host has just to read the result) programmed through the chip and then switch-off the
A mixer oscillator and a PLL downconverts the RF signal link in order to avoid phase noise distortions due to
to intermediate frequency IF1 (36.125 MHz typ.) I2C-bus traffic.
SAW filters eliminate the power of the adjacent channels
around IF1.

IF interface
It is either an analog IF amplifier when IF1 is sampled
(direct IF: digital downconversion concept) or an analog
IF amplifier followed by a downconversion from IF1 to
IF2 at a few MHz (e.g. 4.57 MHz)
When this second solution is used, the ADC sampling
clock could be used (after low-pass filtering) as a
reference clock for downconversion (twice the ADC
sampling clock could also be provided)
The IF amplifier is controlled by the digital AGC of the
chip. A simple RC circuit filters the single bit
( modulated) AGC control (VAGC)
The sampling clock could also be used to control an
external ADC, the inputs to the chip will then be digital
(FI[9:0]).

2001 Nov 08 13
Philips Semiconductors Product specification

DVB-T channel receiver TDA10045H

PACKAGE OUTLINE
QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT317-2

c
y
X

80 51 A
81 50 ZE

e
A2
E HE A
A1 (A 3)

wM
pin 1 index Lp
bp
L

100 31 detail X
1 30

wM ZD v M A
e bp

D B
HD v M B

0 5 10 mm
scale

DIMENSIONS (mm are the original dimensions)

A
UNIT max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y Z D (1) Z E(1)
o
0.25 2.90 0.40 0.25 20.1 14.1 24.2 18.2 1.0 0.8 1.0 7
mm 3.20 0.25 0.65 1.95 0.2 0.15 0.1
0.05 2.65 0.25 0.14 19.9 13.9 23.6 17.6 0.6 0.4 0.6 0o

Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION

97-08-01
SOT317-2 MO-112
99-12-27

2001 Nov 08 14
Philips Semiconductors Product specification

DVB-T channel receiver TDA10045H

SOLDERING Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a
Introduction to soldering surface mount packages
smooth laminar wave.
This text gives a very brief insight to a complex technology. For packages with leads on two sides and a pitch (e):
A more in-depth account of soldering ICs can be found in
larger than or equal to 1.27 mm, the footprint
our Data Handbook IC26; Integrated Circuit Packages
longitudinal axis is preferred to be parallel to the
(document order number 9398 652 90011).
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface smaller than 1.27 mm, the footprint longitudinal axis
mount IC packages. Wave soldering can still be used for must be parallel to the transport direction of the
certain surface mount ICs, but it is not suitable for fine pitch
printed-circuit board.
SMDs. In these situations reflow soldering is
recommended. The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering For packages with leads on four sides, the footprint must
be placed at a 45 angle to the transport direction of the
Reflow soldering requires solder paste (a suspension of
printed-circuit board. The footprint must incorporate
fine solder particles, flux and binding agent) to be applied
solder thieves downstream and at the side corners.
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement. During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
Several methods exist for reflowing; for example,
applied by screen printing, pin transfer or syringe
convection or convection/infrared heating in a conveyor
dispensing. The package can be soldered after the
type oven. Throughput times (preheating, soldering and
adhesive is cured.
cooling) vary between 100 and 200 seconds depending
on heating method. Typical dwell time is 4 seconds at 250 C.
A mildly-activated flux will eliminate the need for removal
Typical reflow peak temperatures range from
of corrosive residues in most applications.
215 to 250 C. The top-surface temperature of the
packages should preferable be kept below 220 C for
Manual soldering
thick/large packages, and below 235 C for small/thin
packages. Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
Wave soldering less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
Conventional single wave soldering is not recommended
300 C.
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and When using a dedicated tool, all other leads can be
non-wetting can present major problems. soldered in one operation within 2 to 5 seconds between
270 and 320 C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:

2001 Nov 08 15
Philips Semiconductors Product specification

DVB-T channel receiver TDA10045H

Suitability of surface mount IC packages for wave and reflow soldering methods

SOLDERING METHOD
PACKAGE
WAVE REFLOW(1)
BGA, HBGA, LFBGA, SQFP, TFBGA not suitable suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS not suitable(2) suitable
PLCC(3), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(3)(4) suitable
SSOP, TSSOP, VSO not recommended(5) suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DATA SHEET STATUS

PRODUCT
DATA SHEET STATUS(1) DEFINITIONS
STATUS(2)
Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.

Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

2001 Nov 08 16
Philips Semiconductors Product specification

DVB-T channel receiver TDA10045H

DEFINITIONS DISCLAIMERS
Short-form specification The data in a short-form Life support applications These products are not
specification is extracted from a full data sheet with the designed for use in life support appliances, devices, or
same type number and title. For detailed information see systems where malfunction of these products can
the relevant data sheet or data handbook. reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
Limiting values definition Limiting values given are in
for use in such applications do so at their own risk and
accordance with the Absolute Maximum Rating System
agree to fully indemnify Philips Semiconductors for any
(IEC 60134). Stress above one or more of the limiting
damages resulting from such application.
values may cause permanent damage to the device.
These are stress ratings only and operation of the device Right to make changes Philips Semiconductors
at these or at any other conditions above those given in the reserves the right to make changes, without notice, in the
Characteristics sections of the specification is not implied. products, including circuits, standard cells, and/or
Exposure to limiting values for extended periods may software, described or contained herein in order to
affect device reliability. improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
Application information Applications that are
the use of any of these products, conveys no licence or title
described herein for any of these products are for
under any patent, copyright, or mask work right to these
illustrative purposes only. Philips Semiconductors make
products, and makes no representations or warranties that
no representation or warranty that such applications will be
these products are free from patent, copyright, or mask
suitable for the specified use without further testing or
work right infringement, unless otherwise specified.
modification.
ICs with MPEG-2 functionality Use of this product in
any manner that complies with the MPEG-2 Standard is
expressly prohibited without a license under applicable
patents in the MPEG-2 patent portfolio, which license is
available from MPEG LA, L.L.C., 250 Steele Street, Suite
300, Denver, Colorado 80206.

PURCHASE OF PHILIPS I2C COMPONENTS

Purchase of Philips I2C components conveys a license under the Philips I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2001 Nov 08 17
Philips Semiconductors Product specification

DVB-T channel receiver TDA10045H

NOTES

2001 Nov 08 18
Philips Semiconductors Product specification

DVB-T channel receiver TDA10045H

NOTES

2001 Nov 08 19
Philips Semiconductors a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825

For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

Koninklijke Philips Electronics N.V. 2001 SCA73

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Printed in The Netherlands 753504/04/pp20 Date of release: 2001 Nov 08 Document order number: 9397 750 08496
This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.