FAN7529 (IC601) - Datasheet II
FAN7529 (IC601) - Datasheet II
FAN7529 (IC601) - Datasheet II
April 2007
FAN7529
Critical Conduction Mode PFC Controller
Features Description
Low Total Harmonic Distortion (THD) The FAN7529 is an active power factor correction (PFC)
Precise Adjustable Output Over-Voltage Protection controller for boost PFC applications that operates in crit-
Open-Feedback Protection and Disable Function ical conduction mode (CRM). It uses the voltage mode
PWM that compares an internal ramp signal with the
Zero Current Detector
error amplifier output to generate MOSFET turn-off sig-
150s Internal Start-up Timer nal. Because the voltage-mode CRM PFC controller does
MOSFET Over-Current Protection not need rectified AC line voltage information, it saves the
Under-Voltage Lockout with 3.5V Hysteresis power loss of the input voltage sensing network neces-
Low Start-up (40A) and Operating Current (1.5mA) sary for the current-mode CRM PFC controller.
Totem Pole Output with High State Clamp FAN7529 provides many protection functions, such as
+500/-800mA Peak Gate Drive Current over-voltage protection, open-feedback protection, over-
8-Pin DIP or 8-Pin SOP
current protection, and under-voltage lockout protection.
The FAN7529 can be disabled if the INV pin voltage is
Applications lower than 0.45V and the operating current decreases to
65A. Using a new variable on-time control method,
Adapter THD is lower than the conventional CRM boost PFC ICs.
Ballast
LCD TV, CRT TV
SMPS
Ordering Information
Operating Temp. Marking
Part Number Range Pb-Free Package Packing Method Code
FAN7529N -40C to +125C Yes 8-DIP Rail FAN7529
FAN7529M -40C to +125C Yes 8-SOP Rail FAN7529
FAN7529MX -40C to +125C Yes 8-SOP Tape & Reel FAN7529
AC
IN
NAUX
VAUX
RZCD
R2 ZCD
CO
VCC
FAN7529 INV
MOT
CS
COMP
R1
GND
FAN7529 Rev. 00
2.5V Vref1
VCC 8
Ref VCC
UVLO
Internal
Bias
Drive 7 OUT
12V 8.5V Disable Output
Timer
ZCD 5 S
6.7V Q
1.4V 1.5V
Zero Current R OVP
Detector 2.675V 2.5V
CS 4
Disable
40k 0.45V 0.35V
8pF
Current Protection
0.8V Comparator
Ramp
Signal Vref1
1V Offset Error
Saw Tooth
MOT 3 Amplifier
Generator
Gm
2.9V 1V~5V 1 INV
Range
6 2
GND FAN7529 Rev. 00
COMP
YWW
FAN7529
1 2 3 4
INV COMP MOT CS
FAN7529 Rev. 00
Pin Definitions
Pin # Name Description
This pin is the inverting input of the error amplifier. The output voltage of the boost PFC
1 INV
converter should be resistively divided to 2.5V.
This pin is the output of the transconductance error amplifier. Components for output
2 COMP
voltage compensation should be connected between this pin and GND.
This pin is used to set the slope of the internal ramp. The voltage of this pin is main-
3 MOT tained at 2.9V. If a resistor is connected between this pin and GND, current flows out of
the pin and the slope of the internal ramp is proportional to this current.
This pin is the input of the over-current protection comparator. The MOSFET current is
4 CS sensed using a sensing resistor and the resulting voltage is applied to this pin. An
internal RC filter is included to filter switching noise.
This pin is the input of the zero current detection block. If the voltage of this pin goes
5 ZCD
higher than 1.5V, then goes lower than 1.4V, the MOSFET is turned on.
This pin is used for the ground potential of all the pins. For proper operation, the signal
6 GND
ground and the power ground should be separated.
This pin is the gate drive output. The peak sourcing and sinking current levels are
7 OUT +500mA and -800mA respectively. For proper operation, the stray inductance in the
gate driving path must be minimized.
This pin is the IC supply pin. IC current and MOSFET drive current are supplied using
8 VCC
this pin.
Thermal Impedance(1)
Symbol Parameter Value Unit
8-DIP 110 C/W
J Thermal Resistance, Junction-to-Ambient
8-SOP 150 C/W
Note:
1. Regarding the test environment and PCB type, please refer to JESD51-2 and JESD51-10.
13.0 9.5
12.5 9.0
Vth(stop) [V]
Vth(start) [V]
12.0 8.5
11.5 8.0
11.0 7.5
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature [C] Temperature [C]
Figure 4. Start Threshold Voltage vs. Temp. Figure 5. Stop Threshold Voltage vs. Temp.
4.00 23.0
3.75 22.5
HY(UVLO) [V]
VZ [V]
3.50 22.0
3.25 21.5
3.00 21.0
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature [C] Temperature [C]
Figure 6. UVLO Hysteresis vs. Temp. Figure 7. Zener Voltage vs. Temp.
60 2.4
45
ICC [mA]
1.6
Ist [A]
30
0.8
15
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature [C] Temperature [C]
Figure 8. Start-up Supply Current vs. Temp. Figure 9. Operating Supply Current vs. Temp.
4 90
3 72
ICC(dis) [A]
Idcc [mA]
2 54
1
36
0
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature [C] Temperature [C]
Figure 10. Dynamic Operating Supply Current vs. Figure 11. Operating Current at Disable vs. Temp.
Temp.
10.0
2.52
7.5
Vref1 [mV]
Vref1 [V]
2.50 5.0
2.5
2.48
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature [C] Temperature [C]
Figure 12. Vref1 vs. Temp. Figure 13. Vref1 vs. Temp.
0.50
-9
0.25
Ib(ea) [A]
Isource [A]
0.00 -12
-0.25 -15
-0.50 -18
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature [C] Temperature [C]
Figure 14. Input Bias Current vs. Temp. Figure 15. Output Source Current vs. Temp.
18 6.6
15 6.3
Veao(H) [V]
Isink [A]
12 6.0
9 5.7
6 5.4
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature [C] Temperature [C]
Figure 16. Output Sink Current vs. Temp. Figure 17. Output Upper Clamp Voltage vs. Temp.
1.10
3.00
1.05
2.95
Veao(Z) [V]
Vmot [V]
1.00 2.90
2.85
0.95
2.80
0.90
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature [C] Temperature [C]
Figure 18. Zero Duty Cycle Output Voltage vs. Temp. Figure 19. Maximum On-Time Voltage vs. Temp.
0.90
27
0.85
Ton(max) [s]
Vcs(limit) [V]
24 0.80
0.75
21
0.70
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature [C] Temperature [C]
Figure 20. Maximum On-Time vs. Temp. Figure 21. Current Sense Input Threshold Voltage vs.
Temp.
1.0 7.2
0.5
6.8
Vclamp(H) [V]
Ib(cs) [A]
0.0
6.4
-0.5
6.0
-1.0
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature [C] Temperature [C]
Figure 22. Input Bias Current vs. Temp. Figure 23. Input High Clamp Voltage vs. Temp.
1.00 1.0
0.75 0.5
Vclamp(L) [V]
Ib(zcd) [A]
0.50 0.0
0.25 -0.5
0.00 -1.0
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature [C] Temperature [C]
Figure 24. Input Low Clamp Voltage vs. Temp. Figure 25. Input Bias Current vs. Temp.
0.9
14
0.6
VO(max) [V]
VO(uvlo) [V]
0.3
13
0.0
12
-0.3
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature [C] Temperature [C]
Figure 26. Maximum Output Voltage vs. Temp. Figure 27. Output Voltage with UVLO Activated vs.
Temp.
300 2.73
250
2.70
200
td(rst) [s]
Vovp [V]
2.67
150
100 2.64
50
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature [C] Temperature [C]
Figure 28. Restart Delay Time vs. Temp. Figure 29. OVP Threshold Voltage vs. Temp.
0.500
0.21
0.475
HY(OVP) [V]
Vth(en) [V]
0.18
0.450
0.15 0.425
0.12 0.400
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature [C] Temperature [C]
Figure 30. OVP Hysteresis vs. Temp. Figure 31. Enable Threshold Voltage vs. Temp.
0.150
0.125
HY(en) [V]
0.100
0.075
0.050
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature [C]
40k OCP
CS 4 Signal 6. Under-Voltage Lockout Block
If the VCC voltage reaches 12V, the ICs internal blocks
8pF
are enabled and start operation. If the VCC voltage drops
Over Current Protection below 8.5V, most of the internal blocks are disabled to
0.8V Comparator reduce the operating current. VCC voltage should be
higher than 8.5V under normal conditions.
FAN7529 Rev. 00
Features
High efficiency (>90% at 85VAC input)
Low Total Harmonic Distortion (THD) (<10% at 265VAC input, 25W load)
1. Schematic
T1 PFC OUTPUT
VAUX
D2
BD C5
R3 R4 R5
D3 R10
C10
Q1
NTC
ZD1 C11 R6
D1
C3 C4 C9
8 7 6 5
VCC OUT GND ZCD
C2 R9
LF1 FAN7529
R2
C1 R11
INV COMP MOT CS
1 2 3 4
V1
R8 R7
F1 C7 R1
C8
C6
FAN7529 Rev. 00
AC INPUT
NVcc
Np
FAN7529 Rev. 00
3. Winding Specification
4. Electrical Characteristics
8. Performance Data
8-DIP
Dimensions are in millimeters (inches) unless otherwise noted..
)
6.40 0.20
0.031
0.79
0.252 0.008
1.524 0.10
0.060 0.004
0.018 0.004
0.46 0.10
(
#1 #8
0.362 0.008
MAX
9.20 0.20
0.378
9.60
#4 #5
0.100
2.54
5.08 3.30 0.30
MAX 0.130 0.012
0.200
7.62
0.300 3.40 0.20 0.33
0.134 0.008 0.013 MIN
+0.10
0.25 0.05
+0.004
0.010 0.002
0~15 September 1999, Rev B
8dip_dim.pdf
8-SOP
Dimensions are in millimeters (inches) unless otherwise noted.
0.1~0.25
MIN
0.004~0.001
1.55 0.20
0.061 0.008
)
0.022
0.56
(
#1 #8
0.194 0.008
MAX
4.92 0.20
0.202
5.13
0.016 0.004
0.41 0.10
#4 #5
0.050
1.27
6.00 0.30 1.80
0.236 0.012 MAX
0.071
0.006 -0.002
0.15 -0.05
MAX0.004
MAX0.10
3.95 0.20
+0.004
+0.10
0.156 0.008
5.72
8
0~
0.225
0.50 0.20
0.020 0.008
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILDS
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.