TN-46-02

DECOUPLING CALCULATION FOR DDR

TECHNICAL NOTE DECOUPLING CAPACITOR

CALCULATION FOR A DDR
MEMORY CHANNEL

Introduction Figure 1: Current Flow During Logic

The fast switching rates of DDR memory devices Transition from 1 to 0
require significantly more burst current than previous
memory technologies, such as SDRAM. In a worst-case
scenario, as many as 81 drivers (64 data, 8 ECC, 9
strobe) may be switching from one state to the other
on a memory module. In a pipelined access , the con-
troller may have an additional 28 signals transitioning
at the same time. This large burst current generates
noise in the supply voltages as charge is drained from
decoupling capacitors. Furthermore, the burst current
causes supply voltages to drop momentarily until the
system power supply, or voltage regulator, can begin
recharging the decoupling capacitors.
Traditional methods for providing power decou-
pling involve placing capacitors near the switching
device in locations that are convenient based on the Itotal = Idc + Iac; where Idc = average steady state cur-
routing of the board, and applying some predeter- rent through Rs, the series resistor, Rt, the parallel ter-
mined ratio of caps to driver pins. Unfortunately, the mination resistor, and Rd, the driver resistance.
higher switching speeds of DDR may render such typi- termination resistor. Iac = switching current for one net
cal ratios less than useful. Careful planning and analy- to change logic states.
sis should be performed to ensure that sufficient As an example, consider a memory channel that
decoupling is provided. supports two double-sided, unbuffered DDR DIMMs,
The following analysis example and recommenda- with Rs = 0 ohms, Rd = 13 ohms, and Rt = 39 ohms.
tions are based on a prototype PC motherboard that Assume that the worst-case switching maintains a 1 V/
supports unbuffered DDR SDRAM. This board was ns edge rate (see Formula 1).
designed and built by Micron Architecture Labs as a
reference board for DDR memory.
Idc = ( VR + RMVTT
DD
s d +R ) t
or Idc = ( 02.5+ 13 1.25
+ 39 )

Current Draw where:

Total current per net is the combination of steady MVTT = 1.25V
VDD = 2.5V
state current through the termination resistors, Idc,
and the switching current through the driver, Iac. Idc is Iac = C ( dvdt ) or Iac = 30 (1.875
1.5 )
constant until the driver changes state. Iac only flows where:
during the state transition. Because the steady state C = load capacitance
dv = voltage range
current transitions from a positive (or negative) level to dt = 10%90% rise/fall time
a negative (or positive) level during the time that Iac is
flowing through the driver, it must be accounted for at Note: DDR SDRAM worst-case input capacitance for DQ/DQS = 5pF
Two double-sided DIMMs = 4 loads per net, 20pF. 2.5pF per inch for a
the same time (see Figure 1). 60 ohm PCB trace. 4 inches of trace would be 10pF. Trace capacitance
plus DRAM capacitance is 30pF.
Voltage switching range at load = 1.875V. 10% to 90% switching time,
worst case = 1.5ns.
For this example:
Idc = 24.0mA
Iac = 37.5mA

(f 1)

TBD
TN4602.fm - Rev. B 7/04 EN 1 2000 Micron Technology, Inc. All rights reserved.

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY THE
APPLICABLE MANUFACTURER WITHOUT NOTICE. MICRON AND TI ONLY WARRANT THEIR RESPECTIVE PRODUCTS TO MEET PRODUCTION DATA SHEET
SPECIFICATIONS. ALL INFORMATION DISCUSSED HEREIN IS PROVIDED ON AN AS IS BASIS, WITHOUT WARRANTIES OF ANY KIND.
 TN-46-02
DECOUPLING CALCULATION FOR DDR
Inductance is much tighter than V2.5, therefore, Lmax for the termi-
The critical limiting factor in designing a decou- nation voltage MVTT, should be calculated separately
pling system is usually not the amount of capacitance. from Lmax for V2.5. For simplicity of calculations,
It is the amount of inductance in the capacitor leads assume that only Idc flows from MVTT and Iac flows
and the vias that attach the caps to the power and from V2.5. In reality, MVTT contributes to the Iac cur-
ground planes. Using 0.1F caps in a 0603 package rent flow during the edge transition, but estimating or
should provide sufficient capacitance when the follow- calculating that contribution would likely not affect
ing calculations are used. the results significantly.
Also note di for MVTT equals twice Idc. This is
Via Inductance because Idc transitions from a positive value to a nega-
Current flows through a via only to the depth of the tive value of the same magnitude. Iac transitions from 0
plane to which it attaches. For example, on a 0.062" to its maximum value during dt, therefore di for V2.5 =
board with the ground plane only 0.004" below the top Iac (see Formula 3).
layer, the effective length of the via would be 0.004".
Typically, each decoupling cap attaches to an internal Lmax =
V(dt)
or Lmax =
0.1(1.5 10-9)

power plane, as well as the ground plane. If the PCB N(di) 109(2 0.024)

stackup is symmetrical and the same diameter via is Where:

used for power and ground, using the length of a single V = MAX allowable voltage drop
dt = 10%90% switching time
via through the entire thickness of the board is equal to di = current per net
N = number of nets switching simultaneously = 109
the sum of the via lengths for power and ground. This
simplifies the calculation of the via inductance. Note: For di use 2 x Idc for MVTT and Iac for V2.5
Tolerance specification for MVTT is 100mV
NOTE: If via structures for power and ground are dif- Tolerance specification for V2.5 is 200mV

ferent, e.g., two ground vias and one power For this example:
MVTT Lmax = 0.029nH
via, then separate calculations for each struc-
V2.5 Lmax = 0.073nH
ture should be done.
To calculate the via inductance, use the following
equation from Johnson & Grahams High-Speed Digital
(f 3)
Design: A Handbook of Black Magic (see Formula 2).
Equivalent Inductance per Capacitor
Package inductance for a 0603 cap can vary from
Lvia = 5.08h In
[ ( ) ]
4h
d
+1 [ (
or Lvia = 5.08h In
0.013) ]
4(0.050)
+1
manufacturer to manufacturer and from one dielectric
Where: type to another. Designers should check component
h = via length data sheets for the correct inductance value if available
d = via diameter
(see Formula 4).
For this example:
0.050" board For this example:
0.013" via 0603 cap was used with a package inductance of 0.87nH
Lvia = 0.948nH
0603 Leq = Lpackage + Lvia
Note: Via sizes are different for the motherboard and DIMM 0603 Leq = 0.87nH + 0.948nH = 1.82nH
module. For simplification we are using the same
values for both.
(f 4)
(f 2)
Number of Capacitors Needed
Maximum Allowable Inductance To calculate the number of capacitors needed,
The fast switching current induces a voltage drop in divide the equivalent inductance of each cap by the
the parasitic inductance of the capacitor and the vias maximum allowable inductance, Lmax (see Formula 5).
that attach it to the voltage planes. From the standard
equation V = L(di/dt), Lmax can be calculated. There Ncap = Leq/Lmax

are two current paths that ultimately flow through the

For this example:
driver. In the case of a 1-to-0 transition, Idc flows MVTT Ncap = 1.82nH/0.029nH = 63
through Rd, Rs and Rt. Iac flows from the charged input V2.5 Ncap = 1.82nH/0.073nH = 25

gates through Rd and Rs into the ground plane. In the (f 5)

case of a 0-to-1 transition, the same current flows in
the other direction from V2.5. The tolerance of MVTT

TBD Micron Technology, Inc., reserves the right to change products or specifications without notice.
TN4602.fm - Rev. B 7/04 EN 2 2000 Micron Technology, Inc. All rights reserved.
 TN-46-02
DECOUPLING CALCULATION FOR DDR
The capacitor count for MVTT may be reduced significantly affect the results. For instance, these cal-
depending on implementation. Some designs may culations were based on using Rd = 13 ohms and Rt =
allow MVTT to be implemented on a surface layer 39 ohms. Changing the resistor values to 22 and 29, for
island, in which case one terminal of the cap can be example, will increase the amount of Idc per net to
attached directly to the plane without a via. Addition- 24.5mA. This reduces MVTT_Lmax and increases the
ally, the effective length of the ground via may be sig- MVTT capacitor count and the V2.5 capacitor count.
nificantly reduced if the PCB stackup has the ground
plane immediately below the surface layer. If this is the Although difficult to predetermine, lower series
case (assuming h = .004"), Lvia = 24.5pH, which is insig- resistance, Rs will also speed up signal edges, resulting
nificant compared to the capacitor package induc- in a larger di/dt quantity. This will increase the number
tance. Therefore, for surface plane decoupling, assume of decoupling caps needed for V2.5.
Leq = Lpackage. Given this assumption, the 0603 capaci- It is also difficult to predict what value should be
tor count for MVTT would be 31. For internal planes, used for dt. This is highly dependent on the strength of
the 0603 capacitor count equals 63. Because the toler- the driver being used and will vary greatly from one
ance on MVTT is so tight, it is recommended that a product family to another. Even in a fully loaded con-
surface plane or some other method of lowering via figuration, some devices have been measured to have
inductance be used. edge rates of 2 V/ns, effectively switching in half the
time. These devices meet all of the minimum specs for
Exceptions and Variations DDR SDRAMs and might run in the same system with
The equations presented here use a linear approxi- devices that only drive 1 V/ns. But the faster devices
mation of differential quantities such as di/dt. More switch the same amount of current over a lower dt
in-depth calculations can be done to get more accu- time, hence they generate significantly more switching
rate predictions. Additionally, each net was assumed to noise and, consequently, may require additional
be equally loaded and of the same type. In an unbuf- decoupling to compensate for the driver strength.
fered DDR channel, address, control, and clock signals It is recommended that some experimentation be
will be more heavily loaded than data or strobes. These done to determine the right amount of decoupling
signals are also unidirectional from controller to RAM, needed. Use the equations and the most accurate data
and they run at half the speed of data and strobes. Sep- sheet information available to design a first prototype.
arate calculations can be done to more accurately pre- Then, measure noise levels on MVTT and V2.5, and
dict the current flow for these nets. edge rates of data and strobes to correlate noise with
The capacitor quantities in this example are very decoupling amounts. New calculations based on these
dependent on the device parameters used in the calcu- new measurements will give a more accurate estimate
lation. This analysis should be done for each new of the decoupling needs of the design.
design as device parameters may be different and will

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TBD Micron Technology, Inc., reserves the right to change products or specifications without notice.
TN4602.fm - Rev. B 7/04 EN 3 2000 Micron Technology, Inc. All rights reserved.