1 Typical On Resistance, 5 V, +12 V,

+5 V, and +3.3 V Quad SPST Switches

ADG1611/ADG1612/ADG1613
FEATURES FUNCTIONAL BLOCK DIAGRAMS
S1
1 typical on resistance
IN1
0.2 on resistance flatness D1
3.3 V to 8 V dual-supply operation S2
3.3 V to 16 V single-supply operation IN2

No VL supply required D2
ADG1611
3 V logic-compatible inputs S3
IN3
Rail-to-rail operation D3
Continuous current per channel S4
LFCSP package: 280 mA IN4
TSSOP package: 175 mA D4

07981-001
16-lead TSSOP and 16-lead, 4 mm 4 mm LFCSP NOTES
1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.
APPLICATIONS Figure 1.

Communication systems S1
IN1
Medical systems
D1
Audio signal routing
S2
Video signal routing IN2
Automatic test equipment D2
ADG1612
Data acquisition systems S3
IN3
Battery-powered systems
D3
Sample-and-hold systems
S4
Relay replacements IN4
D4
GENERAL DESCRIPTION

07981-033
NOTES
The ADG1611/ADG1612/ADG1613 contain four independent 1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.
single-pole/single-throw (SPST) switches. The ADG1611 and Figure 2.
ADG1612 differ only in that the digital control logic is inverted. S1
The ADG1611 switches are turned on with Logic 0 on the IN1
D1
appropriate control input, while Logic 1 is required for the
S2
ADG1612 switches. The ADG1613 has two switches with IN2
digital control logic similar to that of the ADG1611; the logic is D2
ADG1613
inverted on the other two switches. Each switch conducts equally S3
well in both directions when on and has an input signal range that IN3
D3
extends to the supplies. In the off condition, signal levels up to
S4
the supplies are blocked. IN4

The ADG1613 exhibits break-before-make switching action for use D4

07981-034

in multiplexer applications. Inherent in the design is the low charge NOTES

1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.
injection for minimum transients when switching the digital inputs. Figure 3.
The ultralow on resistance of these switches make them ideal PRODUCT HIGHLIGHTS
solutions for data acquisition and gain switching applications
1. 1.6 maximum on resistance over temperature.
where low on resistance and distortion is critical. The on resistance
2. Minimum distortion: THD + N = 0.007%.
profile is very flat over the full analog input range, ensuring
3. 3 V logic-compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V.
excellent linearity and low distortion when switching audio signals.
4. No VL logic power supply required.
The CMOS construction ensures ultralow power dissipation, making 5. Ultralow power dissipation: <16 nW.
them ideally suited for portable and battery-powered instruments. 6. 16-lead TSSOP and 16-lead, 4 mm 4 mm LFCSP.

Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 2009 Analog Devices, Inc. All rights reserved.
ADG1611/ADG1612/ADG1613

TABLE OF CONTENTS
Features .............................................................................................. 1 3.3 V Single Supply........................................................................6
Applications ....................................................................................... 1 Continuous Current per Channel, S or D ..................................7
General Description ......................................................................... 1 Absolute Maximum Ratings ............................................................8
Functional Block Diagrams ............................................................... 1 ESD Caution...................................................................................8
Product Highlights ........................................................................... 1 Pin Configurations and Function Descriptions ............................9
Revision History ............................................................................... 2 Typical Performance Characteristics ........................................... 10
Specifications..................................................................................... 3 Test Circuits ..................................................................................... 13
5 V Dual Supply ......................................................................... 3 Terminology .................................................................................... 15
12 V Single Supply ........................................................................ 4 Outline Dimensions ....................................................................... 16
5 V Single Supply .......................................................................... 5 Ordering Guide .......................................................................... 16

REVISION HISTORY
9/09Rev. 0 to Rev. A
Changes to On Resistance (RON) Parameter, On Resistance Match
Between Channels (RON) Parameter, and On Resistance Flatness
(RFLATON) Parameter, Table 4 ............................................................ 6
Changes to Figure 7 Caption ......................................................... 10

1/09Revision 0: Initial Version

Rev. A | Page 2 of 16
 ADG1611/ADG1612/ADG1613

SPECIFICATIONS
5 V DUAL SUPPLY
VDD = +5 V 10%, VSS = 5 V 10%, GND = 0 V, unless otherwise noted.

Table 1.
40C to 40C to
Parameter 25C +85C +125C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance (RON) 1 typ VS = 4.5 V, IS = 10 mA; see Figure 24
1.2 1.4 1.6 max VDD = 4.5 V, VSS = 4.5 V
On Resistance Match Between Channels (RON) 0.04 typ VS = 4.5 V, IS = 10 mA
0.08 0.09 0.1 max
On Resistance Flatness (RFLAT(ON)) 0.2 typ VS = 4.5 V, IS = 10 mA
0.25 0.29 0.34 max
LEAKAGE CURRENTS VDD = +5.5 V, VSS = 5.5 V
Source Off Leakage, IS (Off ) 0.1 nA typ VS = 4.5 V, VD = 4.5 V; see Figure 25
0.3 1 6 nA max
Drain Off Leakage, ID (Off ) 0.1 nA typ VS = 4.5 V, VD = 4.5 V; see Figure 25
0.3 1 6 nA max
Channel On Leakage, ID, IS (On) 0.2 nA typ VS = VD = 4.5 V; see Figure 26
0.4 1.5 10 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH +0.005 0.1 A typ VIN = VGND or VDD
0.1 A max
Digital Input Capacitance, CIN 5 pF typ
DYNAMIC CHARACTERISTICS 1
tON 165 ns typ RL = 300 , CL = 35 pF
212 253 285 ns max VS = 2.5 V; see Figure 31
tOFF 105 ns typ RL = 300 , CL = 35 pF
137 150 159 ns max VS = 2.5 V; see Figure 31
Break-Before-Make Time Delay, tD (ADG1613 Only) 25 ns typ RL = 300 , CL = 35 pF
20 ns min VS1 = VS2 = 2.5 V; see Figure 32
Charge Injection 140 pC typ VS = 0 V, RS = 0 , CL = 1 nF; see Figure 33
Off Isolation 70 dB typ RL = 50 , CL = 5 pF, f = 1 MHz;
see Figure 27
Channel-to-Channel Crosstalk 110 dB typ RL = 50 , CL = 5 pF, f = 1 MHz;
see Figure 28
Total Harmonic Distortion + Noise (THD + N) 0.007 % typ RL = 110 , 5 V p-p, f = 20 Hz to 20 kHz;
see Figure 30
3 dB Bandwidth 42 MHz typ RL = 50 , CL = 5 pF; see Figure 29
CS (Off ) 63 pF typ VS = 0 V, f = 1 MHz
CD (Off ) 63 pF typ VS = 0 V, f = 1 MHz
CD, CS (On) 154 pF typ VS = 0 V, f = 1 MHz
POWER REQUIREMENTS VDD = +5.5 V, VSS = 5.5 V
IDD 0.001 A typ Digital inputs = 0 V or VDD
1.0 A max
VDD/VSS 3.3/8 V min/max
1
Guaranteed by design, not subject to production test.

Rev. A | Page 3 of 16
ADG1611/ADG1612/ADG1613
12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 2.
40C to 40C to
Parameter 25C +85C +125C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance (RON) 0.95 typ VS = 0 V to 10 V, IS = 10 mA; see Figure 24
1.1 1.25 1.45 max VDD = 10.8 V, VSS = 0 V
On Resistance Match Between Channels (RON) 0.03 typ VS = 0 V to 10 V, IS = 10 mA
0.06 0.7 0.08 max
On Resistance Flatness (RFLAT(ON)) 0.2 typ VS = 0 V to 10 V, IS = 10 mA
0.23 0.27 0.32 max
LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V
Source Off Leakage, IS (Off ) 0.1 nA typ VS = 1 V/10 V, VS = 10 V/1 V, see Figure 25
0.3 1 6 nA max
Drain Off Leakage, ID (Off ) 0.1 nA typ VS = 1 V/10 V, VS = 10 V/1 V see Figure 25
0.3 1 6 nA max
Channel On Leakage, ID, IS (On) 0.2 nA typ VS = VD = 1 V or 10 V; see Figure 26
0.4 1.5 10 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.001 A typ VIN = VGND or VDD
0.1 A max
Digital Input Capacitance, CIN 5 pF typ
DYNAMIC CHARACTERISTICS 1
tON 125 ns typ RL = 300 , CL = 35 pF
156 190 215 ns max VS = 8 V; see Figure 31
tOFF 75 ns typ RL = 300 , CL = 35 pF
87 93 99 ns max VS = 8 V; see Figure 31
Break-Before-Make Time Delay, tD (ADG1613 Only) 35 ns typ RL = 300 , CL = 35 pF
30 ns min VS1 = VS2 = 8 V; see Figure 32
Charge Injection 170 pC typ VS = 6 V, RS = 0 , CL = 1 nF; see Figure 33
Off Isolation 70 dB typ RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 27
Channel-to-Channel Crosstalk 110 dB typ RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 28
Total Harmonic Distortion + Noise 0.012 % typ RL = 110 , 5 V p-p, f = 20 Hz to 20 kHz;
see Figure 30
3 dB Bandwidth 38 MHz typ RL = 50 , CL = 5 pF; see Figure 29
CS (Off ) 60 pF typ VS = 6 V, f = 1 MHz
CD (Off ) 60 pF typ VS = 6 V, f = 1 MHz
CD, CS (On) 154 pF typ VS = 6 V, f = 1 MHz
POWER REQUIREMENTS VDD = 12 V
IDD 0.001 A typ Digital inputs = 0 V or VDD
1 A max
IDD 320 A typ Digital inputs = 5 V
480 A max
VDD 3.3/16 V min/max
1
Guaranteed by design, not subject to production test.

Rev. A | Page 4 of 16
 ADG1611/ADG1612/ADG1613
5 V SINGLE SUPPLY
VDD = 5 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 3.
40C to 40C to
Parameter 25C +85C 125C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance (RON) 1.7 typ VS = 0 V to 4.5 V, IS = 10 mA; see Figure 24
2.15 2.4 2.7 max VDD = 4.5 V, VSS = 0 V
On Resistance Match Between Channels (RON) 0.05 typ VS = 0 V to 4.5 V, IS = 10 mA
0.09 0.12 0.15 max
On Resistance Flatness (RFLAT(ON)) 0.4 typ VS = 0 V to 4.5 V, IS = 10 mA
0.53 0.55 0.6 max
LEAKAGE CURRENTS VDD = 5.5 V, VSS = 0 V
Source Off Leakage, IS (Off ) 0.05 nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 25
0.3 1 6 nA max
Drain Off Leakage, ID (Off ) 0.05 nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 25
0.3 1 6 nA max
Channel On Leakage, ID, IS (On) 0.15 nA typ VS = VD = 1 V or 4.5 V; see Figure 26
0.4 1.5 10 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.001 A typ VIN = VGND or VDD
0.1 A max
Digital Input Capacitance, CIN 5 pF typ
DYNAMIC CHARACTERISTICS 1
tON 215 ns typ RL = 300 , CL = 35 pF
279 334 376 ns max VS = 2.5 V; see Figure 31
tOFF 115 ns typ RL = 300 , CL = 35 pF
150 169 180 ns max VS = 2.5 V; see Figure 31
Break-Before-Make Time Delay, tD (ADG1613 Only) 35 ns typ RL = 300 , CL = 35 pF
25 ns min VS1 = VS2 = 2.5 V; see Figure 32
Charge Injection 80 pC typ VS = 0 V, RS = 0 , CL = 1 nF; see Figure 33
Off Isolation 70 dB typ RL = 50 , CL = 5 pF, f = 100 kHz;
see Figure 27
Channel-to-Channel Crosstalk 110 dB typ RL = 50 , CL = 5 pF, f = 100 kHz;
see Figure 28
Total Harmonic Distortion + Noise 0.093 % typ RL = 110 , f = 20 Hz to 20 kHz,
VS = 3.5 V p-p; see Figure 30
3 dB Bandwidth 42 MHz typ RL = 50 , CL = 5 pF; see Figure 29
CS (Off ) 72 pF typ VS = 2.5 V, f = 1 MHz
CD (Off ) 72 pF typ VS = 2.5 V, f = 1 MHz
CD, CS (On) 160 pF typ VS = 2.5 V, f = 1 MHz
POWER REQUIREMENTS VDD = 5.5 V
IDD 0.001 A typ Digital inputs = 0 V or VDD
1 A max
VDD 3.3/16 V min/max
1
Guaranteed by design, not subject to production test.

Rev. A | Page 5 of 16
ADG1611/ADG1612/ADG1613
3.3 V SINGLE SUPPLY
VDD = 3.3 V, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 4.
40C to 40C to
Parameter 25C +85C +125C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance (RON) 3.2 3.4 3.6 typ VS = 0 V to VDD, IS = 10 mA, VDD = 3.3 V,
VSS = 0 V; see Figure 24
On Resistance Match Between Channels (RON) 0.06 0.07 0.08 typ VS = 0 V to VDD, IS = 10 mA
On Resistance Flatness (RFLAT(ON)) 1.2 1.3 1.4 typ VS = 0 V to VDD, IS = 10 mA
LEAKAGE CURRENTS VDD = 3.6 V, VSS = 0 V
Source Off Leakage, IS (Off ) 0.02 nA typ VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 25
0.3 1 6 nA max
Drain Off Leakage, ID (Off ) 0.02 nA typ VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 25
0.3 1 6 nA max
Channel On Leakage, ID, IS (On) 0.1 nA typ VS = VD = 0.6 V or 3 V; see Figure 26
0.4 1.5 10 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.001 A typ VIN = VGND or VDD
0.1 A max
Digital Input Capacitance, CIN 3 pF typ
DYNAMIC CHARACTERISTICS 1
tON 350 ns typ RL = 300 , CL = 35 pF
493 556 603 ns max VS = 1.5 V; see Figure 31
tOFF 190 ns typ RL = 300 , CL = 35 pF
263 286 300 ns max VS = 1.5 V; see Figure 31
Break-Before-Make Time Delay, tD (ADG1613 Only) 25 ns typ RL = 300 , CL = 35 pF
18 ns min VS1 = VS2 = 1.5 V; see Figure 32
Charge Injection 50 pC typ VS = 1.5 V, RS = 0 , CL = 1 nF; see Figure 33
Off Isolation 70 dB typ RL = 50 , CL = 5 pF, f = 100 kHz;
see Figure 27
Channel-to-Channel Crosstalk 110 dB typ RL = 50 , CL = 5 pF, f = 100 kHz;
see Figure 28
Total Harmonic Distortion + Noise 0.18 % typ RL = 110 , f = 20 Hz to 20 kHz,
VS = 2 V p-p; see Figure 30
3 dB Bandwidth 52 MHz typ RL = 50 , CL = 5 pF; see Figure 29
CS (Off ) 76 pF typ VS = 1.5 V, f = 1 MHz
CD (Off ) 76 pF typ VS = 1.5 V, f = 1 MHz
CD, CS (On) 160 pF typ VS = 1.5 V, f = 1 MHz
POWER REQUIREMENTS VDD = 3.6 V
IDD 0.001 A typ Digital inputs = 0 V or VDD
1.0 1.0 A max
VDD 3.3/16 V min/max
1
Guaranteed by design, not subject to production test.

Rev. A | Page 6 of 16
 ADG1611/ADG1612/ADG1613
CONTINUOUS CURRENT PER CHANNEL, S OR D
Table 5.
Parameter 25C 85C 125C Unit
CONTINUOUS CURRENT, S OR D
VDD = +5 V, VSS = 5 V
TSSOP (JA = 150.4C/W) 175 119 70 mA maximum
LFCSP (JA = 48.7C/W) 280 175 95 mA maximum
VDD = 12 V, VSS = 0 V
TSSOP (JA = 150.4C/W) 206 135 84 mA maximum
LFCSP (JA = 48.7C/W) 336 203 108 mA maximum
VDD = 5 V, VSS = 0 V
TSSOP (JA = 150.4C/W) 140 91 63 mA maximum
LFCSP (JA = 48.7C/W) 220 140 84 mA maximum
VDD = 3.3 V, VSS = 0 V
TSSOP (JA = 150.4C/W) 140 98 70 mA maximum
LFCSP (JA = 48.7C/W) 228 150 91 mA maximum

Rev. A | Page 7 of 16
ADG1611/ADG1612/ADG1613

ABSOLUTE MAXIMUM RATINGS

TA = 25C, unless otherwise noted.

Table 6. Stresses above those listed under Absolute Maximum Ratings

Parameter Rating may cause permanent damage to the device. This is a stress
VDD to VSS 18 V rating only; functional operation of the device at these or any
VDD to GND 0.3 V to +18 V other conditions above those indicated in the operational
VSS to GND +0.3 V to 18 V section of this specification is not implied. Exposure to absolute
Analog Inputs 1 VSS 0.3 V to VDD + 0.3 V or maximum rating conditions for extended periods may affect
30 mA, whichever occurs first device reliability.
Digital Inputs1 GND 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Peak Current, S or D 630 mA (pulsed at 1 ms, ESD CAUTION
10% duty-cycle maximum)
Continuous Current, S or D 2 Data + 15%
Operating Temperature Range
Industrial (Y Version) 40C to +125C
Storage Temperature Range 65C to +150C
Junction Temperature 150C
16-Lead TSSOP, JA Thermal 150.4C/W
Impedance (2-Layer Board)
16-Lead LFCSP, JA Thermal 48.7C/W
Impedance (4-Layer Board)
Reflow Soldering Peak 260C
Temperature, Pb free
1
Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
2
See Table 5.

Rev. A | Page 8 of 16
 ADG1611/ADG1612/ADG1613

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

15 IN1
14 IN2
16 D1

13 D2
IN1 1 16 IN2
PIN 1
D1 2 15 D2 INDICATOR
S1 1 12 S2
S1 3 ADG1611/ 14 S2 VSS 2
ADG1611/ 11 VDD
ADG1612/ ADG1612/
VSS 4
ADG1613
13 VDD GND 3 ADG1613 10 NC
S4 4 TOP VIEW 9 S3
GND 5 TOP VIEW 12 NC (Not to Scale)
(Not to Scale)
S4 6 11 S3

D3 8
IN3 7
D4 5
IN4 6
D4 7 10 D3
IN4 8 9 IN3 07981-002

07981-003
NOTES
1. NC = NO CONNECT.
NC = NO CONNECT 2. EXPOSED PAD TIED TO SUBSTRATE, VSS.

Figure 4. 16-Lead TSSOP Pin Configuration Figure 5. 16-Lead LFCSP Pin Configuration

Table 7. Pin Function Descriptions

Pin No.
16-Lead TSSOP 16-Lead LFCSP Mnemonic Description
1 15 IN1 Logic Control Input.
2 16 D1 Drain Terminal. This pin can be an input or output.
3 1 S1 Source Terminal. This pin can be an input or output.
4 2 VSS Most Negative Power Supply Potential.
5 3 GND Ground (0 V) Reference.
6 4 S4 Source Terminal. This pin can be an input or output.
7 5 D4 Drain Terminal. This pin can be an input or output.
8 6 IN4 Logic Control Input.
9 7 IN3 Logic Control Input.
10 8 D3 Drain Terminal. This pin can be an input or output.
11 9 S3 Source Terminal. This pin can be an input or output.
12 10 NC No Connection.
13 11 VDD Most Positive Power Supply Potential.
14 12 S2 Source Terminal. This pin can be an input or output.
15 13 D2 Drain Terminal. This pin can be an input or output.
16 14 IN2 Logic Control Input.
N/A 17 (EPAD) EP (EPAD) Exposed Pad. Tied to substrate, VSS.

Table 8. ADG1611/ADG1612 Truth Table

ADG1611 INx ADG1612 INx Switch Condition
0 1 On
1 0 Off

Table 9. ADG1613 Truth Table

Logic (INx) Switch 1, Switch 4 Switch 2, Switch 3
0 Off On
1 On Off

Rev. A | Page 9 of 16
ADG1611/ADG1612/ADG1613

TYPICAL PERFORMANCE CHARACTERISTICS

1.4 1.4
TA = 25C VDD = 12V
VSS = 0V
VDD = +3.3V
VSS = 3.3V
1.2 1.2
TA = +125C
TA = +85C
TA = +25C

ON RESISTANCE ()
ON RESISTANCE ()

TA = 40C
1.0 1.0

VDD = +5V
VSS = 5V
0.8 0.8

VDD = +8V
VSS = 8V
0.6 0.6

0.4 0.4

07981-010
07981-013
8 6 4 2 0 2 4 6 8 0 2 4 6 8 10 12
VS OR VD VOLTAGE (V) VS OR VD VOLTAGE (V)

Figure 6. On Resistance as a Function of VD (VS) for Dual Supply Figure 9. On Resistance as a Function of VD (VS) for Different Temperatures,
12 V Single Supply
3.5 2.5
TA = 25C VDD = 5V
TA = +125C VSS = 0V
TA = +85C
3.0 TA = +25C
VDD = 3.3V TA = 40C
VSS = 0V
ON RESISTANCE ()

2.5
ON RESISTANCE ()

2.0

2.0
VDD = 5V
VSS = 0V
1.5 1.5

VDD = 12V
1.0 VSS = 0V VDD = 16V
VSS = 0V

0.5 1.0
07981-014

0 2 4 6 8 10 12 14 16

07981-012
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VS OR VD VOLTAGE (V) VS OR VD VOLTAGE (V)

Figure 7. On Resistance as a Function of VD (VS) for Single Supply Figure 10. On Resistance as a Function of VD (VS) for Different Temperatures,
5 V Single Supply

1.4 4.0
VDD = 3.3V
VSS = 0V

1.2 3.5
ON RESISTANCE ()
ON RESISTANCE ()

1.0 3.0

0.8 2.5 TA = +125C

TA = +85C
TA = +25C
TA = 40C
0.6 2.0
TA = +125C
TA = +85C
VDD = +5V TA = +25C
VSS = 5V TA = 40C
0.4 1.5
07981-006
07981-011

6 4 2 0 2 4 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

VS OR VD VOLTAGE (V) VS OR VD VOLTAGE (V)

Figure 11. On Resistance as a Function of VD (VS) for Different Temperatures,

Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures, 3.3 V Single Supply
5 V Dual Supply

Rev. A | Page 10 of 16
 ADG1611/ADG1612/ADG1613
20 18

16
15
ID, IS (ON) +, + 14
LEAKAGE CURRENT (nA)

LEAKAGE CURRENT (nA)

10 12 ID, IS (OFF) +, +
ID (OFF) , +
10
5 IS (OFF) +,
8 ID, IS (OFF) ,

6 ID (OFF) , +
0
4
ID, IS (ON) , IS (OFF) +,
5 2
IS (OFF) , +
0
10 ID (OFF) +, IS (OFF) , +
2
ID (OFF) +,
15 4

07981-032
0 20 40 60 80 100 120

07981-030
0 20 40 60 80 100 120
TEMPERATURE (C) TEMPERATURE (C)
Figure 12. Leakage Currents as a Function of Temperature, 5 V Dual Supply Figure 15. Leakage Currents as a Function of Temperature,
3.3 V Single Supply
25 600
IDD PER CHANNEL
20 TA = 25C
500
ID, IS (ON) +, + IDD = +12V
15 ISS = 0V
LEAKAGE CURRENT (nA)

400
10 ID (OFF) , +

5 IS (OFF) +, IDD (A) 300

0
200
IDD = +5V
5 ID, IS (ON) , ISS = 5V
IS (OFF) , + 100
10 IDD = +5V
ID (OFF) +, ISS = 0V
0
15
IDD = +3.3V
ISS = 0V
20 100
0 20 40 60 80 100 120
07981-031

07981-005
0 2 4 6 8 10 12
TEMPERATURE (C) LOGIC (V)

Figure 13. Leakage Currents as a Function of Temperature, Figure 16. IDD vs. Logic Level
12 V Single Supply

20 300

VDD = +5V
VSS = 5V
250
15
CHARGE INJECTION (pC)
LEAKAGE CURRENT (nA)

ID, IS (OFF) +, +
200
10
ID, IS (OFF) , 150
VDD = +12V
VSS = 0V
5
ID (OFF) , +
100

0 VDD = +5V
50 VSS = 0V
IS (OFF) +,
IS (OFF) , + VDD = +3.3V
ID (OFF) +, VSS = 0V
5 0
6 4 2 0 2 4 6 8 10 12 14
07981-019

07981-009

0 20 40 60 80 100 120
TEMPERATURE (C) VS (V)

Figure 14. Leakage Currents as a Function of Temperature, Figure 17. Charge Injection vs. Source Voltage (VS)
5 V Single Supply

Rev. A | Page 11 of 16
ADG1611/ADG1612/ADG1613
500 0
TA = 25C
450 VDD = +5V
VSS = 5V
1
400

350

INSERTION LOSS (dB)

tOFF (+3.3V) 2
300 tON (+3.3V)
TIME (ns)

tOFF (+5V)
250 tOFF (5V) 3

200
4
150

100
5
50 tON (+5V) tOFF (5V)
tOFF (+12V) tON (+12V)
0 6

07981-018

07981-004
60 40 20 0 20 40 60 80 100 120 140 1k 10k 100k 1M 10M 100M 1G
TEMPERATURE (C) FREQUENCY (Hz)

Figure 18. tON/tOFF Times vs. Temperature Figure 21. On Response vs. Frequency

5 0
T = 25C TA = 25C
10 VA = +5V
DD VDD = +5V
15 VSS = 5V VSS = 5V
20 20 NO DECOUPLING
CAPACITORS
25
30
OFF ISOLATION (dB)

40
35
ACPSRR (dB)

40
45 60
50 DECOUPLING
55 CAPACITORS
60 80
65
70
100
75
80
85 120
07981-007

1k 10k 100k 1M 10M 100M 1G

07981-008
1k 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 19. Off Isolation vs. Frequency Figure 22. ACPSRR vs. Frequency

0 0.20
TA = 25C
VDD = +5V 0.18
VSS = 5V VDD = +3.3V
20 VS = 2V
0.16 RL = 110
TA = 25C
40 0.14
CROSSTALK (dB)

0.12
THD + N (%)

60 VDD = +5V
0.10 VS = 3.5V
80
0.08

100 0.06
VDD = +12V VDD = +5V
0.04 VS = 5V p-p VSS = 5V
120 VS = 5V p-p
0.02

140 0
07981-016

0 5k 10k 15k 20k 25k

07981-017

1k 10k 100k 1M 10M 100M 1G

FREQUENCY (Hz) FREQUENCY (Hz)

Figure 20. Crosstalk vs. Frequency Figure 23. THD + N vs. Frequency

Rev. A | Page 12 of 16
 ADG1611/ADG1612/ADG1613

TEST CIRCUITS
VDD VSS
0.1F 0.1F

NETWORK
VDD VSS ANALYZER

IS
Sx 50
INx 50
VS

Dx
V1 VOUT
VIN RL
GND 50
Sx Dx

VOUT
VS RON = V1/IS

07981-026
07981-020
OFF ISOLATION = 20 log
VS

Figure 24. On Resistance Figure 27. Off Isolation

VDD VSS
0.1F 0.1F

NETWORK
ANALYZER VDD VSS
VOUT
RL S1
50
Dx RL
S2 50

VS
IS (OFF) ID (OFF) GND
Sx Dx
A A

VOUT
VS VD

07981-027
07981-021

CHANNEL-TO-CHANNEL CROSSTALK = 20 log

VS

Figure 25. Off Leakage Figure 28. Channel-to-Channel Crosstalk

VDD VSS
0.1F 0.1F

NETWORK
VDD VSS ANALYZER

Sx 50
INx
VS

Dx
VOUT
ID (ON) VIN RL
Sx Dx GND 50
NC A

VD
07981-022

07981-028

NC = NO CONNECT VOUT WITH SWITCH

INSERTION LOSS = 20 log
VOUT WITHOUT SWITCH

Figure 26. On Leakage Figure 29. Bandwidth

Rev. A | Page 13 of 16
ADG1611/ADG1612/ADG1613
VDD VSS
0.1F 0.1F

AUDIO PRECISION
VDD VSS
RS
Sx
INx
VS
V p-p
Dx
VOUT
VIN RL
110
GND

07981-029
Figure 30. THD + Noise

VDD VSS
0.1F 0.1F

VIN ADG1612 50% 50%

VDD VSS

Sx Dx VOUT
VIN 50% 50%
ADG1611
RL CL
VS
INx 300 35pF
90% 90%
VOUT
GND

07981-023
tON tOFF

Figure 31. Switching Times

VDD VSS
0.1F 0.1F VIN 50% 50%
0V

VDD VSS 90% 90%

S1 D1 VOUT1
VS1 VOUT1 0V
RL CL
S2 D2 300 35pF
VS2 VOUT2
RL CL
300 35pF 90% 90%
VOUT2
IN1, ADG1613 0V
IN2 GND tD tD

07981-024
Figure 32. Break-Before-Make Time Delay

VDD VSS

VDD VSS VIN ADG1612

ON OFF
RS Sx Dx VOUT

CL
VS VIN ADG1611
INx 1nF

VOUT
GND VOUT
QINJ = CL VOUT
07981-025

Figure 33. Charge Injection

Rev. A | Page 14 of 16
 ADG1611/ADG1612/ADG1613

TERMINOLOGY
IDD tON
The positive supply current. The delay between applying the digital control input and the
ISS output switching on. See Figure 31.
The negative supply current. tOFF
VD (VS) The delay between applying the digital control input and the
The analog voltage on Terminal D and Terminal S. output switching off. See Figure 31.

RON Charge Injection

The ohmic resistance between Terminal D and Terminal S. A measure of the glitch impulse transferred from the digital
input to the analog output during switching. See Figure 33.
RFLAT(ON)
Flatness that is defined as the difference between the maximum Off Isolation
and minimum value of on resistance measured over the specified A measure of unwanted signal coupling through an off switch.
analog signal range. See Figure 27.

IS (Off) Crosstalk
The source leakage current with the switch off. A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance. See
ID (Off) Figure 28.
The drain leakage current with the switch off.
Bandwidth
ID, IS (On) The frequency at which the output is attenuated by 3 dB. See
The channel leakage current with the switch on. Figure 29.
VINL On Response
The maximum input voltage for Logic 0. The frequency response of the on switch.
VINH Insertion Loss
The minimum input voltage for Logic 1. The loss due to the on resistance of the switch.
IINL (IINH) Total Harmonic Distortion + Noise (THD + N)
The input current of the digital input. The ratio of the harmonic amplitude plus noise of the signal to
CS (Off) the fundamental. See Figure 30.
The off switch source capacitance, which is measured with AC Power Supply Rejection Ratio (ACPSRR)
reference to ground. The ratio of the amplitude of signal on the output to the amplitude
CD (Off) of the modulation. This is a measure of the ability of the part to
The off switch drain capacitance, which is measured with avoid coupling noise and spurious signals that appear on the supply
reference to ground. voltage pin to the output of the switch. The dc voltage on the device
CD, CS (On) is modulated by a sine wave of 0.62 V p-p.
The on switch capacitance, which is measured with reference to
ground.
CIN
The digital input capacitance.

Rev. A | Page 15 of 16
ADG1611/ADG1612/ADG1613

OUTLINE DIMENSIONS
5.10
5.00
4.90

16 9

4.50
6.40
4.40 BSC
4.30
1 8

PIN 1
1.20
MAX
0.15 0.20
0.05 0.09 0.75
0.30 8 0.60
0.65 0.19 0 0.45
SEATING
BSC PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 34. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
0.50
0.40
4.00 0.60 MAX 0.30
BSC SQ PIN 1
INDICATOR

12 13 16 1

PIN 1 3.75 2.65

INDICATOR EXPOSED 2.50 SQ
BSC SQ PAD
2.35
4
0.65 9 8 5
BSC 0.25 MIN
TOP VIEW 1.95 BCS
BOTTOM VIEW
12 MAX 0.80 MAX
1.00 0.65 TYP FOR PROPER CONNECTION OF
0.85 THE EXPOSED PAD, REFER TO
0.05 MAX THE PIN CONFIGURATION AND
0.80
0.02 NOM FUNCTION DESCRIPTIONS
SEATING SECTION OF THIS DATA SHEET.
PLANE 0.30 COPLANARITY
0.20 REF 0.08
0.23
0.18
031006-A

COMPLIANT TO JEDEC STANDARDS MO-220-VGGC.

Figure 35. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm 4 mm Body, Very Thin Quad (CP-16-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADG1611BRUZ 1 40C to +125C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1611BRUZ-REEL1 40C to +125C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1611BRUZ-REEL71 40C to +125C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1611BCPZ-REEL1 40C to +125C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-13
ADG1611BCPZ-REEL71 40C to +125C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-13
ADG1612BRUZ1 40C to +125C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1612BRUZ-REEL1 40C to +125C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1612BRUZ-REEL71 40C to +125C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1612BCPZ- REEL1 40C to +125C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-13
ADG1612BCPZ-REEL71 40C to +125C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-13
ADG1613BRUZ1 40C to +125C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1613BRUZ-REEL1 40C to +125C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1613BRUZ-REEL71 40C to +125C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1613BCPZ-REEL1 40C to +125C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-13
ADG1613BCPZ-REEL71 40C to +125C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-13
1
Z = RoHS Compliant Part.

2009 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D07981-0-9/09(A)

Rev. A | Page 16 of 16