14

Power Inverters
Inversion is the conversion of dc power to ac power at a desired output voltage or
current and frequency. A static inverter circuit performs this transformation.
The terms voltage-fed and current-fed are used in connection with inverter circuits.
A voltage-fed inverter is one in which the dc input voltage is essentially constant
and independent of the load current drawn. The inverter specifies the load voltage
while the drawn current shape is dictated by the load.
A current-fed inverter (or current source inverter) is one in which the source, hence
the load current is predetermined and the load impedance determines the output
voltage. The supply current cannot change quickly. This is achieved by series dc
supply inductance which prevents sudden changes in current. The load current
magnitude is controlled by varying the input dc voltage to the large inductance,
hence inverter response to load changes is slow. Being a current source, the
inverter can survive an output short circuit thereby offering fault ride-through
properties.
Voltage control may be required to maintain a fixed output voltage when the dc
input voltage regulation is poor, or to control power to a load. The inverter and its
output can be single-phase, three-phase or multi-phase. Variable output frequency
may be required for ac motor speed control where, in conjunction with voltage or
current control, constant motor flux can be maintained.
Inverter output waveforms are usually rectilinear in nature and as such contain
harmonics which may lead to reduced load efficiency and performance. Load
harmonic reduction can be achieved by either filtering, selected harmonicreduction chopping or pulse-width modulation.
The quality of an inverter output is normally evaluated in terms of its harmonic
factor, ?, distortion factor, , and total harmonic distortion, thd. In section 12.6.2
these first two factors were defined in terms of the supply current. For inverters the
factors are redefined in terms of the output voltage harmonics as follows

n =

Vn
= n n
V1

n >1

(14.1)

Power Electronics

413

The distortion factor for an individual harmonic is

n =

Vn

= n
nV1
n

(14.2)

V 2
n
thd = n / V1 =
n2 =
(14.3)

n 2
n 2 n
n2 n
The factor Vn /n is used since the harmonic currents produced in an inductive load
attenuate with frequency. The harmonic currents produce unwanted heating and
torque oscillations in ac motors, although such harmonic currents are not a
drawback to the power delivered to a resistive heating load.

14.1

dc-to-ac voltage-fed inverter bridge topologies

14.1.1

Single-phase voltage-fed inverter bridge

Figure 14.la shows an H-bridge inverter for producing an ac voltage and

employing switches which may be transistors (MOSFET or IGBT ), or at high
powers, thyristors (GTO or CGT). Device conduction patterns are also shown in
figures 14.lb and c. With inductive loads (not purely resistive), stored energy at
turn-off is fed through the bridge reactive feedback or freewheel diodes D1 to D4 .
These four diodes clamp the load voltage to within the dc supply rails (0 to Vs ).
14.1.1i - Square-wave output
Figure 14.lb shows waveforms for a square-wave output (2t1 =t2 ) where each device
is turned on as appropriate for 180, (that is p) of the output voltage cycle (state
sequence 10, 01, 10, ..). The load current iL grows exponentially through T1 and T2
(state 10) according to
di
Vs = L L + iLR
(V)
(14.4)
dt
When T1 and T2 are turned off, T3 and T4 are turned on (state 01), thereby reversing
the load voltage. Because of the inductive nature of the load, the load current
cannot reverse and load reactive energy flows back into the supply via diodes D3
and D4 (which are in parallel with T3 and T4 respectively) according to
di
Vs = L L + iLR
(V)
(14.5)
dt
The load current falls exponentially and at zero, T3 and T4 become forward-biased
and conduct load current, thereby feeding power to the load.
The output voltage is a square wave of magnitude Vs and has an rms value of Vs .
For a simple R-L load, with time constant t = L /R, during the first cycle with no
initial load current, solving equation (14.4) yields a load current
t
V

iL ( t) = s 1 e
(A)
(14.6)
R

Under steady-state load conditions, the initial current is I as shown in figure 14.lb,
and equation (14.4) yields

Power Inverters

414

I1

Figure 14.1. GCT thyristor single-phase bridge inverter: (a) circuit diagram;
(b) square-wave output voltage; and (c) quasi-square-wave output voltage.

iL ( t) =

for

vL = Vs

Vs Vs t

I e
R R

0 t t1

(A)

(14.7)

(s)

(V)

I 0

(A)

During the second half-cycle (t1 = t = t2 ) when the supply is effectively reversed
across the load, equation (14.5) yields

Power Electronics

415

iL ( t) =

for

vL = Vs

Vs Vs t
+
+ I e
R R

0 t t2 t1

(A)

(14.8)

(s)

(V)

I 0
(A)
A new time axis has been used in equation (14.8)
starting at t = t1 in figure 14.lb.

Since I = - I , the initial

steady-state
current
I
can
be found from equation (14.7)

when, at t = t1 , i L = I yielding
t1

V 1 e Vs
t
I = s
tanh 1
(A)
(14.9)
t =
R
R
2
1+ e
The zero current cross-over point tx, shown on figure 14.1b, can be found by
solving equation (14.7) for t when iL = 0, which yields
I R

tx = ln 1

Vs

(14.10)
$
IR
= ln 1 +
(s)
V
s

The average thyristor current, I TH , average diode current, I D , and mean source
current, I s can be found by integration of the load current over the appropriated
bounds.
1 t
I T = iL ( t ) dt
t2 t
(14.11)
t
1 V
V
t

= s ( t1 to ) + s + $I e e
t2 R
R

where iL is given by equation (14.7) and

1 t
I D = iL ( t ) dt
t2 0
(14.12)
1 Vs
Vs $ t

= t x + I e 1
t2 R
R

where iL is given by equation (14.8)

Inspection of the source current waveform in figure 14.1b shows that the average
source current is related to the average semiconductor device currents by

I s = 2 I TH I D

(14.13)
1 Vs
Vs $ t

t1 + + I e 1
t2 R
R

The steady-state mean power delivered by the dc supply and absorbed by the
resistive load component is given by

Power Inverters

416

1 t
Vs iL( t ) dt = Vs I s
(W)
(14.14)
t1 0
where iL(t) is given by equation (14.7).
The rms output voltage is Vs and the output fundamental frequency fo is
fo = 12t1 = 1t2 .
The instantaneous output voltage expressed as a Fourier series is given by

1
4
VL = Vs
sin nt
(V)
(14.15)
nodd n
and for n = 1 the output rms fundamental voltage vo1 is
2 2
vo 1 =
V = 0.90Vs
(V)
(14.16)
s
The load current can be expressed in terms of the Fourier voltage waveform series,
that is
4 1
iL (t ) = Vs
sin ( nt n )
(14.17)
n =1 nZ n
PL =

where Z n = R 2 + ( n L ) 2
n = tan 1 n L

14.1.1ii - Quasi-square-wave output

The rms output voltage can be varied by producing a quasi-square output voltage
(2t1 =t2 , t0 <t1 ) as shown in figure 14.1c. After T1 and T2 have been turned on (state
10), at the angle p-a one device is turned off. If T1 is turned off, the load current
slowly freewheels through T2 and D4 (state 00) in a zero voltage loop according to
di
0 = L L + iL R
(V)
(14.18)
dt
When T 2 is turned off and T4 and T3 turned on (state 01), the remaining load current
rapidly reduces to zero through diodes D3 and D4 . When the load current reaches
zero, T3 and T4 become forward biased and the output current reverses through T3
and T4 .
The output voltage shown in figure 14.lc consists of a sequence of non-zero
voltages Vs , alternated with zero output voltage periods. During the zero output
period a diode and switch conduct, firstly T1 and D3 in the first period, and T3 and
D1 in the second zero output period. In each case, a zero voltage loop is formed by
a switch, diode, and the load. The next two zero output sequences would be T2 and
D4 then T4 and D2 , forming alternating zero voltage loops (sequence 10, 00, 01, 11,
10, ..) rather than repeating a continuous T1 and D3 then T3 and D1 sequence of zero
voltage loops (sequence 10, 11, 01, 11, 10, .. or sequence 10, 00, 01, 00, 10, ..). By
alternating the zero voltage loops (between states 00 and 11), losses are uniformly
distributed between the semi conductors, device switching frequency is half that
experienced by the load, and a finer output voltage resolution is achievable.
With reference to figure 14.lc, the load current iL for an applied quasi square-wave
voltage is defined as follows.

Power Electronics

417

(i) vL > 0

Vs Vs
t
Io e
R R

for I o 0
(A)
(ii) vL = 0
iL (t ) =

0 t to

(14.19)

0 t t1 to

(14.20)

iLI I (t ) = I e

for I 0

(A)

(iii) vL < 0

Vs Vs
t
+ + I1 e = iL ( t)
R R

I1 0
(A)

iL ( t) =

for

0 t to

(14.21)

The currents I o , I , and I1 are given by

V e
Io = s
R

t1 + to

t1

(A)

t1

(14.22)

1+ e

to

V 1 e
I = s
(A)
(14.23)
t

R
1+e
I1 = Io
(A)
(14.24)
The zero current cross-over instant, tx, shown in figure 14.1c, is found by solving
equation (14.19) for t when iL equals zero current.
I R
tx = ln 1 o
(14.25)
Vs

The average thyristor current, I TH , average diode current, I D , and mean source
current, I s can be found by integration of the load current over the appropriated
bounds (assuming alternating zero volt loops).
1 t
1 t t
IT =
iL ( t ) dt +
iL ( t ) dt
(14.26)
t
t2
2t2 0
where iL is given by equations (14.19) and (14.20) for the respective integrals, and
1 t
1 t t
ID =
iL ( t ) dt +
iL ( t ) dt
(14.27)
0
t2
2t2 0
where iL is given by equations (14.19) and (14.20) for the respective integrals.
Inspection of the source current waveform in figure 14.1b shows that the average
source current is related to the average semiconductor device currents by
1 to
Is =
iL ( t) dt = 2 I TH I D
(14.28)
t1 0
The steady-state mean load and source powers are
1 t
PL =
Vs iL( t ) dt = Vs I s
(W)
(14.29)
t1 0

II

1 o

II

Power Inverters

418

where iL(t) is given by equation (14.19).

The variable rms output voltage is

vrms =

1
t1

to
0

Vs 2 dt

= 1 Vs
and the output fundamental frequency fo is fo = 1t2 .
The output voltage VL in its Fourier coefficient series form is given by

4
cosn
VL = Vs
sin nt
(V)
nodd n
and for n = 1, the rms fundamental of the output voltage vo1 is given by

(14.30)

(14.31)

2 2
Vs cos = 0.90 Vs cos
(V)
(14.32)

The load current can be expressed in terms of the Fourier voltage waveform series,
that is

4
cosn
iL ( t) = Vs
sin ( n t n )
(14.33)
n =1,3,.. nZ n
vo 1 =

where Z n = R 2 + ( n L ) 2
n = tan 1 n L

A variation of the basic four-switch dc to ac single-phase H-bridge is the halfbridge version where two series switches (one pole or leg) and diodes are replaced
by a split two-capacitor source, as shown in figure 14.2a . This reduces the number
of semiconductors and gate circuit requirements, but at the expense of halving the
maximum output voltage. Example 14.3 illustrates the half-bridge and its essential
features. Behaviour characteristics are as for the full-bridge, square-wave, singlephase inverter but Vs is replaced by Vs in the appropriate equations. Only a
square-wave output voltage can be obtained. Since zero volt loops cannot be
created, no rms voltage control is possible. The rms output voltage is Vs .
Example 14.1:

Single-phase H-bridge with an L-R load

A single-phase H-bridge inverter, as shown in figure 14.la, supplies a 10 ohm

resistance with inductance 50 mH from a 340 V dc source. If the bridge is
operating at 50 Hz, determine the load rms voltage and steady-state current
waveforms with
i.
a square-wave output
ii.
a quasi-square-wave output with a 50 per cent on-time.
Solution
The time constant of the load, t = 0.05mH/10O = 5 ms and t2 = 20ms .
i. The output voltage rms value is 340 V ac.
Equation (14.9) gives the load current at the time when the supply polarity is
reversed across the load, as shown in figure 14.lb, that is

Power Electronics

419

to

V 1 e
I = I = s
(A)
t
R
1+e
where t1 = 10 ms. Therefore

340V 1 e 2
I = I =

(A)
10O 1 + e2
= 25.9A
When vL = +340 V, from equation (14.7) the load current is given by
iL = 34-(34 + 25.9) e-200 t = 34-59.9 e-200 t
0 t 10 ms

From equation (14.10) the zero current cross-over time, tx, occurs at
5ms ln (1 + 25.9A10O/340V ) = 2.83 ms after load voltage reversal.
When vL = -340 V, from equation (14.8) the load current is given by
iL = -34 + (34 + 25.9) e-200 t = -34 + 59.9 e-200 t
0 t 10 ms
The mean power delivered to the load is given by equation (14.14), that is
10 ms
1
PL =
340V {34 - 59.9 e-200t } dt
0
10ms
= 2755 W

ii. The quasi-square output voltage has a 5 ms on-time , to , and a 5 ms period of

zero volts.
From equation (14.30) the rms output voltage is
Vs 1 5ms/10ms = Vs 2 = 240V rms .
The current during the different intervals is specified by equations (14.19) to
(14.24). Alternately, the steady-state load current equations can be specified by
determining the load current equations for the first few cycles at start-up until
steady-state conditions are attained.
First 5 ms on-period when vL = 340 V and initially iL = 0 A
iL = 34 - 34 e -200t
and at 5ms, iL = 21.5A
First 5 ms zero-period when vL = 0 V
iL = 21.5 e-200t
and at 5ms, iL =7.9A
Second 5 ms on-period when vL = -340 V
iL = -34 + (34+7.9) e-200t
with iL = 0 at 1 ms and ending with iL = -18.6 A
Second 5 ms zero-period when vL = 0 V
iL = -18.6 e-200t
ending with iL = -6.8A
Third 5 ms on-period when vL = 340 V
iL = 34 - (34+6.8) e-200t

Power Inverters

420

with iL = 0 at 0.9 ms and ending with iL = 19.0 A

Third 5 ms zero-period when vL = 0 V
iL = 19.0 e-200t
ending with iL = 7.0A
Fourth 5 ms on-period when vL = -340 V
iL = -34 + (34+7.0) e-200t
with iL = 0 at 0.93 ms and ending with iL = -18.9 A
Fourth 5 ms zero-period when vL = 0 V
iL = -18.9 e-200t
ending with iL = -7.0A
Steady-state load current conditions have been reached and the load current
waveform is as shown in figure 14.1c. Convergence of an iterative solution is more
rapid if the periods considered are much longer than the load time constant.
The mean load power for the quasi-square wave is given by
5ms
1
PL =
340V {34 - 41 e-200t } dt
10ms 0
= 1378 W
?

Example 14.2:

H-bridge inverter ac output factors

In each waveform case of example 14.1 calculate

i.
the average and peak current in the switches
ii.
the average and peak current in the diodes
iii.
the peak blocking voltage of each semiconductor type
iv.
the average source current
v.
the harmonic factor and distortion factor of the lowest order harmonic
vi.
the total harmonic distortion
Solution
Square-wave

i. The peak current in the switch is I = 25.9 A and the current zero cross-over
occurs at tx=2.83ms . The average switch current, from equation (14.11) is
10ms
1
IT =
(34 - 59.9 e 200 t ) dt
20ms 2.83ms
= 5.71 A
ii. The peak diode current is 25.9 A. The average diode current from equation
(14.12) is
2.83ms
1
ID =
(34 - 59.9 e 200 t ) dt
0
20ms
= 1.66 A

Power Electronics

421

iii. The maximum blocking voltage of each device is 340 V dc.

iv. The average supply current is

Is = 2 I TH I D

= 2 ( 5.71A - 1.66A ) = 8.10A

This results in the supply delivery power of 340Vdc 8.10A = 2754W
v. From equation (14.15), with the third as the lowest harmonic, the distortion
factors are

hf = 3 =
df = 3 =

V3
V1

= 1 , that is, 33 1 3 per cent

3

V3
= 1 , that is, 11.11 per cent
9
3V1

vi. From equation (14.15)

2

thd =
=

V
nn /V1

( ) + ( ) +( )
1
3

1
5

1
7

+ ......

= 46.2 per cent

Quasi-square-wave, a = p (5 ms) and from equation (14.25) tx= 0.93ms
i. The peak switch current is 18.9 A.
From equation (14.26) the average switch current, using alternating zero volt loops,
is
5ms
5ms
1
1
IT =
(34-41e-200t ) dt +
19e-200 t dt
0.93ms
0
20ms
40ms
= 2.18 + 1.50 = 3.68 A

ii. The peak diode current (and peak switch current) is 18.9 A. The average diode
current, from equation (14.27), when using alternating zero volt loops, is given by
0.93ms
1
1
( 34 + 41e200t ) dt + 40ms
20ms 0
= 0.16 + 1.50 = 1.66 A

ID =

5ms

19e-200 t dt

iii. The maximum blocking voltage of each device type is 340 V.

Power Inverters

iv. The average supply current is

I s = 2 I TH I D

422

= 2 ( 3.68A - 1.66A ) = 4.04A

This results in the supply delivery power of 340Vdc 4.04A = 1374W
v. The harmonics are given by equations (14.1) to (14.3)

hf = 3 =

V3
=
V1

df = 3 =

/ 1
3 2

1
3

, that is, 33 1 3 per cent

V3
= 3 = 1 , that is, 11.11 per cent
n
9
nV1

vi.

Vn 2
thd =
n 2 n

/V1
2

1 1 1 1
= + + + + ...
3 5 7 9
= 46.2 per cent
?
Example 14.3:

Single-phase half-bridge with an L-R load

A single-phase half-bridge inverter as shown in the figure 14.2, supplies a 10 ohm

resistance with inductance 50 mH from a 340 V dc source. If the bridge is
operating at 50 Hz, determine for the square-wave output
i.
steady-state current waveforms
ii.
the load rms voltage
iii.
the peak load current and its time domain solution, iL(t)
iv.
the average and peak current in the switches
v.
the average and peak current in the diodes
vi.
the peak blocking voltage of each semiconductor type
vii. the power delivered to the load
Solution
From examples 14.1 and 14.2, t = 5ms.
i. Figure 14.2 shows the output voltage and current waveforms, with various
circuit component current waveforms superimposed. Note that no zero voltage
loops can be created with the half-bridge. Only load voltages Vs , that is
170V, are possible.
ii. The output voltage swing is Vs , 170V, thus the rms output voltage is Vs ,
170V. This is , half that of the full-bridge inverter using the same magnitude source
voltage Vs , 340V.

Power Electronics

423

iii. The peak load current is half that given by equation (14.9), that is
t1

Vs 1 e
Vs
t
I =
=
tanh 1
t
R
R
2
1+ e
340V
10ms
=
tanh
= 12.95A
10O
25ms
The load current waveform is defined by equations (14.7) and (14.8), specifically
Vs Vs t
iL (t ) =

I e
R R

340V 340V
t

+ 12.95A e5ms
10
10

= 17 29.95 e 5ms

0 t 10ms

for

and

Vs Vs t
+
+ I e
R R

340V 340V
t
=
+
+ 12.95 e 5ms
10O
10O

iL ( t) =
II

= 17 + 29.95 e5ms
for
0 t 10ms
By halving the effective supply voltage, the current swing is also halved.
iv. The peak switch current is I$ = 1295
. A.
The average switch current is given by
t
10ms
1
IT =
(17 29.95e 5ms ) dt
20ms 2.83ms
= 2.86 A

Cl
+

Cl

Cl
Cu

Cupper

Cu

Vs

Vs

170V

Vs

Vs

tx

Clower

-170V

t1
12.95A
2.83ms

t2

I
(a)

-12.95A

(b)

Figure 14.2. GCT thyristor single-phase half-bridge inverter:

(a) circuit diagram and (b) square-wave output voltage.

Power Inverters

v. The peak diode current is I$ = 12.95A .

The average diode current is given by
t
2.83ms
1
ID =
17 29.95e 5ms

20ms 0

424

dt

= 0.83 A
vi. When a switch or diode of a parallel pair conduct, the complementary pair of
devices experience a voltage Vs , 340V. Thus although the load experiences half the
supply voltage, the semiconductors experience twice that voltage, the same as with
the full bridge inverter.
vii. The load power is found by averaging the instantaneous load power, that is
10 ms
1
PL =
170V ( 17 - 29.95 e-200t ) dt
0
10ms
= 638.5 W
?

14.1.2

Three-phase voltage-fed inverter bridge

The basic dc to three-phase voltage-fed inverter bridge is shown in figure 14.3. It

comprises six power switches together with six associated reactive feedback
diodes. Each of the three inverter legs operates at a relative time displacement
(phase) of ? p, 120.

Figure 14.3. Three-phase inverter circuit:

(a) GCT thyristor bridge inverter; (b) star-type load; and (c) delta -type load.

Power Electronics

425

14.1.2i - 180 (p) conduction

Figure 14.4 shows inverter bridge quasi-square output voltage waveforms for a
180 switch conduction pattern. Each switch conducts for 180, such that no two
semiconductor switches across the voltage rail conduct simultaneously. Six
patterns exist for one output cycle and the rate of sequencing these patterns
specifies the bridge output frequency. The conducting switches during the six
distinct intervals are shown and can be summarised as in Table 14.1.
Table 14.1. Quasi-square-wave six conduction states - 180 conduction.

Three conducting switches

Interval
1
2
3
4
5
6

T1

T2

T3

T2

T3
T3

leg state

voltage vector

101

v5

001

v1

T4

T5

011

v3

T4

T5

T6

010

v2

T5

T6

T1

110

v6

T6

T1

100

v4

T4

T2

The three output voltage waveforms can be derived by analysing a resistive star
load and considering each of the six connection patterns, as shown in figure 14.5.
Effectively the resistors representing the three-phase load are sequentially cycled
anticlockwise one at a time , being alternately connected to each supply rail.
Alternatively, the generation of the three-phase voltages can be analysed
analytically by using the rotating voltage space vector technique. With this
approach, the output voltage state from each of the three inverter legs (or poles) is
encoded as summarised in the table 14.1, where a 1 signifies the upper switch in
the leg is on, while a 0 means the lower switch is on in that leg. The resultant
binary number (one bit for each of the three inverter legs), represents the output
voltage vector number (when converted to decimal). The six voltage vectors are
shown in figure 14.6 forming sextant boundaries, where the quasi-square output
waveform in figure 14.4b is generated by stepping instantaneously from one vector
position to another in an anticlockwise direction. Note that the rotational stepping
sequence is arranged such that when rotating in either direction, only one leg
changes state, that is, one device turns off and then the complementary switch of
that leg turns on, at each step. This minimises the inverter switching losses. The
dwell time of the created rotating vector at each of the six vector positions, is ? p
(T) of the cycle period (T). Note that the line-to-line zero voltage states 000 and
111 are not used. These represent the condition when either all the upper switches
(T1 , T3 , T5 ) are on or all the lower switches (T2 , T4 , T5 ) are switched on. Phase
reversal can be obtained by interchanging two phase outputs , or as is the preferred
method, the direction of the rotating vector sequence is reversed. Reversing is
therefore effectively achieved by back-tracking along each output waveform.

Power Inverters

T1

T5

T4

426

T3

T2

T6

110

100

101

001

011

010

v6

v4

v5

v1

v3

v2

VRB

VBY

VYR

VRN
(iR)

VBN
(iB)
VYN
(iY )

(b)
Figure 14.4. A three-phase bridge inverter employing 180 switch conduction
with a resistive load: (a) the bridge circuit showing T1, T 5, and T 6 conducting (leg
state v 6 : 110) and (b) circuit voltage and current waveforms with each of six
sequential output voltage vectors identified.

Power Electronics

427

T1 / T4

T5 / T2

T3 / T6

R
T1
T5

T1
VRN = Vs /3

VRN = 2Vs /3

VBN = -2V s /3

VBN = -Vs /3

VYN = Vs /3

VYN = -Vs /3

T2

T6

T6
B

B
T1

T3

T3
VRN = Vs /3

VRN = -Vs /3

VBN = Vs /3

VBN = 2Vs /3

VYN = -2Vs /3

VYN = -Vs /3

T4

T2

T2
R

T5

T5

T3

VRN = -2V s/3

VRN = -Vs /3

VBN = Vs/3

VBN = -Vs /3

VYN = Vs/3

VYN = 2Vs /3

T6
T4

T4
R

2p

Figure 14.5. Determination of the line-to-neutral voltage waveforms for a

balanced resistive load and 180 conduction as illustrated in figure 14.4.

Power Inverters

428

With reference to figure 14.4b, the line-to-load neutral voltage is defined by

2
vRN = Vs [ sin t + 15 sin5t + 71 sin7t + 111 sin11t + . . .]
(V)
(14.34)

similarly for vYN and vBN, where ? t is substituted by ? t + ? p and ? t-? p

respectively.
The line-to-line voltage, from equation (14.31) with a = ? p, is defined by

2 3
V [ sin t - 15 sin5t - 17 sin7 t + 111 sin11 t + . . .] (V)
(14.35)
s
and similarly for vBY and vYR . Figure 14.4b shows that vRB is shifted p with respect
to vRN, hence to obtain the three line voltages while maintaining a vRN reference, ? t
should be substituted with ? t + p, ? t- p and ? t-p, respectively.
Since the interphase voltages consist of two square waves displaced by ? p, no
triplen harmonics (3, 6, 9, . . .) exist. The outputs comprise harmonics given by the
series n = 6r 1 where r = 0 and is an integer. The nth harmonic has a magnitude
of 1/n relative to the fundamental.
v RB =

Interval 4
T 4 T5 T 6 on
leg state 010
v 2 = Vs e p j

Interval 3
T 3 T4 T 5 on
leg state 011
v3 = Vs e p j

Interval # 5
T 1 T 5 T 6 on
leg s tate 1 10
p j
v6 = V s e

Interval # 2
T 2 T 3 T 4 on
leg state 001
0j
v 1 = Vs e

Interval 6
T 1 T2 T 6 on
leg state 1 00
p j
v4 = V s e

Interval 1
T 1 T2 T 3 on
leg state 101
- p j
v 5 = Vs e

001
v1

011
v3

010
v2

110
v6

100
v4

101
v5

Figure 14.6. Generation and arrangement of the six quasi-square inverter output
voltage states.

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429

By examination of the interphase output voltages in figure 14.4 it can be

established that the mean half-cycle voltage is ? Vs and the rms value is v? Vs ,
namely 0.816 Vs . From equation (14.35) the rms value of the fundamental is v6 Vs
/p, namely 0.78 Vs , that is 3/p times the total rms voltage value.
The three-phase inverter output voltage properties are summarised in Table 14.2.
Table 14.2. Quasi-squarewave voltage properties
Conduction
period

Fundamental voltage
peak
rms

Total rms

Characteristic
Distortion Factor

THD

thd

V1

V1

Vrms

180

(V)

(V)

(V)

Phase
Voltage
V L- N

2
V
s

2
V
s

2
V
3 s

= 0.637Vs

2
1
9

= 0.450 Vs

= 0.471Vs

= 0.955

= 0.311

Line
Voltage
V L- L

2 3
V
s
= 1.10 Vs

6
V
s

2
1
9

= 0.78 Vs

2
V
3 s
= 0.816Vs

= 0.955

= 0.311

120

(V)

(V)

(V)

Phase
Voltage
V L- N

3
V
s
= 0.551 Vs

2
1
9

= 0.955

= 0.311

Line
Voltage
V L- L

3
V
s

2
1
9

= 0.955

= 0.311

= 0.955Vs

6
V
2 s
= 0.390 Vs
3
V
2 s
= 0.673 Vs

1
Vs
6
= 0.408Vs
1

Vs

2
= 0.707Vs

14.1.2ii - 120 (? p) conduction

The basic three-phase inverter bridge in figure 14.3 can be controlled with each
switch conducting for 120. As a result, at any instant only two switches (one
upper and one non-complementary lower) conduct and the resultant quasi-square
output voltage waveforms are shown in figure 14.7. A 60 (? p), dead time exists
between two series switches conducting, thereby providing a safety margin against
simultaneous conduction of the two series devices (for example T1 and T4 ) across
the dc supply rail. This safety margin is obtained at the expense of a lower semiconductor device utilisation and rms output voltage than with 180 device
conduction. The device conduction pattern is summarised as in Table 14.3.
Figure 14.4b for 180 conduction and 14.7b for 120 conduction show that the line
to neutral voltage of one conduction pattern is proportional to the line-to-line
voltage of the other. That is from equation (14.31) with a = ? p

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430

Figure 14.7. A three-phase bridge inverter employing 120 switch conduction

with a resistive star load: (a) the bridge circuit showing T 1 and T 2 conducting and
(b circuit voltage and current waveforms.

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431

vRN

) = vRY ( )
=

(14.36)

3
V [ sin t - 15 sin5t - 17 sin7t + 111 sin11t + . . .]
s

(V)

and
v RY ( 2 3 ) = 3 2 vRN ( )
(14.37)
3
Vs [sin t + 15 sin5t + 71 sin7t + 111 sin11t + . . . ]
(V)

Also vRY = v3 vRN and the phase relationship between these line and phase voltages,
of p, has not been retained. That is, with respect to figure 14.7b, substitute ? t with
? t + p in equation (14.36) and ?t + ? p in equation (14.37).
The output voltage properties for both 120 and 180 switch conduction are
summarised in the Table 14.2.

Table 14.3. Quasi-squarewave conduction states - 120 conduction.

Two conducting devices

Interval
1
2
3
4
5
6

14.1.3

T1

T2
T2

T3
T3

T4
T4

T5
T5

T6
T6

T1

Inverter output voltage and frequency control techniques

It is a common requirement that the output voltage and/or frequency of an inverter

be varied in order to control the load power or, in the case of an induction motor, to
control the shaft speed and torque. The six modulation control techniques to be
considered are:

Variable voltage dc link

Single -pulse width modulation
Multi-pulse width modulation
Multi-pulse, selected notching modulation
Sinusoidal pulse width modulation
Triplen injection
Triplens injected into the modulation waveform
Voltage space vector modulation

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432

14.1.3i - Variable voltage dc link

The rms voltage of a square-wave can be changed and controlled by varying the dc
link source voltage. A variable dc link voltage can be achieved with a dc chopper
as considered in chapter 13 or an ac phase-controlled thyristor bridge as considered
in sections 11.2 and 11.5. A dc link L-C smoothing filter may be necessary.
14.1.3ii - Single-pulse width modulation
Simple pulse-width control can be employed as considered in section 14.1.1b,
where a single-phase bridge is used to produce a quasi-square-wave output voltage
as shown in figure 14.1c.
An alternative method of producing a quasi-square wave of controllable pulse
width is to transformer-add the square-wave outputs from two push-pull bridge
inverters as shown in figure 14.8a. By phase-shifting the output by a, a quasisquare sum results as shown in figure 14.8b.

Figure 14.8. Voltage control by combining phase-shifted push-pull inverters:

(a) two inverters with two transformers for summing and (b) circuit voltage waveforms for a phase displacement of a .

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433

The output voltage can be described by

Vo =

an

sin nt

(V)

(14.38)

nodd

where

van = 2

Vs cos n d = 4 Vs cos( n )
n

(V)

(14.39)

The rms output voltage is

Vr = Vs 1-

(V)

(14.40)

and the rms value of the fundamental is

2 2
Vs cos
(V)
(14.41)

As a increases, the magnitude of the harmonics, particularly the third, becomes

significant compared with the fundamental magnitude. This type of control may be
used in high power applications.
V1 =

14.1.3iii - Multi-pulse width modulation

An extension of the single-pulse modulation technique is multiple -notching as
shown in figure 14.9. The bridge switches are controlled so as to vary the on to off
time of each notch, d, thereby varying the output rms voltage which is given by
Vrms = Vs . Alternatively, the number of notches can be varied.
+Vs

d1
-Vs

+Vs

d2

-Vs
Figure 14.9. Inverter control giving variable duty cycle of five notches per half
cycle: (a) low duty cycle, d1, hence low fundamental magnitude and (b) higher
duty cycle, d 2, for a high fundamental voltage output.

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434

The harmonic content at lower output voltages is significantly lower than that
obtained with single-pulse modulation. The increased switching frequency does
increase the magnitude of higher harmonics and the switching losses.
14.1.3iv - Multi-pulse, selected notching modulation
Selected elimination of lower-order harmonics can be achieved by producing an
output waveform as shown in figure 14.10. The exact switching points are
calculated off-line so as to eliminate the required harmonics. For n switchings per
half cycle, n selected harmonics can be eliminated.
In figure 14.10 two notches per half cycle are introduced; hence any two selected
harmonics can be eliminated. The more notches, the lower is the output
fundamental. For example, with two notches, the third and fifth harmonics are
eliminated. From
4

bn =

f ( ) sin n d

for

n = 1,2,3,....

(14.42)

b3 = 4 Vs (1 2cos3 + 2cos3 ) = 0
3
and
b5 = 4 Vs (1 2cos5 + 2cos5 ) = 0
5

Figure 14.10. Output voltage harmonic reduction for a single-phase bridge using
selected notching.

Solving yields a = 23.6 and = 33.3. The fundamental rms component of the
output voltage waveform is 0.84 of a square wave, which is (2v2/p)Vs . Ten
switching intervals exist compared with two per cycle for a square wave, hence
switching losses and control circuit complexity are increased.
In the case of a three-phase inverter bridge, the third harmonic does not exist,
hence the fifth and seventh (b 5 and b7 ) can be eliminated with a = 16.3 and =
22.1. The 5th, 7th, 11th , and 13th can be eliminated with the angles 10.55, 16.09,
30.91, and 32.87 respectively. Because the waveforms have quarter wave
symmetry, only angles for 90 need be stored.

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Power Electronics

The output rms voltage magnitude can be varied by controlling the dc link voltage
or by transformer-adding two phase-displaced bridge outputs as demonstrated in
figure 14.8. The rms magnitude can be changed by introducing an extra constraint
to be satisfied, along with the harmonic eliminating constraints.
The multi pulse selected notching modulation technique can be extended to the
optimal pulse-width modulation method, where harmonics may not be eliminated,
but minimised according to a specific criterion. In this method, the quarter wave
output is considered to have a number of switching angles. These angles are
selected so as, for example, to eliminate certain harmonics, minimise the rms of the
ripple current, or any other desired performance index. The resultant non-linear
equations are solved using numerical methods off-line. The computed angles are
then stored in a ROM look-up table for use. A set of angles must be computed and
stored for each desired level of the voltage fundamental and output frequency.
The optimal pwm approach is particularly useful for high-power, high-voltage GCT
thyristor inverters, which tend to be limited in switching frequency by device
switching losses.
14.1.3v - Sinusoidal pulse-width modulation (pwm)
1 - Natural sampling
(a) Synchronous carrier
The output voltage waveform and method of generation for synchronous carrier,
natural sampling sinusoidal pwm, suitable for the single-phase bridge of figure
14.1, are illustrated in figure 14.11. The switching points are determined by the
intersection of the triangular carrier wave fc and the reference modulation sine
wave, fo . The output frequency is at the sine-wave frequency fo and the output
voltage is proportional to the magnitude of the sine wave. The amplitude M (0 = M
= 1) is called the modulation index. For example, figure 14.11a shows maximum
voltage output (M = 1), while in figure 14.11b where the sine-wave magnitude is
halved (M = 0.5), the output voltage is halved.
If the frequency of the modulation sinewave, fo , is an integer multiple of the
triangular wave carrier-frequency, fc that is, fc = nfo where n is integer, then the
modulation is synchronous, as shown in figure 14.11. If n is odd then the positive
and negative output half cycles are symmetrical and the output voltage contains no
even harmonics. In a three-phase system if n is a multiple of 3 (and odd), the
carrier is a triplen of the modulating frequency and the spectrum does not contain
the carrier or its harmonics.
fc = (6q + 3) fo = nf o
(14.43)
for q = 1, 2, 3.
Sinusoidal pwm requires a carrier of much higher frequency than the modulation
frequency. The generated rectilinear output voltage pulses are modulated such that
their duration is proportional to the instantaneous value of the sinusoidal waveform
at the centre of the pulse; that is, the pulse area is proportional to the corresponding
value of the modulating sine wave.

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436

Figure 14.11. Derivation of trigger signals for naturally sampled pulse-width

modulation waveforms: (a) for a high fundamental output voltage (M = 1) and
(b) for a lower output voltage (M = 0.5), with conducting devices shown.

If the carrier frequency is very high, an averaging effect occurs, resulting in a

sinusoidal fundamental output with high-frequency harmonics, but minimal lowfrequency harmonics.
Rather than using a triangular carrier, which has an alternating offset as shown in
figure 14.11, a triangular carrier without an offset can be used. Now the output
only approximates the ideal. Figure 14.12 shows this pwm generation technique

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Power Electronics

and voltage output waveform applied to the three-phase inverter in figure 14.3. The
offset carrier is not applicable to three-phase pwm generation since complementary
switch action is required. That is, one switch in the inverter leg must always be on.
It will be noticed that, unlike the output in figure 14.11, no zero voltage output
periods exist. This has the effect that, in the case of GCT thyristor bridges, a large
number of commutation cycles is required. When zero output periods exist, as in
figure 14.11, one GCT thyristor is commutated and the complementary device in
that leg is not turned on. The previously commutated device can be turned back on
without the need to commutate the complementary device, as would be required
with the pwm technique illustrated in figure 14.12. Commutation losses are
reduced, control circuitry simplified and the likelihood of simultaneous conduction
of two series devices is reduced.
The alternating zero voltage loop concept can be used, where in figure 14.11b,
rather than T1 being on continuously during the first half of the output cycle, T2 is
turned off leaving T1 on, then when either T1 or T2 must be turned off, T1 is turned
off leaving T2 on.
(b) Asynchronous carrier
When the carrier is not an interger multiple of the modulation waveform,
asynchronous modulation results. Because the output frequency, fo , is usually
variable over a wide range, it is difficult to ensure fc = nfo . To achieve
synchronism, the carrier frequency must vary with frequency fo . Simpler generating
systems result if a fixed carrier frequency is used, resulting in asynchronism
between fo and fc at most output frequencies. Left over, incomplete carrier cycles
create slowly varying output voltages, called subharmonics, which may be
troublesome with low carrier frequencies, as found in high-power drives. Natural
sampling, asynchronous sinusoidal pwm is usually restricted to analogue or ASIC
implementation. The harmonic consequences of asynchronous-carrier naturalsampling are similar to asynchronous-carrier regular-sampling in 2 to follow.
2 - Regular sampling
Asynchronous carrier
When a fixed carrier frequency is used, usually no attempt is made to synchronise
the modulation frequency. The output waveforms do not have quarter-wave
symmetry which produces subharmonics. These subharmonics are insignificant if
fc >> fo , usually, fc > 20 fo .
The implementation of sinusoidal pwm with microprocessors or digital signal
processors is common because of flexibility and the elimination of analogue
circuitry associated problems. The digital pwm generation process involves
scaling, by multiplication, of the per unit sine-wave samples stored in ROM. The
multiplication process is time-consuming, hence natural sampling is not possible.
In order to minimise the multiplication rate, the sinusoidal sine-wave reference is
replaced by a quantised stepped representation of the sine-wave. Figure 14.13
shows two methods used. Sampling is synchronised to the carrier frequency and
the multiplication process is performed at three times the sampling rate for threephase pwm generation (once for each phase).

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438

Figure 14.12. Naturally sampled pulse-width modulation waveforms suitable for a

three-phase bridge inverter: (a) reference signals; (b) conducting devices and
fundamenta l sine waves; and (c) one output line-to-line voltage waveform.

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Power Electronics

Figure 14.13. Regular sampling, asynchronous, sinusoidal pulse-widthmodulation: (a) symmetrical modulation and (b) asymmetrical modulation.

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440

Symmetrical modulation
Figure 14.13a illustrates the process of symmetrical modulation, where sampling is
at the carrier frequency. The quantised sine-wave is stepped and held at each
sample point. The triangular carrier is then compared with the step sine-wave
sample. The modulation process is termed symmetrical modulation because the
intersection of adjacent sides of the triangular carrier with the stepped sine-wave,
about the non-sampled carrier peak, are equidistant about the carrier peak. The
pulse width, independent of the modulation index M, is symmetrical about the
triangular carrier peak not associated with sampling, as illustrated by the upper
pulse in figure 14.14. The pulse width is given by
1
t ps =
(14.44)
(1- M sin2 fot1 )
2 fc
where t1 is the time of sampling.
tp 2s
t p1s

M2

M1
t1

Triangular carrier

fc

Reference fo2

Reference fo1

t2

M2

Line of
symmetry

M1

tp1a
tp2a

Figure 14.14. Regular sampling, asynchronous, sinusoidal pulse-widthmodulation, showing double edge:
(upper) asymmetrical modulation and (lower) symmetrical modulation.

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441

Asymmetrical modulation
Asymmetrical modulation is produced when the carrier is compared with a stepped
sine wave produced by sampling and holding at twice the carrier frequency, as
shown in figure 14.13b. Each side of the triangular carrier about a sampling point
intersects the stepped waveform at different step levels. The resultant pulse width
is asymmetrical about the sampling point, as illustrated by the lower pulse in figure
14.14 for two modulation waveform magnitudes. The pulse width is given by
1
t pa =
1- M ( sin2 fo t1 + sin2 fo t2 )
(14.45)
2 fc

where t1 and t2 are the times at sampling such that t2 = t1 + 1/2fc.

Figure 14.14 shows that a change in the modulation index M varies the pulse width
on each edge, termed double edge modulation. A triangular carrier produces
double edge modulation, while a sawtooth carrier produces single edge
modulation, independent of the sampling technique.
3 - Frequency spectra of pwm waveforms
The most common form of sinusoidal modulation for three-phase inverters is
regular sampling, asynchronous, fixed frequency carrier, pwm. If fc > 20fo , low
frequency subharmonics can be ignored. The output spectra consists of the
modulation frequency fo with magnitude M. Also present are the spectra components associated with the triangular carrier, fc. For any sampling, these are fc and
the odd harmonics of fc. (The triangular carrier fc contains only odd harmonics).
These decrease in magnitude with increasing frequency. About the frequency nfc
are components of fo spaced at 2fo , which generally decrease in magnitude when
further away from nfc. That is, at fc the harmonics present are fc, fc 2fo , fc 4fo ,
while about 2fc , the harmonics present are 2fc f0 , 2fc 3fo ,..., but 2fc is not present.
The typical output spectrum is shown in figure 14.15. The relative magnitudes of
the sidebands vary with modulation depth and the carrier related frequencies
present, fh , are given by

1n +1

1n
fh = +
(14.46)
n fc 2k +
fo
2
2

where k = 1, 2, 3,.... (sidebands) and n = 1, 2, 3,.... (carrier)

M-

2fo

fo

1 fc

with single-phase unipolar pwm

f h = 0 for n odd
(suppressed carrier and n -odd side bands)

2fo

2 fc

3 fc

4 fc

Figure 14.15. Location of carrier harmonics and modulation frequency sidebands,

showing all sideband separated by 2fm.

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442

Although the various pwm techniques produce other less predominate spectra
components the main difference is seen in the magnitude of the carrier harmonics
and sidebands. The magnitudes increase as the pwm type changes from naturally
sampling to regular sampling, then from asymmetrical to symmetrical modulation,
and finally from double edge to single edge. With a three-phase inverter, the
carrier and its harmonics do not appear in the line-to-line voltages since the carrier
is co-phase to the three modulation waveforms.
14.1.3vi - Phase dead-banding
Dead banding is when one phase (leg) is in a fixed on state, and the remaining
phases are appropriately modulated so that the phase currents remain sinusoidal.
The dead banding occurs for 60 periods of each cycle with the phase with the
largest magnitude voltage being permanently turned on. Sequentially each switch
is clamped to the appropriate link rail. The leg output is in a high state if it is
associated with the largest positive phase voltage magnitude, while the phase
output is zero if it is associated with the largest negative phase magnitude. Thus
the phase outputs are cycled, being alternately clamped high and low for 60 every
180 as shown in figure 14.16. A consequence of dead banding is reduced
switching losses since each leg is not switched at the carrier frequency for 120
(two 60 periods 180 apart). A consequence of dead banding is increased ripple
current. Dead banding is achieved with discontinuous modulating reference
signals. Dead banding for a continuous 120 per phase leg is also possible but the
switching loss savings are not uniformly distributed amongst the six inverter
switches.

m = 0

m =

m =

m =

m = 1

? t

1
p
3

2 p
3

4
p
3

5 p
3

2p

Figure 14.16. Modulation reference waveform for phase dead banding.

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443

14.1.3vii - Triplen Injection modulation

The magnitude of the fundamental can be increased from 0.827pu to 0.955pu
without introducing output voltage distortion, by the injection of triplen
components, which are co-phasal in a three-phase system, and therefore do not
appear in the line currents. Two basic approaches can be used to affect this
undistorted output voltage magnitude increase.
Triplen injection into the modulation waveform or
Voltage space vector modulation

Triplens injected into the modulation waveform

An inverter reconstitutes three-phase voltages with a maximum magnitude of 0.827

(3v 3/2p ) of the fixed three-phase input ac supply. A motor designed for the fixed
mains supply is therefore under-fluxed at rated frequency and not fully utilised on
an inverter. As will be shown, by adding third harmonic voltage injection, the flux
level can be increased to 0.955 (3/p) of that produced on the three-phase ac mains
supply.
If overmodulation (M > 1) is not allowed, then the modulation wave M sin ? t is
restricted in magnitude to M = 1, as shown in figure 14.17a.
If VRN = M sin? t = 1pu
and
VYN = M sin(? t + ? p) = 1 pu
then
VRY = v3 M sin(? t - p)
where 0 = M = 1
In a three-phase pwm generator, the fact that harmonics at 3fo (and multiplies of
3fo ) vectorally cancel can be utilised effectively to increase M beyond 1, yet still
ensure modulation occurs for every carrier frequency cycle.
Let
VRN = M' sin?t+ sin3?t) = 1 pu
and
VYN = M' ( sin(? t +? p) + sin 3(? t + ? p)) = 1 pu
then
VRY = v3 M' sin(? t - p )
VRN has a maximum instantaneous value of 1 pu at ?t = ?p, as shown in figure
14.17b. Therefore

VRN ( t = 13 ) =

3
M ' =1
2

that is

' = 2
M
M = 1.155
M
(14.47)
3
Thus the fundamental of the phase voltage is M' sin ? t = 1.155 M sin ? t. That is, if
the modulation reference sin ? t + sin 3 ? t is used, the fundamental output voltage
is 15.5 per cent larger than when sin ? t is used as a reference. The increased
fundamental is shown in figure 14.17b.

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444

Figure 14.17. Modulation reference waveforms:

(a) sinusoidal reference, sin ? t; (b) third harmonic injection reference, sin ? t +
sin 3? t; and (c) triplen injection reference, sin ? t + (1/v3p){9/8sin3? t 80/81sin9? t + . . .} where the near triangular waveform b is half the magnitude
of the shaded area.

The spatial voltage vector technique injects the triplens according to

r

1
( 1)
VRN = M ' sin t +
(14.48)
sin ( 2r + 1) 3t
3 r =0 ( 2r + 1) 13 ( 2r + 1) + 13

The Fourier triplen series represents half the magnitude of the shaded area in figure
14.17c (the waveform marked b), which is formed by the three-phase voltage
waveforms. The spatial voltage vector waveform is defined by
3
sin(t)
0 t 16
2
(14.49)
3
1
1
sin(t + 6 )
6 t
2

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445

The use of this reference increases the duration of the zero volt loops, thereby
decreasing inverter output ripple. The maximum modulation index is 1.155. Third
harmonic injection, yielding M = 1.155, is a satisfactory approximation to spatial
voltage vector.

Voltage space vector pwm

When generating three-phase quasi-square output voltages, the inverter switches

step progressively to each of the six switch output possibilities (states ). In figure
14.6, when producing the quasi-square output, each of these six states is
represented by an output voltage space vector. Each vector has a ? p displacement
from its two adjacent states, and each has a length Vs which is the pole output
voltage relative to the inverter 0V rail. Effectively, the quasi-square three-phase
output is generated by a rotating vector of length Vs , jumping successively from
one output state to the next in the sequence, and in so doing creating six sectors.
The speed of rotation, in particular the time for one rotation, determines the
inverter output frequency. The sequence of voltage vectors {v1 , v3 , v2 , v6 , v4 , v5 } is
arranged such that stepping fro m one state to the next involves only one of the
three poles changing state. Thus the number of inverter devices needing to change
states (switch) at each transition, is minimised.
[If the inverter switches are relabelled, upper switches T1 , T2 , T3 - right to left; and
lower switches T4 , T5 , T6 - right to left: then the rotating voltage sequence becomes
{v1 , v2 , v3 , v4 , v5 , v6 }]
Rather than stepping ? p radians per step, from one voltage space vector position to
the next, thereby producing a six-step quasi-square fixed magnitude voltage output,
the rotating vector is rotated in smaller steps based on the position being updated at
a constant rate (carrier frequency). Furthermore, the vector length can be varied, to
a magnitude less than Vs .
To incorporate a variable rotating vector length (modulation depth), it is necessary
to vary the average voltage in each carrier period. Hence pulse width modulation is
used in the period between each finite step of the rotating vector. Pulse width
modulation requires the introduction of zero voltage output states, namely all the
top switches on (state 111, v7 ) or all the lower switches on (state 000, v0 ). These
two extra states are shown in figure 14.18, at the centre of the hexagon. Now the
pole-to-pole output voltage can be zero, which allows duty cycle variation to
achieve variable average output voltage for each phase, within each carrier period,
proportional to the magnitude of the position vector.
To facilitate vector positions (angles) that do not lie on one of the six quasi-square
output vectors, an intermediate vector Vo/pe j? is resolved into the vector sum of the
two quasi-square vectors adjacent to the rotating vector. This process is shown in
figure 14.19 for a voltage vector Vo/p that lies in sector I, between output states v1
(001) and v3 (011). The voltage vector has been resolved into the two components
Va and Vb as shown.
The time represented by quasi-square vectors v1 and v3 is the carrier period Tc, in
each case. Therefore the portion of Tc associated with va and vb is scaled
proportionally to v1 and v3 , giving ta and tb .

Power Inverters

446

Interval # 4
T4 T5 T6 on
leg state 010
v2 = Vs e p j

Interval # 3
T3 T4 T5 on
leg state 011
v3 = Vs e p j
SECTOR

II
SECTOR

SECTOR

III
Interval # 5
T1 T5 T6 on
leg state 110
v6 = Vs e p j

I
000
111

SECTOR

SECTOR

IV

VI

Interval # 2
T2 T3 T4 on
leg state 001
v1 = Vs e 0 j

SECTOR

V
Interval # 6
T1 T2 T6 on
leg state 100
v4 = Vs e p j

Interval # 1
T1 T2 T3 on
leg state 101
v5 = Vs e - p j

001
v1

011
v3

010
v2

110
v6

100
v4

101
v5

111
v7

000
v0

Figure 14.18. Instantaneous output voltage states for the three legs of an
inverter.

447

Power Electronics

Va
ta
=
=
Tc
v1

2 V sin 1
(3
)
o/ p
3
Vs

Vb
tb
=
=
Tc
v3

2
Vo / p sin
3
Vs

(14.50)

where v1 = v3
The two sine terms in equation (14.50) generate two sine waves displaced by 120,
identical to that generated with standard carrier based sinusoidal pwm.
The sum of ta and tb cannot be greater than the carrier period Tc, thus
t a + t b Tc
(14.51)
ta + tb + to = Tc
where the slack variable to has been included to form an equality. The equality
dictates that vector v1 is used for a period ta , v3 is used for a period tb , and during
period to , the null vector, v0 or v7 , at the centre of the hexagon is used, which do not
affect the average voltage during the carrier interval Tc.
A further constraint is imposed in the time domain. The rotating voltage vector is a
fixed length for all rotating angles, for a given inverter output voltage. Its length is
restricted in both time and space. Obviously the resolved component lengths
cannot exceed the pole vector length, Vs . Additionally, the two vector magnitudes
are each a portion of the carrier period, where ta and tb could be both equal to Tc,
that is , they both have a maximum length Vs . The anomaly is that voltages va and
vb are added vectorially but their durations (times ta and tb ) are added linearly. The
longest time ta + tb possible is when to is zero, as shown in figures 14.19a and
14.18a, by the hexagon boundary. The shortest vector to the boundary is where
both resolving vectors have a length Vs , as shown in figure 14.19b. For such a
condition, ta = tb =Tc, that is ta + tb = Tc. Thus for a constant inverter output
voltage, when the rotating voltage vector has a constant length, Vo / p , the locus of
allowable rotating reference voltage vectors must be within the circle scribed by
the maximum length vector shown in figure 14.19b. As shown, this vector has a
length v1 cos30, specifically 0.866Vs . Thus the full quasi-square vectors v1 , v2 ,
etc., which have a magnitude of 1Vs , cannot be used for generating a sinusoidal
output voltage. The excess length of each quasi-square voltage (which represents
time) is accounted for by using zero state voltage vectors for a period
corresponding to that extra length (1- cos 30 at maximum output voltage).
Having calculated the necessary periods for the inverter poles (ta , tb , and to ), the
carrier period switching pattern can be assigned in two ways.
Minimised current ripple
Minimised switching losses , using dead banding
Each approach is shown in figure 14.20, using single edged modulation. The
waveforms are based on the equivalent of symmetrical modulation where the
pulses are symmetrical about the carrier trough. By minimising the current ripple,
seven switching states are used per carrier cycle, while for loss minimisation (dead
banding) only five switching states occur, but at the expense of increased ripple

Power Inverters

448

current in the output current. When dead banding, the zero voltage state v0 is used
in even numbered sextants and v7 is used in odd numbered sextants.
Sideband and harmonic component magnitudes can be decreased if double-edged
modulation placement of the states is used, which requires recalculation of ta , tb ,
and to at the carrier crest, as well as at the trough.
V3 =Vs e

j ?p

V3 =Vs e

011

j ?p

Tc

011

SECTOR I

SECTOR I

Tc

?t

Vo /p

tb
Vb = 2 VO / P sin
3
000
111

Vs cos30

VoV/pO/P
e

v 3 = V s

ta

Va = 2 VO /P sin ( 13 )
3

v1 =Vs e

Tc

30

000
111

v1 = V s

j0

v1 =V s e j 0

001

001

(a)

(b)

V3 =V s e

j? p

Tc

tb + t a < T c
reduced t o

011

60-a
V o /p

tb + ta > Tc
no to

> V$o /p

T
Tcc

Vo /p

000
111

Tc
v 1 =V s e

tb + ta < Tc
reduced to

j0

001

(c)

Figure 14.19. First sector of inverter operational area involving pole outputs 001
and 011: (a) general rotating voltage vector; (b) maximum allowable voltage
vector length for undistorted output voltages; and (c) over modulation.

Over-modulation is when the magnitude of the demanded rotating vector is greater

than Vo / p such that the zero voltage time reduces to zero, to = 0, during a portion of
the time of one rotation of the output vector. Initially this occurs at 30
( 16 ( 2 Nsector 1) ) when the output vector length reaches Vo / p , as shown in figure
14.19b. As the demand voltage magnitude increases further, the region around the
30 vector position where to ceases to occur, increases as shown in figure 14.19c.
When the output rotational vector magnitude increases to Vs , the maximum
possible, angle a reduces to zero, and to ceases to occur at any rotational angle.

Power Electronics

449

The values of ta , tb , and to (if greater than zero), are calculated as usual, but pulse
times are assigned pro rata to fit within the carrier period Tc.

v0

v1

v3

v7

v7

v3

v1

v0

000

001

011

111

111

011

001

000

to t a

tb

to to

tb

ta

to

FR

FY

FB

Tc
(a)

v1

v3

v7

v7

v3

v1

001

011

111

111

011

001

ta

tb

to t o t b

ta

FR

FY

FB

Tc
(b)
Figure 14.20. Assignment of pole periods ta and tb based on: (a) minimum current
ripple and (b) minimum switching transitions per carrier cycle, Tc .

Power Inverters

14.2

450

dc-to-ac controlled current-sourced inverters

In current-fed inverters (or alternatively current sourced inverter, CSI) the dc

supply is of high reactance, being inductive so as to maintain the required inverter
output bidirectional current independent of the inverter load.
14.2.1

Single-phase current fed inverter

A single-phase, controlled current-sourced bridge is shown in figure 14.21a and its

near square-wave output current is shown in figure 14.21b. No freewheel diodes
are required and the thyristors required forced commutation and have to withstand
reverse voltages. An inverter path must be maintained at all times for the source
controlled current.

Figure 14.21. Single-phase controlled-current sourced bridge inverter:

(a) bridge circuit with a current source input and (b) load current waveform.

Consider thyristors T1 and T2 on and conducting the constant load current. The
capacitors are charged with plates X and Y positive as a result of the previous
commutation cycle.
Phase I
Thyristors T1 and T2 are commutated by triggering thyristors T3 and T4 . The
capacitors impress negative voltages across the respective thyristors to be
commutated off, as shown in figure 14.22a. The load current is displaced from
T1 and T2 via the path T3 -C1 -D1 , the load and D2 -C2 -T4 . The two capacitors
discharge in series with the load, each capacitor reverse biasing the thyristor to
be commutated, T1 and T2 as well as diodes D3 to D4 . The capacitors dis charge
linearly (due to the constant current source).
Phase II
When both capacitors are discharged, the load current transfers from D1 to D2
and from D3 to D4 , which connects the capacitors in parallel with the load via
diodes D1 to D2 . The plates X and Y now charge negative, ready for the next
commutation cycle, as shown in figure 14.22b. Thyristors T1 and T2 are now
forward biased and must have attained forward blocking ability before the start
of phase 2.

Power Electronics

451

The on-going thyristor automatically commutates the outgoing thyristor. This

repeated commutation sequencing is a processed termed auto-sequential thyristor
commutation. The load voltage is load dependent and usually has controlled
voltage spikes during commutation.
Since the GTO and CGT both can be commutated from the gate, the two
commutation capacitors C1 and C2 are not necessary. Commutation overlap is still
essential. Also, if the thyristors have reverse blocking capability, the four diodes
D1 to D4 are not necessary. IGBTs require series blocking diodes, which increases
on-state losses. In practice, the current source inverter is only used in very highpower applications (>1MVA), and the ratings of the self-commutating thyristor
devices can be greatly extended if the simple external capacitive commutation
circuits shown in figure 14.21 are used to reduce thyristor turn-off stresses.
-

- +

- +

(a)

(b)

Figure 14.22. Controlled-current sourced bridge inverter showing commutation of

T1 and T 2 by T3 and T 4: (a) capacitors C1 and C2 discharging and T1, T2, D3, and D4
reversed biased and (b) C1, C 2, and the load in parallel with C 1 and C 2 charging.

14.2.2

Three-phase current fed inverter

A three-phase controlled current-sourced inverter is shown in figure 14.23a. Only

two thyristors can be on at any instant, that is , the 120 thyristor conduction
principle shown in figure 14.7 is used. A quasi-square line current results, as
illustrated in figure 14.23b. There is a 60 phase displacement between
commutation of an upper device followed by commutation of a lower device. An
upper device (T1 , T3 , T5 ) is turned on to commutate another upper device, and a
lower device (T2 , T4 , T6 ) commutate another lower device. The three upper
capacitors are all involved with each upper device commutation, whilst the same
constraint applies to the lower capacitors. Thyristor commutation occurs in two
distinct phases.
Phase I
In figure 14.24a the capacitors C13 , C35 , C51 are charged with the shown
polarities as a result of the earlier commutation of T5 . T1 is commutated by
turning on T3 . During commutation, the capacitor between the two
commutating switches is in parallel with the two remaining capacitors which

Power Inverters

452

are effectively connected in series. Capacitor C13 provides displacement current

whilst in parallel, C35 and C151 in series also provide thyristor T1 displacement
current, thereby reverse biasing T1 .
Phase II
When the capacitors have discharged, T1 becomes forward biased, as shown in
figure 14.24b, and must have regained forward blocking capability before the
applied positive dv/dt. The capacitor voltages reverse as shown in figure 14.24b
and when fully charged, diode D1 ceases to conduct. Independent of this
commutation, lower thyristor T2 is commutated by turning on T4 , 60 later.

Figure 14.23. Three-phase controlled-current sourced bridge inverter:

(a) bridge circuit with a current source input and (b) load current waveform for
one phase showing 120 conduction.

As with the single-phase current sourced inverter, assisted capacitor commutation

can greatly improve the capabilities of self-commutating thyristors, such as the
GTO thyristor and GCT . The output capacitors stiffen the output ac voltage.
A typical application for a three-phase current-sourced inverter would be to feed
and control a three-phase induction motor. Varying load requirements are met by
changing the source current level over a number of cycles by varying the link
inductor input voltage.

Power Electronics

453

Io

C35

C13

D1

+
+

D1

C35

C13

+ C51

Io

D3

+
C51

Io
Io
Io

Io

Io

(a)

Io

(b)

Figure 14.24. Controlled-current sourced bridge three-phase inverter showing

commutation of T1 and T3: (a) capacitors C13 discharging in parallel with C 35 and
C51 discharging in series, with T1,and D3 reversed biased (b) C13, C 35, and C51
charging in series with the load , with T1, forward biased.

An important advantage of the controlled current source concept, as opposed to the

constant voltage link, is good fault tolerance and protection. An output short circuit
or simu ltaneous conduction in an inverter leg is controlled by the current source.
Its time constant is usually longer than that of the input converter, hence converter
shut-down can be initiated before the link current can rise to a catastrophic level.
PWM techniques are applicable to current fed inverters in order to reduce current
harmonics, thereby reducing load losses and pulsating motor shaft torques. Since
current fed inverters are most attractive in very high-power applications, inverter
switching is minimised by using optimal pwm. The central 60 portion about the
maximums of each phase cannot be modulated, since link current must flow and
during such periods both the other phases require the opposite current direction.
Attempts to over come such pwm restrictions include using a current sourced
inverter with additional parallel current displacement paths as shown in figure
14.25. The auxiliary thyristors, Tupper and Tlower, and capacitors, CR , CY, and CB ,
provide alternative current paths (extra control states) and temporary energy
storage. The auxiliary thyristor can be commutated by the extra capacitors.
Characteristics and features of current fed inverters
The inverter is simple and can utilise rectifier grade thyristors. The
switching devices must have reverse blocking capability and experience
high voltages (both forward and reverse) during commutation.
Commutation capability is load current dependent and a minimum load is
required. This limits the operating frequency and precludes use in UPS
systems. The limited operating frequency can result in torque pulsations.

Power Inverters

454

The inverter can recover from an output short circuit hence the system is
rugged and reliable fault tolerant.
The converter-inverter configuration has inherent four quadrant capability
without extra power components. Power inversion is achieved by
reversing the converter average voltage output with a delay angle of a >
p, as in the three-phase fully controlled converter shown in figure 11.18
(or 14.5.3). In the event of a power supply failure, mechanical braking is
necessary. Dynamic braking is possible with voltage fed systems.
Current fed inverter systems have sluggish performance and stability
problems on light loads and at high frequency. On the other hand, voltage
fed systems have minimal stability problems and can operate open loop.
Each machine must have its own controlled rectifier and inverter. The dc
link of the voltage fed scheme can be used by many inverters or many
machines can utilise one inverter. A dc link offers limited ride-through.
Current feed inverters tend to be larger in size and weight, because of the
link inductor and filtering requirements.

T1

T5

T3

T4

T2

T6

Tupper
CR
CY
CB
Tlower

(a)
IR

+Io
?t

-Io
(b)
Figure 14.25. Three-phase controlled-current sourced bridge inverter with
alternative commutation current paths: (a) bridge circuit with a current source
input and two extra thyristors and (b) load current waveform for one phase
showing 180 conduction involving pwm switching.

Power Electronics

455

14.3

Resonant inverters

The voltage source inverters considered in 14.1 involve inductive loads and the use
of switches that are hard switched. That is, the switches experience simultaneous
maximum voltage and current during turn-on and turn-off with an inductive load.
The current fed inverters considered in 14.2 required capacitive circuits to
commutate the bridge switches. When self-commutatable devices are used in
current fed inverters, hard switching occurs. In resonant inverters, the load enables
commutation of the bridge switches with near zero voltage or current switch
conditions, resulting in low switching losses . A characteristic of resonant circuits is
that at regular, definable instants
for a step load voltage, the series L-C-R load current sinusoidally reverses or
for a step load current, the parallel L-C-R load voltage sinusoidally reverses.
If the load can be resonated, as considered in chapter 6.2.3, then switching stresses
can be significantly reduced for a given power through put, provided switching is
synchronised to the V or I zero crossing.
Three types of resonant converters utilise zero voltage or zero current switching.
load-resonant converters
resonant-switch dc-to-dc converters
resonant dc link and forced commutated converters
The single-phase load-resonant converter, which is extensively used in induction
heating applications, is presented and analysed in this chapter. Such resonant load
converters use an L-C load which oscillates, thereby providing load zero current or
voltage intervals at which the converter switches can be commutated with minimal
electrical stress. Resonant switch dc-to-dc converters are presented in chapter
15.9.
Two basic resonant-load single-phase inverters are used, depending on the L-C
load arrangement:
current fed inverter with a parallel L-C resonant (tank) load circuit:
switch turn-off at zero load voltage instants and turn-on with zero voltage
switch overlap is essential (a continuous source current path is required)
voltage fed inverter with a series connected L-C resonant load:
switch turn-off at zero load current instants and turn-on with zero current
switch under lap is essential (to avoid dc voltage source short circuiting)
Each load circuit type can be fed from a single ended circuit or H-bridge circuit
depending on the load Q factor. This classification is divided according to
symmetrical full bridge for low Q load circuits (class D)
asymmetrical singled ended circuit for a high Q load circuit (class E)
High Q circuits can also use a full bridge inverter configuration, if desired, for
higher through-put power.
In induction heating applications, the resistive part of the resonant load, called the
work-piece, is the active load to be heated - melted, where the heating load is
usually transformer coupled. Energy transfer control complication is usually
associated with the fact that the resistance of the load work-piece changes as it
heats up and melts, since resistivity is temperature dependant. However, control is
essentially independent of the voltage and current levels and is related to the
resonant frequency which is L and C dependant. Inverter bridge operation is near

Power Inverters

456

the load resonant frequency so that the output waveform is essentially sinusoidal.
By ensuring operation is below the resonant frequency, such that the load is
capacitive, the resultant leading current can be used to self commutate thyristor
converters which may be used in high power series resonant circuits. This same
capacitive load commutation effect is obtained for parallel resonant circuits with
thyristor current fed inverters operating just above resonance. The output power is
controlled by controlling the converter output frequency.
14.3.1

L-C resonant circuits

L-C-R resonant circuits, whether parallel or series connected are characterised by

the load impedance being capacitive at low frequency and inductive at high
frequency for the series circuit, and visa versa for the parallel case. The transition
frequency between being capacitive and inductive is the resonant frequency, ? o , at
which frequency the L-C-R load circuit appears purely resistive and maximum
power is transferred to the load, R. L-C -R circuits are classified according to
circuit quality factor Q, resonant frequency, ? o , and bandwidth, BW, for both
parallel and series circuits. The characteristics for the parallel and series resonant
circuits are related since every practical series L-C -R circuit has a parallel
equivalent, and visa versa.
As shown in figure 14.26 each resonant half cycle is characterised by
the series resonant circuit current is zero at maximum capacitor stored energy
the parallel resonant circuit voltage is zero at maximum inductor stored energy
The capacitor in a series resonant circuit must have an external path through which
to release its stored energy. The parallel resonant circuit can release its stored
inductive energy within its parallel circuit, without an external circuit. The stored
energy can transfer back and forth between the L and C, gradually dissipating in
the circuit R.
14.3.1i - Series resonant L-C -R circuit
The series L-C-R circuit current for a step input voltage Vs , with initial capacitor
voltage vo and series inductor current io is given by
V v

i ( t ) = s o et sin t + io e t o cos ( t + )
(14.52)

L
where
1
R
1
R
2 = o2 (1 2 )
o =
=
= =
2L
2Qs
2o L
LC
? is the damping factor. The capacitor voltage is important because it specifies the
energy retained in the L-C-R circuit at the end of each half cycle.

i
vc (t ) = Vs (V s vo ) o e t cos ( t ) + o et sin t
(14.53)

C
where
2
2
2
tan =
and o = +

Power Electronics
j?L

?C - j

457

i
Vs

Is

j?L

Is

?C - j

high
Q

high
Q
low
Q

low
Q

Vs

Is
vcapacitor

i series

i inductor

vparallel

?t

ideal commutation
instants

|Z(?)|
R

ideal commutation
instants

Qs

decreasing

BWs

2
1

+90

?Z( ? )
0

capacitive

|Z(?)|
R
1

?Z( ? )
0

?o

-90

?u

Qp

1
2
+90

decreasing

BW p

Z
inductive

?l
Z

?t

?=2pf

Z
?u

inductive

?l

?o

?=2pf
Z
capacitive

-90
(a)

(b)

Figure 14.26. Resonant circuits, step response, and frequency characteristics:

(a) series L-C-R circuit and (b) parallel L-C-R circuit.

At the series circuit resonance frequency ? o , the lowest possible circuit impedance
results, Z=R, hence it can be termed, low-impedance resonance. The series circuit
quality factor or figure of merit, Qs is defined by

Power Inverters

reactive power 2 maximum stored energy

=
average power
energy dissipated per cycle
2
2 Li
L 1
Z
=
= o =
= o
Ri 2 / fo
R
2
R

458

Qs =

(14.54)

where

L
( )
C
The half-power bandwidth BWs is given by

2 f o
BWs = o =
Qs
Qs
and upper and lower half-power frequencies are related by = lu .
lu = o
Zo =

(14.55)

(14.56)
R
4 L
Figure 14.26a shows the time -domain step-response of the series L-C-R circuit for
a high Q load and a low Q case. In the low Q case, to maintain and transfer
sufficient energy to the load R, the circuit requires re -enforcement every half sine
cycle, while with a high circuit Q, re-enforcement is only necessary once per
sinusoidal cycle. Thus for a high circuit Q, full bridge excitation is not necessary,
yielding a simpler power circuit as shown in figure 14.27a and b.
The energy transferred to the load resistance R, per half cycle 1/2fr , is

f lu = f o

W = i ( t ) R d t
2

(14.57)

The active power transferred to the load depends on the repetition rate of the
excitation, fr .
P = W fr
(W)
(14.58)
14.3.1ii - Parallel resonant L-C -R circuit
The load for the parallel case is a parallel L-C circuit, where the active load is
represented by resistance in the inductive path. For analysis , the series L-R circuit
is converted into its parallel R-L equivalent circuit, thus forming the equivalent
parallel L-C-R circuit shown in figure 14.26b. A parallel resonant circuit is used in
conjunction with a current source inverter, thus the parallel circuit is excited with a
step input current. The voltage across a parallel L-C-R circuit for a step input
current Is , with initial capacitor voltage vo and initial inductor current io is given by
I i

v ( t) = vc ( t ) = s o et sin t + vco e t o cos ( t + )

(14.59)
C
The inductor current is important since it specifies the tank circuit stored energy at
the end of each half cycle.

v
iL ( t ) = Is ( I s i o ) o et cos ( t ) + o e t sin t (14.60)

L
where

Power Electronics

459

1
2CR
The circuit Q for a parallel resonant circuit is
R
R
1
Qp = o RC =
=
=
(14.61)
o L Z o Qs
where Zo and ? o are defined as in equations (14.52) and (14.54), except L, C, and R
refer to the parallel circuit values.
=

T3 D3
T1 D1

Vs

T1 D1

C R

T4 D4

T2 D2

T4D4

(a)

(b)

I constant

I constant
Llarge

Llarge
C

Vs

T1 D1

Vs

T3 D3

T3D3

T1 D1

(c)

T4 D4

T2D2

(d)

Figure 14.27. Resonant converter circuits:

(a) series L-C-R with a high Q; (b) low Q series L-C-R; (c) parallel L-C-R and high
Q; and (b) low Q parallel L-C-R circuit.

Power Inverters

The half-power bandwidth BWp is given by

2 f o
BWp = o =
Qp
Qp

460

(14.62)

and upper and lower half power frequencies are related by = lu .

At the parallel circuit resonance frequency ? o , the highest possible circuit
impedance results, Z=R, hence it can be termed, high-impedance resonance.
The energy transferred to the load resistance R, per half cycle 1/2fr , is

W = v ( t) / R d t
2

(14.63)

The active power to the load depends on the repetition rate of the excitation, fr .
P = W fr
(W)
(14.64)
14.3.2

Series resonant inverters

Series resonant circuits use a voltage source inverter as considered in 14.1.1 and
shown in figure 14.27a and b. If the load Q is high, then the resonance of energy
from the energy source, Vs , need only be re-enforced every second half-cycle,
thereby simplifying converter and control requirements. A high Q circuit is
characterised by successive half-cycle capacitor voltage peak magnitudes being of
similar magnitude, that is the decay rate is

vcn
= e 2Q 1 for Q ? 1
(14.65)
vcn+1
Thus there is sufficient energy stored in C to be transferred to the load R, without
need to involve the supply Vs . The circuit is simpler and control is easier.
Also, for any Q, each converter can be used with or without the shown freewheel
diodes. Without freewheel diodes, the switches have to block high reverse voltages
due to the energy stored by the capacitor. MOSFET and IGBT s require series diodes
to achieve the reverse voltage blocking requirements. In high power resonant
applications, the reverse blocking abilities of the GTO and GCT make it an ideal
converter switch. Better load resonant control is obtained if freewheel diodes are
not used.
14.3.2i - Series resonant inverter single inverter leg
Operation of the series load asymmetrical circuit in figure 14.27a depends on the
timing of the switches.
1 - Lagging operation (advancing the switch turn-off angle)
If the converter is operated at a frequency above resonance (effected by
commutating the switches before the end of an oscillation cycle), the inductor
reactance dominates and the load appears inductive. The load current lags the
voltage as shown in figure 14.28. This figure shows the conducting devices and
that a switch is turned on when its parallel diode is conducting. Turn-on therefore
occurs at a low voltage, while turn-off is as with a hard switched inductive load.
Operation and switch timing is as follows:
Switch T1 is turned on while its anti-parallel diode is conducting and the current
in the diode reaches zero and the current transfers to, and begins to oscillate
through the switch T1. The capacitor charges to a maximum voltage and before

Power Electronics

461

the current reverses, the switch T1 is turned off. The current is diverted through
diode D4. T4 is turned on which allows the oscillation to reverse. Before the
current in T4 reaches zero, it is turned off and current is diverted to diode D1,
which returns energy to the supply. The resonant cycle is repeated when T1 is
turned on before the current in diode D1 reaches zero and the process continues.
asymmetrical bridge conducting devices
T1

D4

T4

D1

T1

D4

symmetrical H-bridge conducting devices

T1 T2

D3 D4

T3 T4

D1 D2

T1 T2

D3 D4

f
lagging
IT1

H-bridge
output voltage

IT1
t

0
IT4

Zero for half

bridge

f
lagging
IT1

switch T1/T2
hard turn-off

IT1
t

V ref

V ref

V ref
IT4

switch T4/T3
hard turn-off
t

Figure 14.28. Series L-C-R high Q resonance using the converter circuit in figure
14.27a and b, with a lagging power factor f .

2 - Leading operation (delaying the switch turn-on angle)

By operating the converter at a frequency below resonance (effectively by delaying
switch turn-on until after the end of an oscillation cycle), the capacitor reactance

Power Inverters

462

dominates and the load appears capacitive. The load current leads the voltage as
shown in figure 14.29. This figure shows the conducting devices and that a switch
is turned off when its parallel diode is conducting. Turn-off therefore occurs at a
low current, while turn-on is as with a hard switched inductive load. Fast recovery
diodes are therefore essential.
Operation and switch timing is as follows:
Diode D4 is conducting when switch T1 is turned on, which provides a step
input voltage Vs to the series L-C-R load circuit, and the current continues to
oscillate. The capacitor charges to a maximum voltage and the current reverses
through D1, feeding energy back into the supply. T1 is then turned off with zero
current.
The switch T4 is turned on, commutating D1, and the current oscillates through
the zero volt loop created through T4 and the load. The oscillation current
reverses through diode D4, when T4 is turned off with zero current.
T1 is turned on and the process continues.
Without the freewheel diodes the half oscillation cycles are controlled completely
by the switches. On the other hand, with freewheel diodes, the timing of switch
turn-on and turn-off is determined by the load current zeros, if maximum energy
transfer to the load is to be gained.
The series circuit steady-state current at resonance for the asymmetrical bridge can
be approximated by assuming ? o ? , such that in equation (14.52) io = 0:
1
Vs
i ( t ) =
e t sin t
0 t
(14.66)

L

1e
which is valid for the + Vs loop (through T1) and zero voltage loop (through T4)
modes of cycle operation at resonance, provided the time reference is moved to the
beginning of each half-cycle.
In steady-state the successive capacitor voltage maxima are

1
e /
Vc = Vs
and Vc = Vs
(14.67)
/
1e
1 e /
The peak-to-peak capacitor voltage is therefore
1 + e /
2
Vcp p =
Vs = Vs coth ( / 2 )
Vs
(14.68)
1 e /

The energy transferred to the load R, per half sine cycle (per current pulse) is
2

W =

/
0

i Rdt =
2

/
0

= CVs 2 coth

Vs

et sin t R dt

1e

(14.69)

14.3.2ii - Series resonant inverter H-bridge inverter

When the load Q is not high, the capacitor voltage between successive absolute
peaks decays significantly, leaving insufficient energy to maintain high efficiency
energy transfer to the load R. In such cases the resonant circuit is re-enforced with
energy from the dc source Vs every half-resonant cycle, by using a full H-bridge as
shown in figure 14.27b.

Power Electronics

463

asymmetrical bridge conducting devices

T1

D1

T4

D4

T1

D1

symmetrical H-bridge conducting devices

T1 T2

D1 D2

T3 T4

D3 D4

T1 T2

D1 D2

f
leading
IT1

H-bridge
output voltage

IT1
t

0
Zero for half
bridge

IT4

f
leading
IT1

switch T1/T2
hard turn-on

IT1
t

V ref

switch T4/T3
hard turn-on

V ref

V ref

IT4
t

Figure 14.29. Series L-C-R high Q resonance using the converte r circuit in figure
14.27a and b, with a leading power factor f .

Operation is characterised by turning on switches T1 and T2 to provide energy

from the source during one half of the cycle, then having turned T1 and T2 off, T3
and T4 are turned on for the second resonant half cycle. Energy is again drawn
from the supply Vs , and when the current reaches zero, T3 and T4 are turned off.
Without bridge freewheel diodes, the switches support high reverse bias voltages,
but the switches control the start of each oscillation half cycle. With freewheel
diodes the oscillations can continue independent of the switch states. The diodes
return energy to the supply, hence reducing the energy transferred to the load.
Correct timing of the switches minimises currents in the freewheel diodes, hence
minimises the energy needlessly being returned to the supply. Energy to the load

Power Inverters

464

is maximised. As with the asymmetrical bridge, the switches can be used to control
the effective load power factor. By advancing turn-off to before the switch current
reaches zero, the load can be made to appear inductive, while delaying switch turnon produces a capacitive load effect. The timing sequencing of the conducting
devices, for load power factor control, are shown in figures 14.28 and 14.29.
The series circuit steady-state current at resonance for the symmetrical H-bridge
can be approximated by assuming ? o ? , such that in equation (14.52) io = 0:
2
Vs
i ( t ) =
e t sin t
0 t
(14.70)

L
1e
which is valid for the Vs voltage loops of cycle operation at resonance, provided
the time reference is moved to the beginning of each half-cycle.
In steady-state the capacitor voltage maxima are

1 + e /
Vc = Vs
= Vs coth ( / 2 ) = Vc
(14.71)
/
1e
The peak-to-peak capacitor voltage is therefore
1 + e /
4
Vcp p = 2
Vs = 2Vs coth ( / 2 )
Vs
(14.72)
1 e /

The energy transferred to the load R, per half sine cycle (per current pulse) is
2

W =

/
0

i 2R dt =

Vs

e t sin t Rdt

1 e

(14.73)

= 2CVs2 coth

2
Notice the voltage swing is twice that with the asymmetrical bridge, hence
importantly, the power delivered to the load is increased by a factor of four.

T1

D1
L

Vs
D4

T4

(b)

Cs
C

(a)
(c)
Figure 14.30. Different resonant load arrangements:
(a) switch turn-off snubber capacitor C s; (b) split capacitor; and (c) series coupled
circuit for induction heating.

Power Electronics

465

14.3.2iii - Circuit variations

Figure 14.30a shows an asymmetrical bridge with a turn-off snubber Cs , where Cs
<< C , hence resonant circuit properties are not affected. The capacitive turn-off
snubber is only effective if switch turn-off is advanced such that switch hard turnoff would normally result, that is, the resonant circuit appears capacitive. The
snubber acts on both switches since small signal wise (short dc sources), switches
T1 and T4 are in parallel.
Figure 14.30b shows a series resonant load used with split resonant capacitance.
Resonance re-enforcement occurs every half cycle as with the full H-bridge
topology, but only two switches are used.
Figure 14.31c shows a transformer-coupled series circuit which equally could be a
parallel circuit with C in parallel with the coupled circuit, as shown. Under light
loads, the transformer magnetising current influences operation.
14.3.3

Parallel resonant inverters

Parallel resonant circuits use a current source inverter as considered in 14.2.1 and
shown in figure 14.27c and d. If the load Q is high, then resonance need only be
re-enforced every second half-cycle, thereby simplifying converter and control
requirements. A common feature of parallel resonant circuits fed from a current
source, is that commutation of the switches involves overlap where the output of
the current source is briefly shorted.
14.3.3i - Parallel resonant inverter single inverter leg
Figure 14.27c shows an asymmetrical converter for high Q parallel load circuits.
Energy is provided from the constant current source every second half cycle by
turning on switch T1. When T1 is turned on (and T3 is then turned off) the voltage
across the L-C-R circuit resonates from zero to a maximum and back to zero volts.
The energy in the inductor reaches a maximum at each zero voltage instant. T3 is
turned on (at zero volts) to divert current from T1, which is then turned off with
zero terminal voltage. The energy in the load inductor resonates within the load
circuit, with the load in an open circuit state, since T1 is off. The sequence
continues when the load voltage resonates back to zero as shown in figure 14.26b.
The parallel circuit steady-state voltage at resonance for the asymmetrical bridge
can be approximated by assuming ? o ? , such that in equation (14.59) vo = 0:
1
Is
v ( t ) =
e t sin t
0 t
(14.74)

1e
which is valid for both the +Is loop and open circuit load modes of cycle operation,
provided the time reference is moved to the beginning of each half-cycle.
In steady-state the successive inductor current maxima are

1
e /
IL = Is
and I L = I s
(14.75)
/
1 e
1 e /
The energy transferred to the load R, per half sine cycle (per voltage pulse) is

Power Inverters

466
2

W =

v2

dt =

/
0

Is
t

sin

t
dt

C
/R
1 e

(14.76)

= LI s2 coth

2
14.3.3ii - Parallel resonant inverter H-bridge inverter
If the load Q is low, or maximum energy transfer to the load is required, the full
bridge converter shown in figure 14.26d is used.
Operation involves T1 and T2 directing the constant source current to the load and
when the load voltage falls to zero, T3 and T4 are turned on (and T1 and T2 then
turned off). Overlapping the switching sequence ensures a path always exists for
the current source. At the next half sinusoidal cycle voltage zero, T1 and T2 are
turned on and then T3 and T4 are turned off.
The parallel circuit steady-state voltage for the symmetrical H-bridge can be
approximated by assuming ? o ? , such that in equation (14.59) vo = 0:
2
Is
v ( t ) =
e t sin t
0 t
(14.77)

C
1e
which is valid for both the + Is loops of cycle operation, provided the time
reference is moved to the beginning of each half-cycle .
In steady-state the successive inductor current maxima are

1+ e /
IL = Is
= I s coth ( / 2 ) = I L
(14.78)
/
1 e
The energy transferred to the load R, per half sine cycle (per voltage pulse) is
2

W =

/
0

dt =

/
0

Is

e t sin t / R dt

C
1 e

= 2LI s2 coth

2
As with a series resonant circuit, the full bridge delivers four times more power to
the load than the asymmetrical bridge circuit. Similarly, the load power and power
factor can be controlled by operating above or below the resonant frequency, by
delaying or advancing the appropriate switching instances.
Example 14.4:

Half-bridge with a series L-C-R load

An asymmetrical half-bridge inverter as shown in the figure 14.27a, with the dc

rail L-C decoupling shown in figure 14.32, supplies a 1 ohm resistance load with
series inductance 100 H from a 340 V dc source. If the bridge is to operating at
10kHz, determine:
i.
the necessary series C for resonance at 10kHz and the resultant Q
ii.
the peak load current, its steady-state time domain solution, and peak
capacitor voltages

Power Electronics

467

iii.
iv.
v.
vi.
vii.
viii.
ix.

the bridge rms voltage and fundamental voltage across the L-C-R load
the power delivered to the load and the frequency when half power is
delivered to the load. What is the switching advance/delay time?
the peak blocking voltage of each semiconductor type (and for the
case when the freewheel diodes are not employed)
the average, rms, and peak current in the switches and diodes
the resonant capacitor specification
the dc supply current and the dc link capacitor rms current
summarise conditions if the load is supplied from an H-bridge

Ldc
iC
Idc

T1

D1

T4

D4

Cdc
Vs
340V

100H

1O

Figure 14.32. Asymmetrical-bridge series-resonance circuit.

Solution
i.
From o = 2 fo = 1/ LC the necessary capacitance for resonance at
10kHz and 100H is
1
C=
= 2.5F
2
( 2 10kHz ) 100 H
The circuit quality factor Q is given by

Q=

Zo
L
100 H
=
/R =
/1 = 6.3
R
C
2.5 F

Therefore
a = 5103 O/H
? = 0.079
Zo = 6.3 O
ii.

? = 62.6 krad/s (9.968 kHz)

BW s = 9.97 krad/s (1.587kHz)

The steady-state current is given by equation (14.66)

V
1
i ( t ) =
s e t sin t

L
1e
= 245.5 e 5000 t sin ( 2 10kHz t )

Power Inverters

468

Since the Q is high, a reasonably accurate estimate of the peak current results
if the

current expression is evaluated at sin(p), that is t =25s, which yields i = 216.7A.

The rms load current is 216.7A/2 = 153.2A rms
From equation (14.67) the maximum capacitor voltages are

1
e /
Vc = Vs
and Vc = Vs
/
1e
1 e /
340V
340Ve0.25
=
=
0.25
1e
1 e0.25
= 1537V
= 1197V
iii.
The bridge output voltage is a square wave of magnitude 340V and 0V,
with a 50% duty cycle. The rms output voltage is therefore 340/2=240.4V.
Since the load is at resonance, the current is in phase with the fundamental of the
bridge output voltage. The fundament voltage magnitude is given by
1
2V
b1 =
Vs sin1 t = s = 216.5V peak
0

2V
s = 153V rms
The rms load current results because of the fundamental voltage, that is, the peak
sine current is 216.5V/1O = 216.5A peak or 153V/1O = 153A rms. This agrees
with the current values calculated in part b.
iv.

The power delivered to the load is given by

2
P = irms
R = ib21 R

= 153A2 1 = 23.41kW
Substitution into equation (14.69) gives 23.15kW at a pulse rate of 210kHz.
Alternately
P = Vs I = Vs 0.45 I rms
=340V0.45 153A=23.42kW
The half-power frequencies are when the reactive voltage equals the resistive
voltage.
R
f lu = f o
4 L
= 10kHz 796Hz
Thus at 9204 Hz and 10796 Hz the voltage across the resistive part of the load is
reduced to 1/2 of the inverter output voltage. The power (proportional to voltage
squared) is therefore halved at the half-power frequencies.
Operating above resonance, f > fo produces an inductive load and this is achieved
by turning T1 and T4 off prematurely. Zero current turn-on occurs, but hard
switching results at turn-off. To operate at the 10796Hz (92.6s) upper half-power
frequency the period has to be reduced from 100s (10kHz) to 92.6s. The period
of each half cycle has to be reduced by (100s - 92.6s) = 3.7s
Operating below resonance, f < fo produces a capacitive load and this is achieved
by turning T1 and T4 on late. Zero current turn-off occurs, but hard switching

469

Power Electronics

results at turn-on. By delaying turn-on of each switch by (109s - 100s),

4.5s, the effective oscillation frequency will be decreased to the lower half-power
frequency, 9204Hz.
v.
The bridge diodes, which do not conduct at resonance, clamp switch and
diode maximum supporting voltages to the rail voltage, 340V dc.
Note that if clamping diodes were not employed the device maximum off-state
voltages would occur during switch change over, when one switch has just been
turned off, and just before the on-going switch is turned on. The load current is
zero, so the load terminal voltage is the capacitor voltage.
Switch T1 would need to support

a forward voltage of Vs - v = 340V + 1197V =1537V = v and

a reverse voltage of v - Vs = 1537V - 340V = 1197V = - v , while

Switch T4 supports

a forward voltage of v = 1537V and

a reverse voltage of - v = 1197V.

Thyristor family devices must be used, or devices with a series connected diode,
which will increase the converter on-state losses.
vi.
At resonance the two freewheel diodes do not conduct.
The rms load current is 153.2 A at 10 kHz, where switch T1 conducts half the
cycle and T4 conducts the other half which is the opposite polarity of the cycle.
Each switch therefore has an rms current rating of 153.2/2 = 108.3A rms.
Since both switches conduct the same current shape, each has an average current
rating of a half-wave rectified sine of magnitude 216.5A, that is
1
1
I T1 =
216.5sintdt = 216.5A
0
2

= 0.45 216.5/ 2 = 97.4A

By Kirchhoffs current law, this current value for T1 is also equal to the average dc
input current from the supply Vs .

vii.
The capacitor has a bipolar voltage and current requirement of 1537V
and 216.7 A. The rms ratings are therefore 1087V rms and 153A rms. A
metallised polypropylene capacitor capable of 10kHz ac operation, with a
maximum dv/dt rating of approximately (1537+1197)? , that is 85.6V/s, is
required.
viii.
The dc supply current is the average value of the half-wave rectified
sinusoidal load current, which is the average current in T1. That is
I dc = 0.45 153.1A rms

= 68.9A dc
The rms current in the dc link capacitor is related to the dc input current and switch
T1 rms current (as found in part f), by
I c = I T21 I dc2
= 108.32 68.92 = 83.6A rms

Power Inverters

470

ix.
The load dependant parameters C, ? o , ?, a, Q, BW, ?, and half power
points remain unchanged.
From equation (14.70) the steady-state current is double that for the asymmetrical
bridge,
V
2
i ( t ) =
s e t sin t

L
1e
= 491 e 5000 t sin ( 2 10kHz t )

The peak current is i = 433.4A.

The rms load current is 433.4A/2 = 306.4A rms
From equation (14.71) both the maximum capacitor voltages are

1 + e /
Vc = Vs
= Vc
/
1e
1 + e0.25
= 340V
= 2734V
1 e0.25
The power delivered to the load is four times the asymmetrical case and is
2
P = i rms
R = 306.4A 2 1 = 93.88kW
The average switch current is 194.8A, but the average supply current is four times
the asymmetrical case and is 275.5.6A.
?
14.3.4

Single-switch current source series resonant inverter

The inverter in figure 14.31 is applicable to high Q load circuits such that the
output is essentially sinusoidal, with zero average current. Based on the operating
mechanisms, a sinusoidal current implies the switch has a 50% duty cycle. The
switch turns on and off at zero volts so switch losses are low and the operating
frequency can be high. The input inductor Llarge in conjunction with the input
voltage source, during steady state operation, act as a current source input, Is , for
the resonant circuit, such that Vs Is is equal to the power delivered to the load R.
When the switch T1 is turned on, with zero terminal voltage, it conducts both the
constant current Is and the current io resonating in the output circuit, as shown in
the circuit waveforms in figure 14.31. The resonating load current builds up. The
switch T1, which is in parallel with Cs , is turned off. Current from the switch is
diverted to Cs, which charges from an initia l voltage of zero. Cs thus forms a turnoff snubber in parallel with T1. The charge on Cs eventually resonates back to zero
at which instant the switch is turned on, again, with zero turn-on loss.
The resonant frequency is o = 1/ Lo Co and because of the high Q, a small
change in the switching frequency significantly decreases the output current, hence
output voltage.
As with any current source inverter, the peak switch voltage is in excess of Vs .
Since the current is sinusoidal, the average load voltage and inductor voltage are
zero. Therefore the average voltage across Co and Cs is the supply voltage Vs . The
peak switch voltage can be estimated to be in excess of Vs /0.45 which is based on
a half-wave rectified average sinusoidal voltage.

Power Electronics

471

Llarge
Vs

Is
iT

iD1

i Cs

Lo

Co

io

T 1 D1

Rload

Cs

io

switch conducting
d=

switch off

switch conducting

1/2fo

1/2fo

Is

Is

i T1
IT1 = Is + i o

Is
i Cs = Is + i o
i Cs

i D1

VT1
Vs

io

io

Is

IT1

Rload

Is

ICs

Rload

Figure 14.31. Single-switch, current-source resonant converter circuit and

waveforms.

Power Inverters

472

If the load conditions change and the switch duty cycle is varied from d = ,
circuit voltages increase and capacitor Cs voltage discharges before the circuit
current reaches zero. The capacitor and switch are bypassed with current flowing
through the diode D1. This diode prevents the switch from experiencing a negative
voltage and the capacitor from charging negatively.
Although such resonant converters offer features such as low switching losses and
low radiated EMI, optimal control and performance are difficult to maintain and
extremely high circuit voltages occur at low duty cycles.

14.4

Multi-level voltage-source inverters

The conventional three-phase, six-switch dc to ac voltage-source inverter is shown

in figure 14.3. Each of the three inverter legs has an output which can provide one
of two voltage levels, Vs , when the upper switch (or diode) is on, and 0 when the
lower switch (or diode) conducts. The quality of the output waveform is
determined by the resolution and switching frequency of the pwm technique used.
Vs

Vs

Vs
Vs /N-1

Vs
a

Vs /N-1

Vs
Va0

Vs

Va0

Va0

Vs /N-1

0
+Vs
+V
+Vs

+Vs
0V

0V

-Vs
-Vs
(a)

(b)

-Vs
(c)

-Vs

Figure 14.33. One phase leg of a voltage-source bridge inverter with:

(a) two levels; (b) three levels; and (c) N-levels, with N-1 capacitors and
waveform for five levels.

A multilevel inverter (directly or indirectly) divides the dc rail, so that the output of
the leg can be more than two levels , as shown in figure 14.33 for a diode clamped
multilevel inverter model. In this way, the output quality is improved because both
pulse width modulation and amplitude modulation can be used. The output pole is
made from more than two series connected switches, so the total dc rail can be the
sum of the voltage rating of the individual switches. Very high output voltages can

473

Power Electronics

be achieved, where each device does not experience a voltage in excess of its
individual rating.
A multilevel inverter allows higher output voltages with low distortion (due to the
use of both pulse width and amplitude modulation) and reduced output dv/dt.
There are three main types of multilevel converters
Diode clamped
Flying capacitor, and
Cascaded H-bridge
14.4.1

Diode clamped multilevel inverter

Figure 14.33 shows the basic principle of the diode clamped (or neutral point
clamped) multilevel inverter, where only one dc supply, Vs , is used and N is the
number levels present in the output voltage between the leg output and the inverter
negative terminal, Va-neg . The capacitors split the dc rail voltage into a number of
lower voltage levels, each of which can be tapped and connected to the leg output
through switches. Only one string of series connected capacitors is used for any
number of output phase legs.
The number of levels in the line-to-line voltage waveform will be
k = 2N 1
(14.79)
while the number of levels in the line to load neutral of a star (wye) load will be
p = 2k 1
(14.80)
The number of capacitors required, independent of the number of phase, is
N cap = N 1
(14.81)
while the number of clamping diodes per phase is
Dclamp = 2 ( N 1)

(14.82)

The number of possible switch states is

n states = N phases

(14.83)

and the number of switches in each leg is

Sn = 2 ( N 1)

(14.84)

The basic three-level inverter is shown in figure 14.34, along with the basic threelevel voltage from the leg output to centre tap of the capacitor string, R (neutral
point). When switch T1 is on, its complement T1 ' is off, and visa versa. Similarly
for the pair of switches T2 and T2 '. Specifically T1 and T2 on give the output +Vs ,
T1 ' and T2 ' on give the output -Vs , and T2 and T1 ' on give the output 0. Essential
to attaining these output levels , are the clamping diodes Du and Dl . These two
diodes clamp the outer switches to the capacitor string mid-point, which is half the
dc rail voltage. In this way, no switch experiences a voltage in excess of half the
dc rail voltage. Inner switches must be turned on (or off) before outer switches are
turned on (or off).
The five-level inverter uses four capacitors and eight switches in each inverter leg.
A set of clamping diodes (three in total for each leg) clamp the complementary
switches in each leg. The output is characterised by having five levels, Vs ,
Vs , and zero. Some of the clamp ing diodes experience voltages in excess of that
experienced by the main switches. Series connection of some of the clamping

Power Inverters

474

diodes avoids this limitation, but at the expense of increasing the number of
clamping diodes from 2 (N-1) to (N-1)(N -2) per phase. Thus, depending on the
diode position in the structure, two diodes have blocking requirements of
N 1 k
VRB =
Vs
(14.85)
N 1
where 1 = k =N-2. These diodes require series connection of diodes, if all devices
in the structure are to support Vs /(N-1). For N >2, capacitor imbalance occurs.
The general output voltage, to the centre of the capacitor string is given by
V
Van = s (T1 + T2 + .. ..+ TN 1 ( N 1))
(14.86)
N 1
Table 14.4. Conduction paths in the diode clamped three-level inverter
Vout

On
switches

Vs

T1 T2

T1 T2

D1 D2

none

T1' T2

Dcu T 2

T1' D cl

Dcu Dcl

- Vs

T1' T2 '

T1' T2 '

D1' D 2'

none

Cu

Current path
+ iL
- iL

T1

D1

T2

D2

Active clamping
diodes

Dcu

Vs
R
D1
T 1

Cl?
Dc?
cl
D

D2
T 2

neg
ia

ib

ic

VaR
+Vs
t
0
-Vs

Vb a

Vao

Figure 14.34. Three-phase, voltage-source, three-level, diode-clamped (NPC)

bridge inverter.

Power Electronics

475

14.4.2

Flying capacitor multilevel inverter

One leg of a fly-capacitor clamped five-level voltage source inverter is shown in

figure 14.35, where capacitors are used to clamp the switch voltages to Vs . The
available output voltages are Vs , Vs , and 0, where the output is connected to
the dc link (Vs and 0) indirectly via capacitors. Figure 14.35 shows that in general,
switches Tn and Tn+1 connect to capacitor Cn . The configuration offers more
available switch states than the clamped diode inverter, and this redundancy allows
better, flexible control of capacitor voltages. For example, Table 14.5 shows that
there are six states for obtaining 0V output, and four states for each of Vs. The
output states Vs do not involve the capacitors, hence they offer no redundant
states. The basic switch restriction is that only one complementary switch (e.g., T4
or T4 ' ) is on at any time, so as to prevent shorting of a flying capacitor.
The number of levels in the line-to-line voltage waveform will be
k = 2N 1
(14.87)
while the number of levels in the line to load neutral of a star (wye) load will be
p = 2k 1
(14.88)
The number of capacitors required, which is dependent of the number of phase, is
for each phase,
N cap = ( N 1)( N 2 )
(14.89)
Table 14.5. Five-level flying-capacitor inverter output states (phase A to R)

mode

VAR

Vs

2
N-1
states

Vs

3
N2-4N+1

states

4
N-1
states

-Vs

-Vs

T1

switching states
T2
T3
T4

C1

capacitors
C2
C3

paths

Vs

Vs

-VC3

Vs

-VC2+VC3

Vs-VC1+VC2

-Vs+VC1

Vs

Vs-VC1+VC2 -VC3

-Vs+VC1-VC3

Vs-VC1+-VC3

-Vs+VC1-VC2+VC3

-Vs

Vs-VC1

-Vs+VC1-VC2

-Vs

-VC2 -VC3

-Vs

+VC3

-Vs

-VC2

+VC2

Power Inverters

476

The number of possible switch states is

n states = N phases

(14.90)

and the number of switches in each leg is

Sn = 2 ( N 1)

(14.91)

The current output paths in Table 14.5 are made up by the series (and parallel)
connection of the flying capacitors through the turn-on of the appropriate switches.
Capacitors shown as negative are discharging in the formed path, while those
shown as positive are charging. Use of the shown redundant states allows control
of the voltage level on all the flying capacitors, while providing the desired output
voltages.
A feature of the flying capacitor multilevel inverter is its ride through capability
due to the large capacitance used. On the other hand, the capacitors have a high
voltage rating and suffer from high current ripple, since they conduct the full load
current when connected into an active output voltage state. Capacitor initial
charging is also problematic especially given the capacitors fo r each leg are
independent.

VC1

VC1
T1 D1

Vs

T1 D1

VCu
Cu
C1

VCu

T2 D2

VC2

C
C?l

Cu

T2 D2

T2?D2?

VVClC?
VC3

T1?D1?

T 3 D3

Vs
C1

VC?
Cl

C2

C3

T4 D4

phase
a

C?l

(a)

T4?
' D'4?
T3?
' D'3 ?

T '2? D'2?
T'1? D'1?

(b)

Figure 14.35. One leg of a voltage-source:

(a) three-level and (b) five-level, flying capacitor clamped bridge inverter.

phase
a

Power Electronics

477

14.4.3

Cascaded H-bridge multilevel inverter

The N-level cascaded H-bridge, multilevel inverter comprises (N-1) series

connected single phase H-bridges per phase, for which each H-bridge has its own
isolated dc source. Three output voltages are possible, Vs , and zero, giving a total
number of states of 3( N1) , where N is odd. Figure 14.36 shows one phase of a
seven-level cascaded H-bridge inverter.
The cascaded H-bridge multilevel inverter is based on multiple two level inverter
outputs (each H-bridge), with the output of each phase shifted. Despite four diodes
and switches, it achieves the greatest number of output voltage levels for the fewest
switches.
Its main limitation lies in its need for isolated power sources for each level and for
each phase, although for VA compensation, capacitors replace the dc supplies, and
the necessary capacitor energy is only to replace losses due to inverter losses. Its
modular structure of identical H-bridges is a positive feature.

Vs

D2 T2

T1 D 1
V1

Vs

T 3 D3

D4 T4

T1 D 1

D2 T2
V1

Vs

T 3 D3

D4 T4

T1 D 1

D2 T2
V1

T 3 D3

D4 T4

Figure 14.36. One leg of a voltage-source, seven-level, cascaded H-bridge

inverter.

Power Inverters

478

The number of levels in the line-to-line voltage waveform will be

k = 2N 1
(14.92)
while the number of levels in the line to load neutral of a star (wye) load will be
p = 2k 1
(14.93)
The number of capacitors or isolated supplies required per phase is
N cap = ( N 1)
(14.94)
The number of possible switch states is
n states = N phases

(14.95)

and the number of switches in each leg is

Sn = 2 ( N 1)

(14.96)

Table 14.6. Three output states of H-bridge and their current paths.

Vs

On
switches
T2 T 3

none

D4 D1

D2 D3

-Vs

T1 T 4

T1 T 4

D2 D3

Vl

Bidirectional current paths

+ iL
- iL
T2 T 3
D2 D3

A comparison between the three basic multilevel inverters is possible from the
numerical summary of component numbers for each inverter, as in Table 14.7.
The diode clamped inverter requires many clamping diodes; the flying capacitor
inverter requires many independent capacitors; while the cascaded inverter requires
many isolated power supplies.
Table 14.7. Multilevel inverter component count, per phase.
Inverter
type
diode
clamped
fly
capacitor
cascade

levels
VA-B

VA-N

switches
& diodes

diodes
clamping

flying
capacitors

Level
capacitors

Isolated
supplies

2N-1

4N-3

2(N-1)

(N-1)(N-2 )

(N-1)

2N-1

4N-3

2(N-1)

(N-1)(N-2)

(N-1)

2N-1

4N-3

2(N-1)

(N-1)*

(N-1)*

VA-0V

* either / or

14.4.4

PWM for multilevel inverters

Two basic approaches can be used to generate the necessary pwm signal for
multilevel inverters. Each approach is based on the extension of a two level
equivalent.
Modulating waveform comparison with offset triangular carriers
Space vector modulation based on a rotating vector in multilevel space

479

Power Electronics

14.4.4i Multiple offset triangular carriers

Various sinusoidal pwm techniques were considered in section 14.1.3v and
14.1.3vi of this chapter. Figure 14.37 shows how a triangular carrier is associate
with each complementary switch pair, four carriers (N-1) for the five-level inverter
as illustrated. The parts of figure 14.37 show how the four individual carriers can
be displaced with respect to one another. The figure also shows how triplen
injection is incorporated. The appropriate five-level switch states, as in tables 14.4
to 14.6, can be used to decode the necessary switching sequences. To minimise
losses, switching only occurs between adjacent levels.
Vs
Vs
0
-Vs
1

-Vs

-1

Figure 14.37. Multi-carrier based pwm generation for one phase of a voltagesource, five-level, inverter.

14.4.4ii Multilevel rotating voltage space vector

Space vector modulation for the two-level inverter was considered in section
14.1.3vi of this chapter. The basic hexagon shape for two levels is extended to
higher levels as shown in figure 14.38, for three levels . The number of triangles,
vectors, and states increases rapidly as the level number increases.

Power Inverters

480

Table 14.8. Properties of N-level vector spaces

levels
N
2
3
5

states
N3
8
27
125

triangles
6(N-1)2
6
24
96

vectors
3N(N-1)+1
7
19
61

vectors
in each hexagon
(1+6)
(1+6)+12
(1+6)+12+18+24

From table 14.8, the states for the two and three level inverters can be specified as
follows.
The 2-level inverter
The zero state matrix is
[ 000 111]
The first and only hexagon is shown in figure 14.18a.
[100 110 010 011 001 101]
The three level inverter
The zero state matrix is
[ 000 111 222]
The first hexagon matrix is
100 110 010 011 001 101
211 221 121 122 112 212

The second hexagon matrix is

[ 200 210 220 120 020 021 022 012 002 102 202 201]
These pole states are shown figure 14.38.
120

020
010
121

021

110
221
000
111
222

011
122

022

001
112

012

002

220

210
100
211

101
212
102

200

201
202

Figure 14.38. Rotating voltage space vector approached applied to three phases
of a voltage-source three-level, inverter.

A ?0 ?represents the minimum voltage obtainable from the multilevel converter and
N-1 represents the maximum value. For example, in a two -level converter, ?0 ?is
equivalent to 0V and ?1 ?is equivalent to Vs , where Vs is the converter DC link
voltage. In a three-level converter ?0 ?is equivalent to -Vs , ?1 ?is equivalent to 0 V,
and?2 is equivalent to Vs where Vs is the link voltage of the multilevel converter.

Power Electronics

481

When the rotating vector is drawn in the vector space, it is decomposed into
vectors bordering the triangle it lies in. When operating in the outer hexagon, the
vectors states used in the inner most hexagon mean that that level of the converter
is operating with a six-step quasi-square output voltage waveform, to which is
added a modulated square waveform for the next higher level.

14.5

Reversible converters

Power inversion by phase angle control is attained with a fully controlled singlephase converter as discussed in section 11.3.3. Power regeneration is also possible
with the fully controlled three-phase converter shown in figure 11.17. If a fully
controlled converter supplies a dc machine, two-quadrant control is possible (QI
and QIV), motoring in one direction of rotation and generating in the other
direction. Power regeneration into the supply is achieved by reversing the dc
output voltage by controlling the converter phase delay angle.
The dual or double converter circuit in figure 14.39a and b will accommodate fourquadrant dc machine operation, where the circuit performs as two fully controlled
converters in anti-parallel. Each converter is able to rectify and invert, but because
of their inverse parallel connection, one converter (the positive converter P)
operates in quadrants QI and QIV, while the other (the negative converter N)
operates in quadrants QII and QIII, as shown in figure 14.40.
The two converters can be operated synchronously, called simultaneous control or
independently where one is always blocking, called independent control.
14.5.1

Independent control

Simultaneous converter control can be used if continuous load current can be

guaranteed. Only one converter, depending on the quadrant, need operate at anyone
time (the other is in a blocking state), as shown in figure 14.39a. No circulating
currents arise due to possible mismatched converter output voltages. The
continuous current condition may be difficult to ensure at light load levels.
Additional series armature inductance, L in figure 14.39a and b, helps with current
smoothing and ensuring continuous machine current.
A machine rotational direction change is affected by the following converter
operating procedure.
Initially the motor is operating in quadrant I, with 0 = a 1 =90 for the
positive converter P. The negative converter, N, is in the fully blocking
state, with all thyristors turned off.
The positive converter is put into the inverting mode with 90 = a 1 =180,
changing the average output voltage from positive to negative. The
machine current rapidly falls to zero. The machine rotational speed slows,
the rate depending on the load inertia.
After a dead time, the positive converter blocks and the negative converter
N starts in a motor braking mode in quadrant II. The motor speed falls
rapidly to zero.

Power Inverters

482

a1

a2
(a)

dc link

a1
a2

(b)

a1
a2

(c)

(d)
dc link

input L-C
filter

output
filter
rectifier/
converter

3F
input

inverter

3F
output

Figure 14.39. Reversible converter allowing four-quadrant control of: (a) a dc

machine with independent converters; (b) a dc machine with simultaneously
controlled converters; and (c) voltage and (d) current feed induction machine.

Power Electronics

483

The second converter operates in quadrant III and rapidly accelerates the
motor in the opposite direction, with 0 = a 2 = 90.
The dead time before turning on the negative converter N is to ensure the positive
converter P is fully off, otherwise the three-phase input voltage lines may short
through the converters. Such a current condition cannot be controlled with linecommutated thyristors. Operation is characterised by transitions from QI to QII to
QIII for reversal, and transitions from QIII to QIV to QI for returning to the
original direction of rotation.
speed
vo

Ia

Ia
+

a1

vo

vo

a2
regenerative br aking
/inversion

II

motor/rectification

torque

motor/rectification

III

IV

regenerative br aking
/inversion

Ia

Ia

Ia
P

N
E

vo

a2

a1

vo

Figure 14.40. Four quadrants of reversible converter operation.

14.5.2

Simultaneous control

Simultaneous converter control, also called circulating current control, functions

with both converters always in operation which give a faster dynamic response
than when the converters are used mutually exclusively. To avoid supply short
circuits requires that the output voltage of both converters (rectifier Vr and inverter
Vi ) be the same in order to minimise circulating currents.
Vr + Vi = 0

V cos 1 + V cos 2 = 0
cos 1 + cos 2 = 0
that is 1 + 2 =180

(14.97)

Power Inverters

484

As shown in equation (14.97), this implies that both converters operate with firing
angles that sum to 180. Each converter produces the opposite polarity output
voltage, which is cancelled by reversing the relative output connections. Under
such conditions the load current can be maintained continuous. To minimize any
circulating current due to ripple voltage produced by instantaneous voltage
difference between the two converters, inductance is usually inserted between each
converter and the dc machine load, as shown in figure 14.39b. Adversely the cost
and weight are increased, and the supply power factor and drive efficiency are
decreased, compared to that obtained with independently controlled converters.
A machine rotational direction change is affected by the following converter
operating procedure.
Initially the motor is operating in quadrant I for the rectifying, positive
converter, with 0 = a 1 = 90. The other converter is operating in the
inverting mode with 90 = a 2 = 180, such that a1 + a2 = 180. The output
voltage for both converters is the same, and the negative converter N
carries only the circulating current.
For rotational direction reversal, a 1 = 90 and a 2 = 90, such that a 1 + a 2 =
180. The armature back emf voltage now exceeds the converter output
voltages, and current diverts to the negative converter N and the machine
regeneratively brakes, operating in quadrant II. The current rapidly falls to
zero and the positive converter P carries only the ac circulating current.
The speed rapidly falls to zero, with a 1 = a2 = 90 giving zero output
voltage, so as to control the armature current since the back emf is zero.
Then with a 2 < 90 the machine rapidly accelerates in quadrant III, in the
reverse direction to the original rotation.
For reversing the direction of rotation from Q III the operation sequence is QIII to
QIV to QI. Since no converter dead time is introduced, a fast dynamic response can
be attained. A small dc circulating current is deliberately maintained, that is
greater in magnitude than the peak of the ac ripple current. The ac current can then
flow continuously in both converters, both of which can operate in the continuous
conduction mode without the need for continuous converter current reversal
operation.
14.5.3

Inverter regeneration

The bridge freewheel diodes of a three-phase inverter restrict the dc rail or dc link
voltage from reversing. The dual or double converter circuit in figure 14.39c will
allow inversion with a three-phase voltage fed inverter. One converter rectifies, the
other converter inverts, functioning as a self-commutated inverter, transferring
power from the dc link to the ac supply. Complete four-quadrant control of the
three-phase ac machine on the inverter is achieved in conjunction with control of
the dc to ac inverter. That is, motor reversal is achieved by effectively
interchanging the pwm control signals associated with two phases. The real power
flow back into the ac supply is controlled by the converter phase delay angle, while
the reactive power flow is controlled by the voltage magnitude. The angle and
voltage are not independent. In the case of a pwm controlled inverter fed ac

Power Electronics

485

machine, the ac to dc converter can be uncontrolled, using all diodes, since dc

output voltage reversal is not utilised.
Figure 14.39d shows a fully reversible current controlled converter/inverter
configuration, using self-commutating devices. The use of self-commutated
switches (rather than mains commutated converter thyristors) offers the possibility
to minimise the input current distortion and to reduce the inductor size hence
improve the dynamic current response. The switch series diodes are essential since
the shown IGBT s have no useable reverse blocking capability. The use of reverse
blocking GCT s avoids the need for the series blocking diodes, which reduces the
on-state voltage losses but increases gate drive complexity. Series connection of
devices is necessary above a few kV, and above 1 MVA the GCT dominates.
14.6

Standby inverters and uninterruptible power supplies

Standby inverters and uninterruptible power supplies (upss) provide a 50/60 Hz

supply in the event of an ac mains failure. An ups must provide ac output such that
mains failure is undetected by the load. To achieve this , an ups continually feeds
the load from an inverter. A load that can tolerate a short interruption of the ac
supply is fed from a standby inverter which becomes operational within 1-5 ms
after the ac supply failure. In communications, computing, and automated
production lines, upss are essential for even brownouts (V and f outside bounds
for reliable equipment operation), while in lighting and heating applications,
standby inverters are used since a few missing ac cycles (due to a blackout total
interruption of the mains power)) may be tolerated. In each power supply case, the
alternative energy source is a standby dc battery. The ups keeps the battery charged
when the ac input is supplying the output power.
14.6.1

Single-phase UPS

A basic single-phase UPS is shown in figure 14.41. A key safety objective is to

retain the supply neutral at both the supply input and the ac output, without
resorting to any from of isolating transformer. Consequently, the input ac mains is
half-wave rectified by diodes DR+ and D R . Boost converters on the positive and
negative groups ensure supply sinusoidal input current and unity power factor.
The output H-bridge (T1 -T4 ) uses pwm and feedback control to produce a fixed
frequency and magnitude output (and ac mains phase synchronisation if required),
which is filtered by an L-C filter. In the event of a loss of the ac supply, the
backup batteries, V+ and V -, provide energy to the boost converters, hence to the
output inverter. The battery backup voltage magnitude is much less than the ac
supply magnitude and diodes , DB+ and D B , isolate the batteries from the rectified ac
supply voltage. The shown ups has two basic limitations that manufactures strive
to overt.
If the battery is to be connected to neutral, then two batteries are
necessary. Proprietary attempts using only one battery involve circuit
complications and limitations. At best, with one battery, it is one forward
biased diode voltage drop from neutral.

Power Inverters

486

Because the batteries supplies are not isolated during normal operation,
during part of the mains cycle near zero voltage, the batteries provide
energy. This decreases their lifetime and necessitates more complicated
trickle charge circuits. The input current is also distorted at the 0V
crossover. Replacement of the blocking diodes DB by switches involves
complexity and battery backup operation requires detection and is not fail
safe.
wave rectifier

DR
ac

boost converter

H-bridge inverter

T3

DB

+
T

L-C filter

T1

D1

D3

Lo
Co

N
V

DB
DR

T4

D4

D2

T2

Figure 14.41. Single-phase uninterruptible power supply.

14.6.2

Three-phase ups

Figure 14.42 shows a basic three-phase ups, used up to a few tens of kilowatts. The
ac supply is rectified and filtered. A forward converter controls the dc link voltage
to just above the battery voltage level. This dc voltage is boosted to a dc level such
that after inversion it provides the required output voltage magnitude. If the input
ac fails or droops, the dc link power is provided by the battery via diode VB . The
output inverter is usually operational in a pwm mode, which allows precise
frequency control, voltage control, ac mains phase synchronisation, and minimisation of low frequency output harmonics. With pwm control min imal filtering
is required, which minimises the filter weight, cost, size, and losses. A three-phase
ups can utilise third harmonic injection (14.1.4(iv)).
A three-phase boost input converter can be used to maintain sinusoidal ac supply
input currents at unity power factor.

o/p

Power Electronics

487

Figure 14.42. Three-phase uninterruptible power supply.

14.7

Power filters

Power L-C filters are used to reduce harmonics or ripple from

the rectifier output (dc filter)
the inverter output (ac filter).
L-C low-pass, second-order filters are shown in figures 14.39, 14.41, and 14.42. In
figure 14.42, the L-C smoothing filter at the rectifier output, filters the ac mains
frequency components leaving dc. The same type of filter is used in the inverter
output to filter pwm harmonics, leaving the relative low frequency modulation
frequency.
The L-C filter fundamental cut-off frequency is dependent on L, C, and the load
impedance ZL
vo
1
1
=
=
(14.98)
L
1
2
vi 1 + j L ( Z L + jC ) 1 LC + j Z L
The simplest design approach is to assume a non-load condition, ZL? 8, whence
the filter cut-off frequency is fo = 1/ 2 LC .
Frequency components below fo , including dc, are passed. Those components
above fo are attenuated by a second order fall-off in gain. Any frequency
components inadvertently around the resonant frequency, fo , will be amplified. For
this reason, the filter may be damped with parallel connected R-C snubbers.

Power Inverters

488

Reading list
See chapter 11 reading list.

Problems
14.1.
The inverter in figure 14.3 is supplied from a 340 V dc source. The load
has a resistance of 10 ohms and an inductance of 10 mH. The basic operating
frequency is 50 Hz, with three notches per half cycle giving half the maximum
output, similar to that shown in figure 14.9.
Determine the load current waveform over the first two cycles and determine the
power delivered to the load based on the current waveform of the final half cycle.
14.2.
The inverter and load in problem 14.1 are controlled so as to eliminate the
third and fifth harmonics in the output voltage.
Determine the load current waveform over the first two cycles and the power
delivered to the load based on the current waveform of the last half cycle.
14.3.
Output voltage harmonic reduction can be achieved by employing multiphase, selected notching modulation control on a three-phase bridge as discussed in
14.1.4. An output as in figure 14.10 with a = 16.3 and = 22.1 eliminates the 5th
and 7th harmonics.
Determine the fundamental voltage output component and compare it with that of a
square wave. Determine the output rms voltage.
14.4.
With the aid of figure 14.7 determine the line-to-neutral and line-to-line
output voltage of a dc to three-phase inverter employing 120 device conduction.
Calculate the interphase:
i.
mean half-cycle voltage
ii.
rms voltage
iii.
rms voltage of the fundamental.
14.5.
The three-phase inverter bridge in figure 14.4 has a 600 V dc rail and a 10
O per phase load. For 180 and 120 conduction calculate:
i. the rms phase current
ii. the power delivered to the load
iii. the switch rms current.
[24.5 A, 18 kW, 17.3 A; 28.3 A, 24 kW, 14.15 A]