Debugger Hc12
Debugger Hc12
Debugger Hc12
MCS12 ......................................................................................................................................
Warning ..............................................................................................................................
Troubleshooting ................................................................................................................
SYStem.Up Errors
FAQ .....................................................................................................................................
10
10
10
11
11
12
14
SYStem.BdmClock
15
16
16
17
17
18
19
19
20
SYStem.CPU
SYStem.CpuAccess
SYStem.LOCK
SYStem.MemAccess
SYStem.Mode
SYStem.Option BASE
SYStem.Option CLKSW
SYStem.Option DUALPORT
MCS12 Debugger
14
SYStem.Option GLOBAL
20
20
21
COP support
22
23
SYStem.Option SOFTWORD
SYStem.Option VFP
SYStem.Option WATCHDOG
Program Breakpoints
23
23
Data Breakpoints
24
25
25
25
TrOnchip.Mode
26
26
27
27
27
28
29
30
TrOnchip.RESet
TrOnchip.VarCONVert
TrOnchip.XBreakt
TrOnchip.RESERVE
31
31
32
34
34
SYStem.Option PAGING
Banked applications
34
SYStem.Option ROMHM
35
Transparent mode
35
SYStem.Option TRANS
Local and Global Memory Map on S12X Targets
38
39
SYStem.Option MEMEXP
Memory expansion
40
SYStem.Option ROMTST
40
41
Basics
41
Logical Address
41
Physical Address
41
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44
45
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45
1989-2016 Lauterbach GmbH
MCS12 Debugger
46
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Support ...............................................................................................................................
47
Available Tools
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Compilers
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50
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Products .............................................................................................................................
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Product Information
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Order Information
52
MCS12 Debugger
MCS12 Debugger
Version 24-May-2016
10-Feb-16
SP:0017BE \\MCC\mcc\sieve+36
E::w.d.l
addr/line
571
SP:0017BE
572
SP:0017C0
SP:0017C2
SP:0017C4
SP:0017C6
SP:0017C8
code
........... MIX EI
label
mnemonic
comment
flags[ k ] = FALSE;
clr.b
(a2)
k += prime;
adda.l d4,a2
; prime,a2
add.l
d4,d3
; prime,k
moveq
#12,d0
; #18,d0
cmp.l
d3,d0
; k,d0
bge
$17BE
4212
D5C4
D684
7012
B083
6CF4
MCS12 Debugger
E::w.v.ref
flags = (1, 1, 1, 1, 1
k = 3
prime = 3
i = 0
count = 0
vint = 1
Debugger Basics - Training (training_debugger.pdf): Get familiar with the basic features of a
TRACE32 debugger.
Architecture-specific information:
Processor Architecture Manuals: These manuals describe commands that are specific for the
processor architecture supported by your debug cable. To access the manual for your processor
architecture, proceed as follows:
-
RTOS Debugger (rtos_<x>.pdf): TRACE32 PowerView can be extended for operating systemaware debugging. The appropriate RTOS manual informs you how to enable the OS-aware
debugging.
MCS12 Debugger
Warning
NOTE:
Disconnect the debug cable from the target while the target power is
off.
2.
Connect the host system, the TRACE32 hardware and the debug
cable.
3.
4.
5.
6.
7.
Power down:
1.
2.
3.
4.
MCS12 Debugger
Warning
Troubleshooting
SYStem.Up Errors
The SYStem.UP command is the first command of a debug session where communication with the target is
required. If you receive error messages while executing this command this may have the following reasons.
The target is in reset - another device may hold the reset line active.
There is a problem with the electrical connection between ICD12 and the target - check if the
BDM connector is plugged correctly and if the target is built corresponding to the definition of the
used BDM connector.
The 68HC12 has no clock - check the frequency on the EXTAL pin with a scope.
The clock for the BDM transmission is not set correctly - refer to SYStem.BdmClock
FAQ
No information available
MCS12 Debugger
Troubleshooting
NOTE:
On all TRACE32 tool configurations except for the emulator device B:: is
already selected.
MCS12 Debugger
The internal clock generator can only generate each frequency entered in the
clock field. The software will select the best one for your application. So don t
worry if the value you see differs from the one you entered.
Set the SYStem Options in the option field corresponding to your target configuration and application
program. Generally the SYStem Options can remain at the default values for the first start, except for banked
applications.
If banking is in use, the debugger must know how the CPU is configured to access the banks. Items of
interest are:
Which of the higher address lines are used as address lines, which are used as ports (only
HC12A4/F8)? This information is given with the command SYStem.Option Axx.
Which of the chip select lines are used as chip selects, which are used as ports (only HC12A4/
F8)? This information is given with the command SYStem.Option CSxx.
How are the according bits in the MISC register set (only HC12DA128/HC12DG128)? This
information is given with the command SYStem.Option ROMTST and the SYStem.Option
ROMHM.
MCS12 Debugger
To use banking on HC12DA128 or HC12DG128 the SYStem.Option MEMEXP must be switched to on.
For details please refer to the chapters Using the MMU for HC12A4/F8 and Using the MMU for HC12DA/
DG128.
By default the In Circuit Debugger for 68HC12 (ICD12) modifies the code to realize a breakpoint. This will
not work for ROM or FLASH. To provide breakpoints in ROM/FLASH areas the CPU s on-chip breakpoints
can be used (not HC12A4).
This command asserts a reset to the CPU and drives the line BKGD to GND. So the CPU will enter the
special variant of the operating mode defined by the pins MODA and MODB, which must be configured by
the target.
LAUTERBACH recommends to use single chip mode for starting from reset. In this case the CPU will enter
Special Single Chip Mode without executing any code. So all registers will contain reset values. In all other
cases the CPU will try to execute code after reset, until the debugger gets control on it. So some registers
may contain unexpected values.
MCS12 Debugger
10
d.load.u <iar6812>.dbg
Register.Set SP 0xBFF
Register.Set PC main
MCS12 Debugger
11
WinCLEAR
SYStem.Reset
SYStem.BdmClock 2000000.
SYStem.CPU M68HC12B.
MAP.BOnchip 0x08000--0x0ffff
SYStem.Up
Data.LOAD.Elf hic.abs
Register.Set PC main
Register.Set SP 0xBFF
Data.List
Register /SpotLight
MCS12 Debugger
12
PER.view
;
;
;
;
;
;
;
;
You can find suggestions for such PRACTICE script files (*.cmm) on the CD-ROM with the path
/demo/m68hc12/compiler/*.cmm.
Refer to the MCS12 Debugger (debugger_hc12.pdf) and ICD Tutorial (icd_tutorial.pdf) or to the
PRACTICE Script Language Users Guide (practice_user.pdf) how to do this. You can also find some
information on basic actions with the debugger.
Please keep in mind that only the Processor Architecture Manual (the document you are reading in at the
moment) is CPU specific, while all other parts of the online help are generic for all CPUs. So if there are
questions related to the CPU the Processor Architecture Manual should be your first choice.
MCS12 Debugger
13
Restrictions
Reset Configuration
COP Function
The watchdog can only be used with the longest timer period. Refer
to SYStem.Option WATCHDOG.
On-chip Breakpoints on
derivatives with paging
TrBus commands do
not work
MCS12 Debugger
14
SYStem.BdmClock
Format:
AUTO
Clock source for BDM communication is the internal oscillator. The clock is
calculated and set automatically with help of a synchronization mechanism.
This selection can only work if the used processor contains a BDM
implementation which offers the SYNC command (not available on LA-7714
and LA-7717).
EXT
Clock source is the frequency from clock cable or from pin 10 of the 10 pin
connector. The Clock Cable is a flying lead connection.
EXT/2
Clock source is the frequency from clock cable or from pin 10 of the 10 pin
connector divided by two. The Clock Cable is a flying lead connection.
ECLK
Clock source for BDM communication is the ECLK (PE4) of the processor. The
ICD12 expects this signal on Pin 3 of the 6pin connector or Pin 8 of the 10 pin
connector. If ECLK is selected, the CLKSW bit of the BDM Status Register is
set.
INT
Clock source for BDM communication is the internal oscillator, which can be set
with the command SYStem.BdmClock <value>.
<value>
This command selects the source for the clock to be used for the communication between BDM an CPU.
Generally this frequency has to match the frequency of ECLK (unstretched). At derivatives without PLL this
frequency is half of the frequency applied to the CPUs EXTAL pin.
The internal oscillator cannot provide every frequency. The software uses the best setting for the selected
value and shows it in the SYStem window in the field BdmClock.
If your application requires to debug with active PLL please refer to the chapter Debugging with active
PLL.
MCS12 Debugger
15
SYStem.CPU
Format:
SYStem.CPU <type>
<type>:
SYStem.CpuAccess
Format:
Default: Denied.
Enable
Denied
Nonstop
Lock all features of the debugger, that affect the run-time behavior.
Nonstop reduces the functionality of the debugger to:
trace display
The debugger inhibits the following:
all features of the debugger that are intrusive (e.g. action Spot for breakpoints, performance analysis via StopAndGo mode, conditional breakpoints etc.)
MCS12 Debugger
16
SYStem.LOCK
Format:
Default: OFF.
If the system is locked, no access to the debug port will be performed by the debugger. While locked, the
debug connector of the debugger is tristated. The main intention of the lock command is to give debug
access to another tool.
SYStem.MemAccess
Format:
CPU
Denied
Default: Denied.
MCS12 Debugger
17
SYStem.Mode
Format:
SYStem.Mode <mode>
<mode>:
Attach
Down
Go
Up
Attach
This command works similar to Up command. The difference is, that the target
CPU is not reset. The BDM/JTAG/COP interface will be synchronized and the
CPU state will be read out. After this command the CPU is in the SYStem.Up
mode and can be stopped and debugged.
Down
Go
Resets the target with debug mode enabled and prepares the CPU for debug
mode entry. After this command the CPU is in the system.up mode and running.
Now, the processor can be stopped with the break command or until any break
condition occurs.
StandBy
Up
Resets the target and sets the CPU to debug mode. After execution of this
command the CPU is stopped and prepared for debugging. All register are set
to the default value.
MCS12 Debugger
18
SYStem.Option BASE
Format:
The SYStem.Option BASE defines the base address of the internal registers. On HC12 target systems the
user should always keep this address on the same value as the internal CPU register INITRG. (<address> is
a 16 bit value). On MC9S12 and S12X targets the value of INITRG can be read by the DBM interface and so
there is no action necessary.
The ICD needs to know, where the CPU s internal registers are assigned to. This information is used to
show the CPU s internal registers in the peripheral window, which can be opened by the PERipheral
command and to control some of the internal registers, when the EEPROM and FLASH programming
algorithms or the on-chip Hardware Breakpoints are in use.
Technical background: The registers of the CPU12 family members can be assigned to any 2-Kilobyte
boundary within the standard 64-Kilobyte address space. The location of the registers in the memory map of
M68HC12X depends from the register INITRG (Adr. 0x0011 after reset). The difficulty with this is that
INITRG is also mapped with the rest of the register block. If the INITRG is changed from 0x00 to 0x28 the
address of INITRG changes from 0x0011 to 0x2811. After this the SYStem.Option BASE is to be changed
from 0x0 to 0x2800:
After reset (at SYStem.Up the CPU receives a reset) the register block resides at
location 0x0000. If the SYStem.Option BASE holds a value other than 0x0, the
peripheral window for example shows nonsense.
SYStem.Option CLKSW
Format:
If the SYStem Option CLKSW is set to on, the debugger will set the CLKSW bit in the BDM Status register.
This configures the BDM interface of the CPU to work on bus frequency. If this frequency changes (for
example if an application switches to PLL clock) BDM communication will be lost if the user does not change
the contents of SYStem.Option BdmClock accordingly.
MCS12 Debugger
19
SYStem.Option DUALPORT
Format:
If the SYStem Option DUALPORT is active, the debugger does all memory accesses by hidden access. So
there will be no window freeze while executing user code. Disadvantage of doing so is, that the hidden
memory access may slow down the target application.
SYStem.Option GLOBAL
Format:
On S12X targets two different views on the memory map are possible. One is similar to the view used for the
MC9S12 with a 64k address room and memory expansion using page pointers in some ranges (Local
Memory Map), the other view has one linear address map (Global Memory Map).
If you use commands without memory class and the SYStem.Option Global is off, the TRACE32 software
will use the memory classes p: and d: which are intended to be used for logical addresses (Local Memory
Map).
If you use commands without memory class and the SYStem.Option Global is on, the TRACE32 software
will use the classes gp: and gd: which are intended to be used for global addresses (Global Memory Map).
SYStem.Option SOFTWORD
Format:
When a software breakpoint is set, the first byte of the original opcode is replaced with the command BGND
(Opcode 0x00). If the desired memory location is located in a range which can only be written by word
access, a special mechanism is required which does a read-modify-write operation. With the option you can
activate this mechanism:
OFF
ON
MCS12 Debugger
20
SYStem.Option VFP
Format:
OFF
ON
To program the FLASH EEPROM on some derivatives the necessary programming voltage can be applied
to the VFP pin. This option is activated and deactivated automatically if the debugger s capability to program
the FLASH EEPROM is used.
The line VFP on the BDM Connector is at 5 V if SYStem.Option VFP is off and at 12 V if SYStem.Option
VFP is on.
Further information can be found in the Chapters FLASH EEPROM Management.
MCS12 Debugger
21
SYStem.Option WATCHDOG
COP support
Only HC12
Format:
ON
The Watchdog (COP) is triggered by the emulator while the CPU is in break
mode. The debugger continuously generates write accesses to address 0x3F
altering the write data between 0xAA and 0x55.
This mechanism allows to debug an application which needs an active Watchdog (COP). To make the
mechanism work properly, the Watchdog Timer Rate must be switched to the slowest mode.
For details, please refer to Debugging with active Watchdog, page 30.
MCS12 Debugger
22
Hardware Breakpoints
Most derivatives of the CPU12 family contain a breakpoint module with two 16 bit registers. Refer to the
Technical Summary of your derivative to check if hardware breakpoints are available.
The built in breakpoints on some derivatives with paging react only on the
addresses within the 64K memory map. They do not take care of the paging
(e.g.: HC12DA/DG128). This is a problem of the CPU, which cannot be solved
by the debugger.
Example: If an on-chip breakpoint is set for example to address 68004 the CPU will break on fetching from
58004 (or from any other page).
The hardware breakpoints are controlled by registers located in the CPU s
register block. This block can be mapped with the INITRG register. To have the
hardware breakpoints working proper the user must take care that the debugger
knows the position of the registers all the time. This information is given by the
SYStem.Option BASE.
The on-chip hardware breakpoints can be used in the following modes:
Program Breakpoints
Generally the In Circuit Debugger for HC12 (ICD12) uses software breakpoints to realize program
breakpoints. Software breakpoint means that the code at the desired memory location is modified by the
debugger to make the CPU break when the program counter meets this address. After this the original
contents of this memory location is restored.
This mechanism does not work proper if a certain memory area can only be written by word accesses. In
this case use the SYStem.Option SOFTWORD.
This mechanism cannot work in Read Only Memory. To provide breakpoints in ROM areas the CPU s
hardware breakpoints can be used. The memory ranges, where hardware breakpoints should be used, have
to be defined with the command MAP.BOnchip.
MAP.BOnchip 0x1000--0x0ffff
With the command Break.List the actual breakpoint configuration can be checked.
MCS12 Debugger
23
Hardware Breakpoints
Read and Write Breakpoints can be set with the command Break.Set:
Break.Set 0x4738 /w
b.s 0x0b223 /r
Data Breakpoints
Data Breakpoints always use the CPU s Hardware Breakpoints regardless off the ranges defined with
MAP.BOnchip. To provide a Breakpoint on address match and data match both 16 bit registers are needed.
So there is only one breakpoint of this type available.
Data Breakpoints can be set with the TrOnchip menu. Use OnChip Trigger in the Trigger menu to open
this window. The address is specified with the following command:
Break.Set 0x4738 /a
MCS12 Debugger
24
Hardware Breakpoints
TrOnchip Commands
TrOnchip.view
Format:
TrOnchip.view
TrOnchip.CONVert
Format:
The hardware breakpoints of the HCS12 can only cover specific ranges. If a range cannot be programmed
into the breakpoint it will automatically be converted into a single address breakpoint when this option is
active. This is the default. Otherwise an error message is generated.
to.conv on
b.s 0x1000--0x17ff
b.s 0x1001--0x17ff
to.conv off
b.s 0x1000--0x17ff
b.s 0x1001--0x17ff
/w
/w
/w
/w
MCS12 Debugger
25
TrOnchip Commands
TrOnchip.Mode
Format:
TrOnchip.Mode <mode>
<mode>:
BreakAORB
BreakATHENB
TraceAORB
TraceATHENB
OFF
BreakAORB
BreakATHENB
TraceAORB
Recording cycles to the on-chip trace is stopped if one of the two comparators
A or B matches.
TraceATHENB
OFF
Some derivatives of 9S12 have an enhanced on-chip debug module which offers some complex trigger
features and a small on-chip trace. Please refer to your CPU s manual to check if your chip offers this
feature. These debug features are based on two address comparators which can be specified in the
following way:
Break.Set 0x8000 /Alpha /Read
TrOnchip.RESet
Format:
TrOnchip.RESet
MCS12 Debugger
26
TrOnchip Commands
TrOnchip.VarCONVert
Format:
The hardware breakpoints of the HCS12 can only cover specific ranges. If you want to set a marker or
breakpoint to a complex variable, the on-chip break resources of the HCS12 CPU may be not powerful
enough to cover the whole structure. If the option TrOnchip.VarCONVert is on the breakpoint will
automatically be converted into a single address breakpoint. This is the default setting. Otherwise an error
message is generated.
TrOnchip.XBreakt
Format:
The hardware breakpoints of the HCS12 can only cover specific ranges. If you want to set a marker or
breakpoint to a complex variable, the on-chip break resources of the HCS12 CPU may be not powerful
enough to cover the whole structure. If the option TrOnchip.VarCONVert is on the breakpoint will
automatically be converted into a single address breakpoint. This is the default setting. Otherwise an error
message is generated.
TrOnchip.RESERVE
Format:
tbd.
MCS12 Debugger
27
TrOnchip Commands
Memory Classes
Description
C:, P:, D:
A:
EEPROM:
EEPROM write
E:
AP:
C:, P: and D:
This storage classes operate on the same physically memory. They are only used to be compatible with
other emulation probes.
On S12X targets the numbers following the semicolon are taken as addresses in the local memory map.
G:, GC:, GP: and GD:
This storage classes are only available on S12X targets and operate on the same physically memory. They
are only used to be compatible with other emulation probes. The numbers following the semicolon are taken
as addresses in the global memory map.
EEPROM:
This storage class is used to program the internal EEPROM. On read cycles there is no difference to the
access mode with C: or D:. On write cycles the monitor program executes an EEPROM write protocol.
Data.Set EEPROM:0E00 12 34
D.s
EE:
0E00 12 34
MCS12 Debugger
28
Memory Classes
Mask
Action
MC68HC912A4
all Masks
MC68HC912D60
0F68K
1F68K
0K75F
MC68HC912D60
XF73K
Select any option than ECLK and take care that the
BDM interface is supplied with a frequency at half
value of EXTAL.
Warning: Due to a chip problem the CPU might stop
unexpected while debugging with active PLL.
MC68HC912DA128
0H55W
4H55W
Select any option than ECLK and take care that the
BDM interface is supplied with a frequency at half
value of EXTAL.
Warning: Due to a chip problem the CPU might stop
unexpected while debugging with active PLL.
MC68HC912DG128
0H55W
4H55W
Select any option than ECLK and take care that the
BDM interface is supplied with a frequency at half
value of EXTAL.
Warning: Due to a chip problem the CPU might stop
unexpected while debugging with active PLL.
MC68HC912DG128
0K50E
MCS12 Debugger
29
MCS12 Debugger
30
Take a copy of this file and modify the data.load command to the needs of your application.
If you do not use the Programming Voltage Generator of the ICD12 supply the CPU s VFP pin
with the necessary voltage (12 V FLASH types only).
To be able to debug within FLASH EEPROM areas the CPU s Hardware Breakpoints must be activated.
Refer to chapter Using Hardware Breakpoints.
Using FLASH.Erase <unit> with MC9S12DP family members will also erase the
three other units which belong to the same flash block.
The reason can be found in the different sizes of flash pages in the memory
(16 KByte) and block erasable hardware units (64 KByte).
To avoid this, you can use the command FLASH.Erase <range>.
MCS12 Debugger
31
EEPROM Management
The ICD12 supports easy writing to the internal EEPROM. It executes the necessary EEPROM program
sequence instead of the normal write operation if a write access to the EEPROM is indicated. There are two
ways to do this:
1.
;
;
;
;
;
setting bytes
short form
clear EEPROM
loading a binary file named
eepromdat.bin
MCS12 Debugger
32
EEPROM Management
2.
An example how to load an application to RAM, ROM, EEPROM for the HC12D60 in one step can be found
on the CD-ROM with the path
/demo/m68hc12/etc/flash/eeprom.cmm:
Writes to EEPROM can only be successful, when the according protection bits in
the register EEPROT (0x00F1, EEPROM Block Protect) are cleared.
MCS12 Debugger
33
EEPROM Management
Banked Applications
To support applications which use more than the 64K direct accessible memory paging is required. To
activate banking on targets switch the SYStem.Option PAGING to ON and set the SYStem.Option
ROMHM and the SYStem.Option TRANS according to the needs of your application.
On MC9S12 and S12X targets the SYStem.Option PAGING to ON
SYStem.Option PAGING
Format:
Banked applications
The SYStem.Option PAGING enables the support for banked applications on HC12 applications. It activates
a memory scheme similar to the one used for FIRE12. No MMU is required, all address based commands
(MAP.Bonchip, flash programming) are based on logical addresses.
Do not activate this option on S12X targets. On MC9S12 targets, you can use
this option for compatibility to old PRACTICE (*.cmm) files. Do not use it for new
designs.
MCS12 Debugger
34
Banked Applications
SYStem.Option ROMHM
Format:
The SYStem.Option ROMHM must be set if the bit ROMHM is set in the CPUs MISC register. In this case
page 6 of the FLASH EEPROM is visible from 0x4000--0x7fff.
SYStem.Option TRANS
Format:
Transparent mode
The SYStem.Option Trans has effect on logical addresses smaller then 64K. If it is on then accesses in this
area show the 64K of memory as seen by the CPU in the current paging configuration. This is the
transparent mode. If it is off then in banked areas page zero of this area is shown and the contents of the
according page register has no influence. It has no effect on the memory access of the CPU executing user
code.
Address
Access to
000000--00ffff
000000--00ffff
010000--0ffffff
pages 1..0ff
100000--0ffffffff
MCS12 Debugger
35
A logical address alone doesn't unique identify the physical address, as the address depends also on the
setup of the INITRG, WINDEF, MXAR, MISC, CSCTL0 and CSCTL1 registers. As a result, logical
addresses should only be used, if the MMU registers were already setup. Accessing internal resources
(RAM or peripherals) is handled like an access outside of the MMU window. The following schematic shows
these relations for some examples:
preset: CSCTL0=30,CSCTL1=10, WINDEF=40
logical address:
A21..A14
-->
logical address:
1
PAGE
logical address:
5
6
7
16 bit
logical CPU address
(Hex)
(Hex)
d
e
f
16 bit
current-mmu logical CPU address
-->
-->
(Hex)
5
6
7
16 bit
current-mmu logical CPU address
-->
-->
logical address:
5
6
7
16 bit
logical CPU address
-->
(Hex)
outside pages
exp. physical address:
0ffcdef
MCS12 Debugger
36
To activate the correct address translation for breakpoints, the MMU command must be activated. The
creation and activation of the MMU translation can be done automatically for some file formats during
download. The following script will prepare the 68HC12A4 for using the MMU without additional address
lines and with CSP0 line to select between RAM and ROM:
sys.res
y.res
mmu.res
map.res
sys.o csp0e on
sys.m ai
map.m fast
map.ram 0x0200--0x0ffff
map.ram 0x0bf0000++0x0ffff
map.opf 0x8000--0x0ffff
map.opf 0x0bf0000++0x0ffff
map.i
d.s
d.s
d.s
d.s
d.s
d.s
d.s
d.s
d.s
0x013 0x0e
0x16 0x0
0x3c 0x30
0x3d 0x10
0x12 0x11
0x3e 0x5
0x0f0 0x0fc
0x0f1 0x0
0x37 0x40
;
;
;
;
;
disable rom
disable the watchdog
CSCTL0
CSCTL1
set EEPROM to 0x1000
; enable P-Paging
When accessing memory with physical addressing (A:) by the CPU the address
for the CPU is transformed to a bank and offset using the MMU table. Physical
addressing of emulation memory is always possible without transformation
(EA:).
MCS12 Debugger
37
The logical address in these ranges is composed by the address within the 64k memory map (A15..A0) and
the byte above to select the desired page (A23..A16).
Examples:
Local Address
Global Address
Comment
P:0xFD8000
GP:0x7F4000
D:0x021000
GD:0x003000
D:0xFB0A23
GD:0x13EE23
P:0xFDC100
GP:0x7FC100
MCS12 Debugger
38
SYStem.
Options
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
0x0000-0x3FFF
MEMEXP off
MEMEXP on
0x4000-0x7FFF
MEMEXP off
MEMEXP on
ROMHM off
MEMEXP on
ROMHM on
MEMEXP off
MEMEXP on
ROMTST off
PIX
2
PIX
1
PIX
0
MEMEXP on
ROMTST on
PIX
2
PIX
1
MEMEXP off
MEMEXP on
ROMTST off
MEMEXP on
ROMTST on
PIX
2
PIX
1
0x8000-0xBFFF
0xC000-0xFFFF
The expanded physical address lines A13 to A0 contain the same level as the according pins of the CPU.
The table shows that the expanded physical address depends on the address, the page index and on the
bits ROMTST and ROMHM in the MISC register of the CPU. The emulator needs to know how these bits
are configured in the application. This information is given with the following SYStem.Options:
MCS12 Debugger
39
SYStem.Option MEMEXP
Format:
Memory expansion
The SYStem.Option MEMEXP enables the support for banked applications. If it is off, then the address
information on the CPUs pins is put on the emulators memory, break and trace system directly. If it is on the
expanded physical address is put on instead.
SYStem.Option ROMTST
Format:
The SYStem.Option ROMTST must be set if the bit ROMTST is set in the CPUs MISC register. In this case
the CPU is running in the Flash EEPROM TEST mode, where the FLASH EEPROM is in use as four 32K
windows located from 0x8000--0xffff. This option is only available if SYStem.Option MEMEXP is activated.
MCS12 Debugger
40
Logical Address
The logical address is a combination of an address in the 64K address area and the selected program or
data page. It contains 6 hexadecimal digits. The lower four digits contain the 64K address and the upper two
digits contain the number of the program or data page. The following table shows a few examples:
Address in 64K Address Range
Logical Address
0x8000
PPAGE = 0xF1
0xF18000
0x7124
DPAGE = 0x10
0x107124
0x400
EPAGE = 0x03
0x30400
Physical Address
The physical address is the address the CPU shows on its bus. It depends on the application which address
lines are used and which not. To make the ICD12 know if an Address or ChipSelect is used or not there is a
switch for each of the Addresses ADDR[21..16].
Format:
MCS12 Debugger
41
If a line of PortG is used as address line the according SYStem.Option must be set to ON if it is used as
general I/O it should be set to OFF.
Format:
If a line of PortF is used as chip select line the according SYStem.Option must be set to ON. If it is used as
general I/O is should be set to OFF.
A23
A22
A21
A20
CS3
CSD
CSD2
CSP1
CPU A21
CPU A20
CSP0
CPU A21
CPU A20
CPU A21
CPU A20
The expanded physical address range contains 23 address lines though the CPU has only 21 address lines.
The chip select lines affect A[23..20] of the expanded physical address. IF CSD, CSD2 or CS3 are active the
lines A21 and A20 contain levels which may be different to the levels on the CPUs pins. A[19..0] contain the
same levels as the CPUs pins (These statements and the table are only valid if the address lines A21 to A16
on the CPU are in use as address).
MCS12 Debugger
42
The following table gives an overview on the relation between logical address and expanded physical
address on the HC12A4:
Address in
64K Area
Active
Chip
Select
A23
A22
A21
A20
A19
A18
A17
A16
0x0000-0x03FF
EWDIR = 1
EWEN = 1
CS3
PEA1
7
PEA1
6
0x0400-0x07FF
EWDIR = 0
or
EWEN = 1
CS3
PEA1
7
PEA1
6
0x7000-0x7FFF
CSD
PDA1
9
PDA1
8
PDA1
7
PDA1
6
0x8000-0xBFFF
PWEN = 1
CSP1
PPA2
1
PPA2
0
PPA1
9
PPA1
8
PPA1
7
PPA1
6
0x8000-0xBFFF
PWEN = 1
CSP0
PPA2
1
PPA2
0
PPA1
9
PPA1
8
PPA1
7
PPA1
6
all other
cases
MCS12 Debugger
43
Address in
64K Area
Active
Chip
Select
A15
A14
A13
A12
A11
A10
A9--A0
0x0000-0x03FF
EWDIR = 1,
EWEN = 1
CS3
PEA15
PEA14
PEA13
PEA12
PEA11
PEA10
A9--A0
0x0400-0x07FF
EWDIR = 0
or
EWEN = 1
CS3
PEA15
PEA14
PEA13
PEA12
PEA11
PEA10
A9--A0
0x7000-0x7FFF
CSD
PDA15
PDA14
PDA13
PDA12
A11
A10
A9--A0
0x8000-0xBFFF
PWEN = 1
CSP1
PPA15
PPA14
A13
A12
A11
A10
A9--A0
0x8000-0xBFFF
PWEN = 1
CSP0
PPA15
PPA14
A13
A12
A11
A10
A9--A0
A15
A14
A13
A12
A11
A10
A9--A0
all other
cases
MCS12 Debugger
44
BDM Connector
BKGD
ECLK
/RESET
N/C
VCC
GND
MCS12 Debugger
45
BDM Connector
BKGD
GND
GND
/RESET
GND
VCC
The pins 3 and 5 are connected to GND on the BDMs connector. Be careful in using this connector with the
modified 6-pin Version from FREESCALE. You might cause short circuits to ECLK and VFP! If you want to
stay compatible add jumpers to your design to disconnect ECLK and VFP from the BDM connector.
ECLK
/RESET
VFP
VCC
GND
This Connector is supported if the last 4 digits of the Serial Number show a number higher than 3000. It is
recommended to add a capacitor (100 nF 1 uF between Pin5 (VFP) and GND) to the target, if the BDM
should supply the cpu with the necessary programming voltage for the FLASH EEPROM.
GND
N/C
/RESET
N/C
VCC
GND
VFP
EXTAL
Be careful with the pins 3 and 5. They are connected to GND on the BDMs female connector. The drawing
above shows how the male connector on the target should be connected.
Pin 10 (EXTAL) must not be connected, if there is a crystal used as clock source. It is recommended to add
a capacitor (100 nF 1 uF between Pin9 (VFP) and GND) to the target, if the BDM should supply the cpu
with the necessary programming voltage for the FLASH EEPROM.
MCS12 Debugger
46
BDM Connector
Support
MC68HC912D60
MC68HC912DG128
MC68HC912DT128
MC9S12A128
MC9S12A256
MC9S12A64
MC9S12B128
MC9S12B256
MC9S12B64
MC9S12C128
MC9S12C32
MC9S12C64
MC9S12C96
MC9S12D64
MC9S12DB128
MC9S12DG128
MC9S12DG256
MC9S12DJ128
MC9S12DJ256
MC9S12DJ64
MC9S12DP256
MC9S12DP512
MC9S12DT128
MC9S12DT256
MC9S12G128
MC9S12G240
MC9S12G32
MC9S12G64
MC9S12G96
MC9S12GC128
MC9S12GC16
MC9S12GC32
MC9S12GC64
MC9S12GC96
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
POWER
INTEGRATOR
ICD
TRACE
ICD
MONITOR
ICD
DEBUG
FIRE
ICE
CPU
Available Tools
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
MCS12 Debugger
47
Support
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
POWER
INTEGRATOR
ICD
TRACE
ICD
MONITOR
ICD
DEBUG
FIRE
ICE
CPU
MC9S12H256
MC9S12HA32
MC9S12HA48
MC9S12HA64
MC9S12HY32
MC9S12HY48
MC9S12HY64
MC9S12HZ128
MC9S12HZ256
MC9S12KG128
MC9S12KG256
MC9S12KG32
MC9S12KG64
MC9S12KT256
MC9S12NE64
MC9S12P128
MC9S12P32
MC9S12P64
MC9S12P96
MC9S12Q128
MC9S12Q32
MC9S12Q64
MC9S12Q96
MC9S12VR32
MC9S12VR64
MC9S12XB128
MC9S12XB256
MC9S12XD128
MC9S12XD256
MC9S12XD64
MC9S12XDG128
MC9S12XDP512
MC9S12XDQ256
MC9S12XDT256
MC9S12XDT384
MC9S12XDT512
MC9S12XEG128
MC9S12XEP100
MC9S12XEP768
MC9S12XEQ384
MC9S12XEQ512
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
MCS12 Debugger
48
Support
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
POWER
INTEGRATOR
ICD
TRACE
ICD
MONITOR
ICD
DEBUG
FIRE
ICE
CPU
MC9S12XET256
MC9S12XF128
MC9S12XF256
MC9S12XF384
MC9S12XF512
MC9S12XFE128
MC9S12XFR128
MC9S12XS128
MC9S12XS256
MC9S12XS64
MC9S12ZVB128
MC9S12ZVB23
MC9S12ZVB64
MC9S12ZVC128
MC9S12ZVC128A
MC9S12ZVC192
MC9S12ZVC192A
MC9S12ZVC64
MC9S12ZVC64A
MC9S12ZVC96
MC9S12ZVC96A
MC9S12ZVH128
MC9S12ZVH64
MC9S12ZVHY32
MC9S12ZVHY64
MC9S12ZVL16
MC9S12ZVL32
MC9S12ZVL8
MC9S12ZVLS16
MC9S12ZVLS32
MC9S12ZVM32
MC9S12ZVMC128
MC9S12ZVMC64
MC9S12ZVML128
MC9S12ZVML32
MC9S12ZVML64
MCS12KC128
MCS12KC64
MCS12KL128
MCS12KL64
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
MCS12 Debugger
49
Support
Compilers
Language
Compiler
Company
Option
C
C
C
C
CX68HC12
ICC6812
HICROSS-HC12
HICROSS
Cosmic Software
IAR Systems AB
NXP Semiconductors
NXP Semiconductors
COSMIC
UBROF
HICROSS
ELF/DWARF2
Comment
Company
Comment
Elektrobit tresos
Erika
osCAN
OSEK
OSEKturbo
ProOSEK
RTXC 3.2
uC/OS-II
via ORTI
via ORTI
via ORTI
via ORTI
via ORTI/former MetrowerksOSEK
via ORTI
2.0 to 2.92
Tool
Company
ALL
ALL
ALL
ADENEO
X-TOOLS / X32
CODEWRIGHT
ALL
CODE CONFIDENCE
TOOLS
CODE CONFIDENCE
TOOLS
EASYCODE
ECLIPSE
Adeneo Embedded
blue river software GmbH
Borland Software
Corporation
Code Confidence Ltd
ALL
ALL
ALL
Host
Windows
Windows
Windows
Linux
EASYCODE GmbH
Eclipse Foundation, Inc
Windows
Windows
MCS12 Debugger
50
Support
CPU
Tool
Company
Host
ALL
ALL
ALL
ALL
ALL
RHAPSODY IN MICROC
RHAPSODY IN C++
CHRONVIEW
LDRA TOOL SUITE
UML DEBUGGER
Windows
Windows
Windows
Windows
Windows
ALL
ALL
ATTOL TOOLS
VISUAL BASIC
INTERFACE
LABVIEW
IBM Corp.
IBM Corp.
Inchron GmbH
LDRA Technology, Inc.
LieberLieber Software
GmbH
MicroMax Inc.
Microsoft Corporation
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
CODE::BLOCKS
C++TEST
RAPITIME
DA-C
TRACEANALYZER
SIMULINK
TA INSPECTOR
UNDODB
VECTORCAST UNIT
TESTING
VECTORCAST CODE
COVERAGE
WINDOWS CE PLATF.
BUILDER
Windows
Windows
NATIONAL
INSTRUMENTS
Corporation
Open Source
Parasoft
Rapita Systems Ltd.
RistanCASE
Symtavision GmbH
The MathWorks Inc.
Timing Architects GmbH
Undo Software
Vector Software
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Linux
Windows
Vector Software
Windows
Windows
Windows
Products
Product Information
OrderNo Code
Text
LA-3748
BDM-MCS12Z
LA-7736
BDM-MCS12X
MCS12 Debugger
51
Products
Order Information
Order No.
Code
Text
LA-3748
LA-7736
BDM-MCS12Z
BDM-MCS12X
MCS12 Debugger
52
Products