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AT89S52 Microcontroller

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AT89S52 Microcontroller

Features:
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Compatible with MCS-51 Products


8K Bytes of flash memory
Endurance: 10,000 Write/Erase Cycles
4.0V to 5.5V Operating Range
256 x 8-bit Internal RAM
Watchdog Timer
Three 16-bit Timer/Counters
32 Programmable I/O Lines
Three 16-bit Timer/Counters

RST Pin:
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Reset input. A high on this pin for two machine cycles while the oscillator is
running resets the device.
This pin drives high for 98 oscillator periods after the Watchdog times out.
The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this
feature.

LCD Interfacing with 8051 Microcontroller

Category

Pin NO.

Power Pins

Contrast Pin

Pin Name Function


Ground Pin, connected to

VSS Ground
2

VDD or VCC

Voltage Pin +5V

Vo or VEE

Contrast Setting, connected


to VCC thorough a variable
resistor

Control Pins

RS

Register Select Pin:


RS=0 Command mode,
RS=1 Data mode
5

RW

:Read/ Write pin


,RW=0 Write mode
RW=1 Read mode
6

7-14

D0-D7

Enable, a high to low pulse


need to enable the LCD

Data Pins

Data Pins, Stores the Data


to be displayed on LCD or
the command instructions

Backlight Pins

15
16

LED+ or A To power the Backlight +5V


LED- or K

Backlight Ground

GSM Interfacing With AT89S52


RXD&TXD:
RXD: is the first pin in port 3(P3.0),Its used in serial
communications(as serial input port).
TX of GSM to RXD (PIN 10) of 8051
TXD: is the second pin in port 3(P3.1),Its used in serial
communications(as serial output port).
RX of GSM to TX (PIN 11) of 8051
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Interrupts:
Port 3(P3.2 & P3.3)
The interrupts refer to a notification, communicated to the
controller, by a hardware device or software.
on receipt of which controller momentarily stops and responds to
the interrupt.
Whenever an interrupt occurs the controller completes the
execution of the current instruction and starts the execution of
Interrupt Service Routine (ISR) or Interrupt Handler .
Each of these interrupt sources can be individually enabled or
disabled by setting or clearing a bit in Special Function Register IE. IE
also contains a global disable bit, EA, which disables all
interrup111111ts at once.
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