Tutor Marked Assignment #1: The Open University of Sri Lanka
Tutor Marked Assignment #1: The Open University of Sri Lanka
Tutor Marked Assignment #1: The Open University of Sri Lanka
Contacts:
S-mail: -
C. J. Basnayakege:
cjbas@ou.ac.lk
[Q2] Consider the following Boolean functions F1, F2, F3 and F4.
F1 (w, x, y, z) = (0, 1, 6),
F2 (w, x, y, z) = (a, b, c, d)
F4 (w, x, y, z) = (a, b, c, d)
Where a, b, c, and d, are the last four digits of your registration number.
(a) Draw the K-map for F1, F2, F3, F4 and find optimize expressions for F1, F2, F3, F4.
(b) Draw truth tables for the above expressions.
(c) Draw circuit diagrams to realize the same functions by using following PLDs. (Clearly show the
size of the each PLD)
(i) ROM
(ii) PLA
(iii) PAL
Figure 1
[Q5]
(a) Draw a truth table drive a Boolean function for 4 to 1 Multiplexer.
(b) Draw a circuit diagram using digital logic gates to perform the function of the 4 to 1
multiplexer.
(c) Write a HDL (VHDL) entity declaration for the 4 to 1 Multiplexer.
(d) Write behavioral program for the 4 to 1 Multiplexer using VHDL.
(e) Show the simulation results (waveforms) of the 4 to 1 Multiplexer using XILINX
software.
[Q6]
(a) Draw a truth table drive a Boolean function for 2 to 4 Decoder.
(b) Draw a circuit diagram using digital logic gates to perform the function of the 2 to 4
Decoder.
(c) Write a HDL (VHDL) entity declaration for the 2 to 4 Decoder.
(d) Write structural program for the 2 to 4 Decoder using VHDL.
(e) Show the simulation results (waveforms) of the 2 to 4 Decoder using XILINX software.
Submit your written assignment on or before 10th June 2016 and late submissions will not
be accepted!
Clearly show your assumptions if any, when you answering the questions.
Refer the learning resources (VHDL video lectures) given in the Moodle before answer
the questions.
Use Xilinx web pack software to write VHDL program. (You can get a copy of this
software from the laboratory)
[Q1]
(a) Write structural and behavioral VHDL program for T-Flip-Flop.
(b) Compare and contrast the each modelling methods above (a) with simulation
waveforms.
[Q2]
Analyze the FSM shown in the Figure A2.Q3.F1 where C is an inputs, and a and b are outputs.
(a) Derive Boolean functions for T0, T1, a and, b.
(b) Draw a state transition table for the FSM shown in Figure A2.Q3.F1.
(c) Draw a state diagram for the FSM shown in Figure A2.Q3.F1.
Figure A2.Q3.F1
[Q3]
(a) Draw an ASM chart for the digital circuit shown in Figure A2.Q3.F1 use state diagram
drawn in Q3 (c).
(b) Write a structural VHDL program for the FSM shown in the Figure A2.Q3.F1.
(c) Write test bench for the system and show the simulation results.
[Q5]
Refer the Quadrature Decoder Circuit diagram shown in the Figure A2.Q5.F1 to answer the
questions given in below.
(a) Derive Boolean functions for the Counter up and the Counter Down outputs.
(b) Draw a waveform to show the inputs and outputs of the circuit.
(c) Write a structural VHDL program using A2.Q1.(a). Clearly show the necessary hardware
changes of the given Quadrature Decoder Circuit.
Figure A2.Q5.F1
Submit your written assignment on or before 12th August 2016 and late submissions will
not be accepted!
Clearly show your assumptions if any, when you answering the questions.
Refer the learning resources (VHDL video lectures) given in the Moodle before answer
the questions.
Use Xilinx web pack software to write VHDL program. (You can get a copy of this
software from the laboratory)
Channels A/B
3 1 or 3 0
Recognizer
Datapath
Dout
(Control Unit)
Clock
Reset
Figure A3Q1: Digital Electronic Filter Unit
The DEFU consists of a Control unit and a Datapath on each channel of the optical encoder.
The Control unit is a recognizer that checks if the input from the optical encoder (Channel
A/B)) has short duration pulses and then controls the input data to flow through the datapath,
which consists of a 2: 1 multiplexer and a D flip-flop. If the input level has the same value (1
or 0) on at least three (3) consecutive clock cycles, then the input is not considered as a noise.
In this case the output of the recognizer (z) is active high, which then allows the input data
(Channels A/B) to flow through the datapath. The data value, thus becomes the new output
of the DEFU. Otherwise the input is considered as a noise and the datapath output (Dout) of
the DEFU remain the same.