R01ds0272eu0100 Synergy SSP PDF
R01ds0272eu0100 Synergy SSP PDF
R01ds0272eu0100 Synergy SSP PDF
The Renesas SynergyTM Software Package (SSP), the heart of the Renesas SynergyTM Platform, is a complete integrated
software package that was created using industry best practices and tested to commercial standards. It is composed of a realtime operating system (RTOS), middleware, communication stacks, function libraries, a rich application framework, and
low-level drivers.
Major components of the SSP include Express Logics X-Ware. X-Ware includes the premier ThreadX RTOS plus
middleware and stacks including NetX IPV4 TCP/IP stacks respectively, USBX USB Host/Device protocol stack,
FileX MS-DOS compatible file system, and GUIX graphics runtime library. These are bundled in the Renesas SSP with
additional libraries, a rich Application Framework, plus Hardware Abstraction Layer (HAL) drivers and Board Support
Packages (BSP) that are completely optimized for use with Renesas Synergy Microcontrollers (MCU) and developed
according to the IEC/ISO/IEEE-12207 Software Life Cycle Process standard while using the MISRA C:2012 coding
guidelines. The SSP is supported and maintained by Renesas on a continuous basis, and Renesas warrants the SSP to
operate as per the Performance section of this datasheet.
ThreadX RTOS
FileX
USBX
GUIX
Advanced
Scheduler
FAT12/16/32,
exFAT, SD,
microSD, CF, and
MemoryStick
Host Classes
FTP
SNTP
Audio
SPI
(Storage, CDC,
HID, Hub)
Canvas
TFTP
NAT
Console
IIC
Security &
Encryption
JPEG
UART
CMSIS DSP
Touch Panel
Thread
Monitor
Inter-process and
Inter-thread
Communication
Memory
Management
Message Queue
Application Framework
Drawing
Telnet
TCP
Host Stack
Screen
PPP
IPv4/v6
Complete Flash
Management
Host Controller
System
SMTP
UDP
Device Classes
Widget
POP3
ICMP
Messaging
ADC
Very Fast
Performance and
Low Footprint
Window
HTTP
IGMP
Power Profile
DNS
ARP
Cap. Touch
Sensing
DHCP
RARP
2D Drawing
Engine
External IRQ
Device Stack
Device Controller
SDHI
ADC12
QSPI
ADC14
USBHS
SPI
DAC12
USBFS
IIC
DMA Controller
CAN
SSI
UART
Code Flash
Data Transfer
Controller
Capacitive Touch
Sensing Unit
Graphics LCD
Controller
Segment LCD
Controller
Clock
Management
Asynchronous General
Purpose Timer
2D Drawing
Engine
Parallel Data
Capture Unit
JPEG Decoder
Security &
Encryption
RTC
General PWM
Timer 32-Bit
WDT
Safety
Figure 1
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1.1.
Key Features
ThreadX RTOS
NetX
Ethernet Driver
IPv4 compliant TCP/IP Protocol Stack
Integrated with ThreadX
Zero-copy API
RFC 791 Internet Protocol (IP)
RFC 826 Address Resolution Protocol (ARP)
RFC 903 Reverse Address Resolution Protocol
(RARP)
RFC 792 Internet Control Message Protocol (ICMP)
RFC 3376 Internet Group Management Protocol
(IGMP)
RFC 768 User Datagram Protocol (UDP)
RFC 793 Transmission Control Protocol (TCP)
NetX Application
Datasheet
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FileX
Memory support
Application Framework
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Datasheet
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1.2.
Datasheet
Introduction
This SSP datasheet includes functional descriptions and specifies performance data for the major software modules that are
included in the Synergy Software Package (SSP).
Information prior to section 13 of this datasheet provides a functional summary overview of each SSP software module,
including the memory footprint of each module for code (Flash memory) and data (SRAM). For full description and details
of each SSP software module, please refer to the SSP Users Manual.
Information in section 13 in this datasheet include SSP performance measurements of SSP software modules that may
include direct performance of individual software modules and in some cases the combined performance of several software
modules in higher system-level test scenarios.
Estimated Memory requirements in this document have been specified for the GCC compiler (-O2 optimizations) and the
IAR C/C++ compiler (-Om optimization) and specifies the following memory consumption for each module:
Flash Memory Usage = .text + .data
SRAM Memory Usage = .data + .bss +.noinit
All performance tests in this document are included in section SSP System Performance Warranted and Non-Warranted
and have been conducted and measured on specified Synergy hardware systems, typically a Synergy Development Kit. This
section also specifies the test environment for each performance test that includes:
SSP version.
Renesas Synergy hardware (Development Kit).
When the Synergy hardware is specific, it also identifies which Synergy MCU is used, the operating frequency,
and the MCU configuration settings.
Toolchain version (including complier optimization levels).
2. ThreadX RTOS
2.1.
Component Introduction
At the core of Renesas Synergy Software Package (SSP) is the industry-leading Express Logic, Inc. ThreadX RTOS. It is
optimized for MCUs in the Renesas Synergy family and tightly integrated with the SPP. ThreadX includes a completely
optimized, high-performance real-time kernel designed specifically for real-time embedded systems running on
microcontrollers, providing fast, sub-microsecond context switching and small, 2-KB memory footprint (Flash Memory).
The key features of ThreadX include:
ThreadX memory protection ensures that application threads and the ThreadX kernel are protected against accidental read
or write access from other threads. This prevents code or data corruption from latent application bugs, and eliminates one of
the most common causes of application crashes.
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Datasheet
Semaphores &
Mutex
Message
Queues/
Mailbox
Event Flags
Memory Management
Timer Support
Resource Management
ThreadX Kernel
Figure 2
2.2.
Table 1
ThreadX Features
1424
byte
event
1884
1560
0
0
initialize
isr
364
8
0
0
misra
mutex
0
2136
0
0
queue
semaphore
2516
1392
0
0
thread
time
4504
40
108
0
timer
trace
1888
112
0
0
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Flash (Bytes)
SRAM (Bytes)
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Table 2
Datasheet
Flash (Bytes)
SRAM (Bytes)
block
byte
1460
2008
0
0
event
initialize
1702
320
0
52
isr
misra
4
0
0
0
mutex
queue
2244
2708
0
0
semaphore
thread
1494
4536
0
284
time
timer
40
1808
0
1380
trace
112
Component Introduction
SSP includes a highly optimized embedded TCP/IP-IPv4-compliant protocol stack, NetX, for enabling IoT/M2M
communication protocols and embedded applications that require network connectivity. NetX is completely integrated with
ThreadX and is based on Express Logics unique Piconet architecture that provides a zero-copy API interface for
applications. Key features and capabilities provided with NetX include:
NetX provides complete set of protocol components that comprise the TCP/IP standard:
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Datasheet
SSP
NetX Application Bundle
NetX/NetX Duo
TCP
ICMPv4/v6
UDP
IPv4/v6
IPSec
ARP
RARP
IGMP
Network Driver
Synergy MCU
Ethernet
MAC Controller
Figure 3
3.2.
Table 3
Flash (Bytes)
SRAM (Bytes)
arp
icmp
4532
1692
0
0
igmp
ip
1948
9912
0
0
packet
ram
2504
796
0
104
rarp
system
992
192
0
96
tcp
trace
16216
0
0
0
udp
5128
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Table 4
3.3.
Datasheet
Flash (Bytes)
SRAM (Bytes)
arp
icmp
4820
1702
0
0
igmp
ip
1924
9760
0
8
packet
ram
2520
852
8
104
rarp
system
1078
156
0
120
tcp
trace
16394
0
12
0
udp
5080
Table 5
Table 6
Flash (Bytes)
3.1K
SRAM (Bytes)
0
Flash (Bytes)
3.6K
SRAM (Bytes)
1
Component Introduction
Included with SSP are additional application layer protocols that are frequently used in networking devices:
These implementations of core networking protocols are thread-safe, compliant with respective RFCs/standards, and have
been optimized for memory footprint and CPU utilization. Networking applications are individually selectable for each
project providing flexibility to system designer to incorporate only applications necessary for the target application.
4.2.
Estimated memory requirements for this section will be provided in future updates of this document
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Component Introduction
SSP provides a high performance and low memory footprint MS-DOS compatible file system, FileX, for embedded
applications that require file operations. FileX is implemented as a C library. Only the features used by the application are
brought into the final image. The footprint of FileX is as small as 6 KB. Additionally, FileX has minimal function call
layering, an internal logical sector cache, contiguous cluster allocation, and consecutive cluster reading and writing. All of
these attributes make FileX extremely fast and efficient.
FileX provides many advanced features for embedded file applications, including the following key capabilities:
X-Ware
SSP
Flash
SDHI
Flash
SPI
Flash
BSP
SD/
MMC
HAL
S/IF
USBX
ThreadX
Application
Framework
FileX
MCU
USB
MS
Figure 4
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SPI
Flash
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5.2.
Datasheet
Table 7
Table 8
Flash (Bytes)
SRAM (Bytes)
directory
file
13040
8652
0
0
media
ram
7765
192
13
0
system
unicode
1020
3520
96
0
utility
4336
Flash (Bytes)
SRAM (Bytes)
directory
file
12308
8460
0
0
media
ram
7078
168
16
0
system
unicode
730
3344
168
768
utility
4296
Component Introduction
GUIX is SSPs high-performance graphical user interface framework. GUIX includes a full-featured runtime UI library and
a matching GUI design application for desktop PCs named GUIX Studio. GUIX is fully integrated within SSP and like
ThreadX, GUIX is designed to have a small footprint and high performance, making it ideal for todays deeply embedded
applications. GUIX uses the same high-performance design and coding methods as ThreadX and has been designed to meet
the growing need for dynamic user interfaces with limited hardware resources. GUIX has minimal function call layering,
and optimized clipping, drawing, and event handling making it extremely fast and responsive.
Key features and capabilities of GUIX include:
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Endian neutral
SSP
ThreadX
Application
Framework
GUIX
Runtime
HAL
BSP
Synergy MCU
Graphics LCD
Controller
Figure 5
6.2.
2D Drawing
Engine
JPEG
Codec
Estimated memory requirements for this section will be provided in future updates of this document.
7. USBX
7.1.
Component Introduction
SSP includes an embedded USB stack fully integrated with ThreadX and supporting high-performance USB Host and
Device modes for embedded applications. USBX requires a small memory footprint and is modular, allowing for only the
features used by the application to be included into the final image. This minimizes the footprint of the USB stack being
built for the target device. USB Low Speed, Full Speed and High Speed modes are supported.
Supports most of the standard USB class drivers including Mass Storage, Printer, HID, Audio, Hub, RNDIS, Data
Pump, PTP, and PictBridge.
Integrated with Express Logic components (FileX and NetX).
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Datasheet
Storage
Class
CDC
Class
Custom
Class
VBUS
Manager
Keyboard
HUB Class
Isoch
Classes
Mouse
Async
Classes
Remote
Control
HID Class
OHCI
EHCI
Software
Schedule
Controller
Driver
Figure 6
7.2.
Estimated memory requirements for this section will be provided in future updates of this document.
7.3.
Table 9
Table 10
USB Driver
Full Speed Device
4.3K
Flash (Bytes)
0
SRAM (Bytes)
8.6K
Flash (Bytes)
4.5K
8.5K
SRAM (Bytes)
0
0
8. Application Framework
8.1.
Introduction
The Application Framework is a key subsystem in Renesas SSP, which, along with the Hardware Abstraction Layer (HAL),
abstracts hardware peripherals. It provides a uniform and consistent programming interface with standardized APIs for
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system designers and developers. This allows them to access and use most major features in SSP without having to worry
about the complexity of the underlying low-level device interfaces in the platform.
The Application Framework is tightly integrated with ThreadX, provides thread-safe APIs for accessing shared resources,
and manages access conflicts by providing mutual exclusion and synchronization services amongst application tasks.
The Application Framework in SSP links the RTOS with HAL and provides high-level, C-callable interfaces for commonly
used platform system services.
Application Program
SSP
Application Framework
ThreadX
X-Ware
Audio
SPI
Console
IIC
JPEG
UART
Touch Panel
Thread Monitor
External IRQ
Power Profile
Messaging
Others
HAL
BSP
Synergy
MCU
Figure 7
8.2.
8.2.1.
Component Introduction
Application Framework
The Audio Playback Framework in SSP provides standardized, C-callable, high-level APIs for playback of audio content.
The framework handles the integration and synchronization of multiple HAL peripherals like timers, DMA, and DAC to
facilitate audio playback. The Audio Playback Framework APIs are thread-safe and abstract underlying MCU hardware
features; for example, timers, Sampling Rate Convertor, and DACs.
The Audio Playback Framework supports 16-bit mono uncompressed (linear) PCM samples and lets developers plug in
custom components. The framework supports single instantiation.
Playback control features provided with Audio Framework:
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DAC
PWM
Plays long buffers by splitting the data into smaller manageable blocks.
Repeat/loop playback of supplied audio data until ThreadX timeout.
Can request next data using callback after last buffer playback begins.
Scaling to playback signed 16-bit PCM samples through unsigned 12-bit DAC.
Basic mixing of multiple streams.
The Audio Playback Framework does not support reading files in a file system and decoding audio. These
functions are performed outside of the Audio Playback Framework.
Figure 8
8.2.2.
Table 11
Table 12
Flash (Bytes)
2,952
SRAM (Bytes)
0
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Flash (Bytes)
3,560
SRAM (Bytes)
0
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8.3.
8.3.1.
Component Introduction
Datasheet
The Inter-Thread Messaging Framework in SSP provides easy to use high-level APIs for inter-thread communication and
synchronization. The Inter-Thread Messaging Framework implements a lightweight, event-driven message-passing
mechanism that lets applications pass messages between two or more threads. The Messaging Framework makes it simple
to use the ThreadX message queue mechanism for passing messages, and provides additional features beyond the basic
RTOS message queue services:
Message management: The framework supports buffer control blocks to manage each message.
Message buffering: The framework manages buffer allocation and release for messages.
Message publish/subscribe mechanism: The framework allows multiple threads to listen to an Event Class without
the message producer thread knowing who is subscribing to a message for the Event Class and the subscribers not
knowing who produces the message.
Handshaking: The framework provides an option for handshakes between a message producer and a consumer
thread by invoking a specified callback function of the producer thread from a consumer thread.
Message formatting: The framework provides a predefined common message header. It also provides some typical
payload structure templates as examples.
Message Priority: The framework provides the capability to post high priority messages that receive precedence for
delivery.
Messaging Framework provides user applications a buffer that is allocated in the memory pool to store the
message header and payload. The framework also has the provision for user applications to release the buffer.
Framework supports unicast and multicast messaging.
Sender Thread
Messaging
Framework
Listener Thread
Event
Handler Start
SF_MESSAGE_
BufferAcquire ()
Start
Allocate
Event process
Write message
SF_MESSAGE_Pend ()
Message
SF_MESSAGE_Post ()
Release
Memory pool
Event
Handler End
Figure 9
8.3.2.
SF_MESSAGE_
BufferRelease ()
Table 13
Table 14
Flash (Bytes)
2,052
SRAM (Bytes)
0
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Flash (Bytes)
2,118
SRAM (Bytes)
0
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8.4.
I2C Framework
8.4.1.
Component Introduction
Datasheet
The I2C Framework in SSP abstracts the software interface for the I2C driver. It provides a simple high-level, C-callable
API for seamless and thread-safe access of the I2C interface from multiple application threads.
The I2C framework is ThreadX aware and handles the integration and synchronization of multiple I2C peripherals on an
I2C bus. The I2C Framework enables the user to create one or more I2C buses and connect multiple I2C peripherals to the
buses. The I2C Framework makes use of low-level I2C driver modules and SCI common driver modules to communicate
with I2C peripherals. The I2C Framework provides Mutual Exclusion and Synchronization services to manage
simultaneous multiple access requests. Internally the framework uses ThreadX objects like mutex bus locking/unlocking for
blocking, and synchronization techniques like event flags for completion of transactions. The I2C Framework supports
handling of restart condition and provides common interface for both SCI I2C and RI2C peripherals.
The framework blocks access to a specific channel while in use with mutex.
The framework driver handles callback to notify application of events.
The framework maintains a counter that tracks how many devices are currently on the bus.
The framework also provides timeout parameter to the write/read API functions.
The framework provides lock options to lock a bus for a device and provides an unlock API to unlock the locked
bus by device.
The framework supports all channels available with the device.
Framework supports opening of multiple devices on the same bus.
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Figure 10
8.4.2.
I2C Framework
Table 15
Table 16
Flash (Bytes)
1456
SRAM (Bytes)
0
8.5.
8.5.1.
Component Introduction
Flash (Bytes)
1,430
SRAM (Bytes)
0
The Touch Panel I2C Framework in SSP provides a high-level, C-callable programmable interface for interfacing with
external touch screen controllers. Internally the Touch Panel I2C Framework uses I2C to interface with the touch screen
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controller. The Touch Panel I2C Framework API provides seamless and thread-safe software interface for touch screens
from SSP.
The Touch Panel I2C Framework is commonly used for capturing touch input for GUI applications. It produces touch data
messages with position information (X and Y coordinates) and event type information which are posted to event queue(s)
using the Messaging Framework. The touch panel framework also creates a thread to poll the touch driver and post touch
data to the Messaging Framework.
The Touch Panel I2C Framework sequentially processes UI input events in the order they are received from I2C interface.
The framework supports receiving input events from multiple touch screens. Internally the framework uses mutex for
synchronization between multiple application threads. The framework uses external interrupt interface for synchronization.
The API has provisions for:
The touch panel framework supports touch controllers available on all Renesas Product Examples and Development Kits.
Figure 11
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8.5.2.
Datasheet
Table 17
Table 18
Flash (Bytes)
1,472
SRAM (Bytes)
0
8.6.
8.6.1.
Component Introduction
Flash (Bytes)
1,508
SRAM (Bytes)
0
The External Interrupt Framework provides a high-level, C-callable interface for scheduling event driven execution of
threads in the SSP. When the IRQ is raised by applications, it causes a thread to pend until an external pin interrupt is
received or a timeout occurs. Common use cases include waiting for a switch press from a user or waiting for a signal from
an external hardware device.
The interrupt framework is ThreadX aware and provides generic external interrupt handling capability. The APIs for
Interrupt Framework are thread-safe and internally the framework uses ThreadX objects like mutex for blocking, and
synchronization techniques like semaphores for interrupt handling by multiple application threads. Some of the key features
include:
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Figure 12
8.6.2.
Datasheet
Table 19
Table 20
Flash (Bytes)
744
SRAM (Bytes)
0
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Flash (Bytes)
704
SRAM (Bytes)
0
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8.7.
8.7.1.
Component Introduction
Datasheet
The JPEG Decode Framework module in SSP abstracts the on-chip JPEG codec and provides a simple high-level, Ccallable API for seamless and device independent integration of JPEG decoder application threads. The JPEG codec allows
for high-speed compression of raw images and decoding of JPEG images. The codec conforms to the JPEG baseline
compression and decompression standard, JPEG Part 2, ISO-IEC 10918-2.
The JPEG Decode Framework is ThreadX aware and provides primary JPEG decoder functionality. The JPEG APIs are
thread-safe and internally the framework uses ThreadX objects like mutex for blocking, and synchronization techniques,
like event flags for completion of JPEG data decompression by multiple application threads.
The JPEG Decode Framework APIs handles the decode tasks by taking application specific encoded data in an input buffer
and allocating an output buffer pointer to store the decoded image frame. Alternatively, the API can handle streaming
encoded data into JPEG decoder module. This feature allows an application to read encoded JPEG image from a file or
from network without buffering the entire image. The framework allows the application to specify the number of image
lines to decode so that the application can decode the image on the fly without buffering the entire frame.
Figure 13
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8.7.2.
Datasheet
Table 21
Flash (Bytes)
sf_jpeg_decode
Table 22
1,852
SRAM (Bytes)
4
Flash (Bytes)
sf_jpeg_decode
8.8.
UART Framework
8.8.1.
Component Introduction
1,784
SRAM (Bytes)
4
The UART Framework module in SSP abstracts the serial communication peripherals and provides a simple high-level, Ccallable API for seamless and device independent integration of serial ports from multiple application threads.
The UART Framework is ThreadX aware and provides generic full-duplex UART communication. Internally the
framework uses ThreadX objects like mutex for blocking and synchronization techniques like event flags to manage
simultaneous multiple access requests. The SSP UART driver designates the HAL driver to call the frameworks UART
callback function and handles events generated by UART hardware. The UART Framework module can be implemented by
several hardware peripherals at the HAL layer. The connection to the HAL layer is established by passing in a driver
structure at initialization time. Both SCI and USBX UART modules are supported in this version.
The UART Framework in Synergy implements the Synergy Communications Interface.
Application Program
X-WareTM
SCI
HAL
S/IF
USBXTM
ThreadX
UART
Application
Framework
UART port
BSP
Synergy
MCU
USB
(CDC)
Figure 14
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SCI
UART Framework
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8.8.2.
Datasheet
Table 23
Table 24
Flash (Bytes)
1,584
SRAM (Bytes)
0
8.9.
Console Framework
8.9.1.
Component Introduction
Flash (Bytes)
1,522
SRAM (Bytes)
0
The Console Framework module in SSP provides easy to use high-level, C-callable APIs for implementing a CLI
(command line interface). The framework defines command names and callback function for each command, and uses the
Communications Framework to receive commands and input strings, parse the content, and invoke the relevant command
handler routine.
The Console Framework can handle inputs from other serial interfaces as well; for example, USB CDC. The parser within
the framework provides support for nested menus, standard commands to return to the root menu (~) and to back out to
the previous menu (..). It also supports arrow key input, backspace, and delete keys.
The Console Framework support hierarchical menus, and parsing of input command based on predefined command list.
The framework provides notification when a command is selected, and provides an error code if the command isn't found.
The Console Framework supports:
Application Program
Start
SF_CONSOLE_Open ()
Start
SF_CONSOLE_Prompt ()
Read UART
Parse
command
Figure 15
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8.9.2.
Datasheet
Table 25
Table 26
Flash (Bytes)
2,372
8.10.
SRAM (Bytes)
Flash (Bytes)
2,280
SRAM (Bytes)
8
Figure 16
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Figure 17
Datasheet
Table 28
SRAM (Bytes)
0
8.11.
Flash (Bytes)
1,408
Flash (Bytes)
1,628
SRAM (Bytes)
0
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The Periodic Sampling ADC Framework provides C-callable, generic and thread-safe APIs for applications to sample data
over available ADC channels. Key features of the Framework include:
Figure 18
Table 30
Flash (Bytes)
1,716
8.12.
SRAM (Bytes)
0
Flash (Bytes)
1,664
SRAM (Bytes)
0
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functionality and can be used for short tones or chirps. For advanced audio applications, this framework is typically used
with the Audio Playback Framework.
Audio Playback HW DAC Framework features include:
Figure 19
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Flash (Bytes)
1,340
SRAM (Bytes)
28
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Table 32
Datasheet
8.13.
Flash (Bytes)
1,358
SRAM (Bytes)
28
Figure 20
Memory Usage for Capacitive Touch Sensing Unit Framework GCC Compiler
Framework Component
sf_touch_ctsu
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Flash (Bytes)
1,204
SRAM (Bytes)
1,024
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Table 34
Datasheet
Memory Usage for Capacitive Touch Sensing Unit Framework IAR Compiler
Framework Component
sf_touch_ctsu
8.14.
Flash (Bytes)
1,204
SRAM (Bytes)
1,296
Pressed State
Released State
Long Touch
Short Touch
Multi Touch
Button is stuck in pressed state
The framework is designed to be used together with configuration data generated by the Workbench 6 tool.
8.14.2. Estimated Memory Requirements
Table 35
Memory Usage for Capacitive Touch Sensing Unit Button Framework GCC Compiler
Framework Component
sf_touch_ctsu_button
Table 36
Flash (Bytes)
1,964
Memory Usage for Capacitive Touch Sensing Unit Button Framework IAR Compiler
Framework Component
sf_touch_ctsu_button
8.15.
SRAM (Bytes)
0
Flash (Bytes)
1,872
SRAM (Bytes)
120
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The SPI Framework is ThreadX aware and provides common framework for SPI interfaces. The Framework integrates with
existing SPI driver interfaces like SCI SPI and supports:
Figure 21
Memory Usage for Serial Peripheral Interface (SPI) Framework GCC Compiler
Framework Component
sf_spi
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Flash (Bytes)
1,880
SRAM (Bytes)
0
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Table 38
Datasheet
Memory Usage for Serial Peripheral Interface (SPI) Framework IAR Compiler
Framework Component
sf_spi
8.16.
Flash (Bytes)
1,926
SRAM (Bytes)
0
Run
RTC
External Interrupt
These modes determine which clocks and peripherals are disabled during Software Standby mode, as well as what the
output pin states are prior to and after exiting Software Standby mode.
The Interface uses the RTC, LPM, IOPORT and CGC peripherals on the Synergy microcontroller hardware and provides an
easy-to-use software interface to access the low power operating modes.
Supported Power Profiles:
Software Standby
Wakeup
Figure 22
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Table 40
Flash (Bytes)
1,068
8.17.
SRAM (Bytes)
Flash (Bytes)
1,008
SRAM (Bytes)
8
Figure 23
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Table 42
Flash (Bytes)
384
8.18.
SRAM (Bytes)
Flash (Bytes)
378
SRAM (Bytes)
0
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Figure 24
Datasheet
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Flash (Bytes)
9,452
SRAM (Bytes)
129
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Table 44
8.19.
Datasheet
Flash (Bytes)
10,102
SRAM (Bytes)
129
Table 46
Flash (Bytes)
2,232
32
8.20.
SRAM (Bytes)
Flash (Bytes)
2,232
SRAM (Bytes)
32
Open
Close
Read
Write
The USBX Communication Framework (CDC ACM) in Synergy implements the Synergy Communications Interface.
8.20.2. Estimated Memory Requirements
Table 47
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Flash (Bytes)
1,456
SRAM (Bytes)
284
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Table 48
Datasheet
8.21.
Flash (Bytes)
1,406
SRAM (Bytes)
282
Figure 25
Memory Usage for Block Media Interface for SD Multi Media Card GCC Compiler
Framework Component
sf_block_media_sdmmc
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Flash (Bytes)
180
SRAM (Bytes)
0
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Table 50
Datasheet
Memory Usage for Block Media Interface for SD Multi Media Card IAR Compiler
Framework Component
sf_block_media_sdmmc
Flash (Bytes)
236
SRAM (Bytes)
0
9. Crypto Library
9.1.
Component Introduction
The Secure Crypto Engine (SCE7) is the security and encryption block on Synergy S7G2 group MCUs. It features many
security features and National Institute of Standards and Technology (NIST)-compliant, primitive cryptographic algorithms
for various applications. These features and algorithms can perform authentication and secure communication between the
microcontroller and an external communication device or network, and can encrypt confidential and sensitive data and
program for storage in the microcontroller. The security and encryption block also features high-throughput and low-power
hardware accelerators to enable authentication and to meet secure communication requirements for various applications.
The SSP Cryptographic library provides a simple C-callable API interface for these functions and capabilities available in
the SCE7.
The SCE7 incorporates a high-throughput, 128-bit true random number generator (TRNG) that can generate random
numbers with high entropy for use as seeds to deterministic random number generators (such as NIST SP800-90A DRBG).
The TRNG generates cryptographically secure random numbers. Synergy MCUs also support several cryptographic hashing
functions SHA1/SHA224/SHA256/MD5/GHASH.
Additionally, SCE7 supports several NIST-compliant symmetric encryption algorithms like Advanced Encryption Standard
(AES 128/192/256-bit), Data Encryption Standard (3DES/DES) and Alleged RC4 (ARC4). These encryption algorithms,
along with private keys, are used for secure data exchange and to securely store data and program in the MCU.
SCE7 also supports several NIST-compliant asymmetric algorithms for data exchange. The data transmitter and receiver
uses shared keys.
The SSP Cryptographic library provides high-level, C-callable APIs for the following security functions in SCE7:
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9.2.
Public keys are exchanged between the transmitter and receiver, then the public and private keys are used to
compute the shared secret between transmitter and receiver.
Rivest, Shamir, and Adleman (RSA).
Used for public-key cryptography.
Generates two keys: public and private.
Transmitter encrypts using the public key.
Receiver decrypts using the private key.
Supports up to 2048-bit key length.
Used in digital verification for authentication, signature generation and verification, encryption/decryption for key
exchange and wrapping, and other security functions.
Estimated Memory Requirements
Estimated memory requirements for this section will be provided in future updates of this document.
10.
10.1.
Component Introduction
The ARM Cortex Microcontroller Software Interface Standard DSP hardware block (CMSIS-DSP) in the Cortex-M4
processor core based Synergy family of MCUs provides a suite of common signal processing functions.
The CMSIS-DSP library is a hardware abstraction layer included in SSP for Synergy MCUs that includes a collection of
over 60 completely optimized signal processing functions commonly used in digital signal control applications. The library
supports key arithmetic formats such as fixed-point/fractional (Q7, Q15, Q31) and single precision floating-point (32-bit)
arithmetic for DSP operations. The combination of high-efficiency signal processing functions in SSP with the low-power,
low-cost, and high-performance benefits of Synergy MCUs having underlying SIMD architecture and FPU provide a
compelling solution for diverse applications in IoT/M2M markets.
The CMSIS-DSP library covers operations under the following major categories:
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11.
11.1.
Introduction
HAL modules in SSP are device-independent drivers for peripherals available on Synergy MCUs. The HAL modules
provide abstracted and well-defined interfaces. The underlying functionality of these interfaces can be implemented by
multiple device drivers. The HAL drivers use system services like timers and provide generic, high-level, C-callable
interfaces which are functional but device independent. The Application Framework in SSP uses the HAL drivers for
interfacing with the low-level device-specific drivers. HAL drivers can also be used by application programs to interface
directly with the respective peripheral, bypassing the SSP Framework. However these modules are RTOS independent (not
ThreadX aware) and are not thread-safe.
Figure 26
11.2.
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Table 52
Flash (Bytes)
2,228
11.3.
SRAM (Bytes)
24
Flash (Bytes)
2,412
SRAM (Bytes)
24
Configure any of the available clocks (HOCO, MOCO, LOCO, Main Clock, PLL, Sub-Oscillator) as the system
clock source.
Configure the internal clocks (ICLK, PCLK etc.).
Switch the clocks on and off.
Configure the output clocks.
Set up the Oscillation Stop Detection feature.
Table 54
Flash (Bytes)
1,796
SRAM (Bytes)
0
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Flash (Bytes)
1,784
SRAM (Bytes)
0
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11.4.
Datasheet
Memory Usage for Capacitive Touch Sensing Unit (CTSU) GCC Compiler
HAL Component
r_ctsu
Table 56
Flash (Bytes)
13,021
Memory Usage for Capacitive Touch Sensing Unit (CTSU) IAR Compiler
HAL Component
r_ctsu
11.5.
SRAM (Bytes)
920
Flash (Bytes)
13,137
SRAM (Bytes)
1,214
Set left-justified or right-justified 12-bit value format for 16-bit input data registers.
Enable or disable output amplifiers.
Select external or internal reference voltages.
Operate in synchronous anti-interference mode with Analog-to-Digital Converter (ADC) Module.
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Table 58
Flash (Bytes)
864
11.6.
SRAM (Bytes)
1
Flash (Bytes)
900
SRAM (Bytes)
1
Interrupt the CPU, which will call a user callback function if provided.
Toggle a port pin.
Transfer data using DMAC/DTC when configured with Transfer Interface.
Start another peripheral when configured with ELC Interface.
The AGT supports runtime calculation of the period in standard units such as milliseconds and Hertz to ensure the period
calculation is accurate and based on the current clock speed. The AGT can be used to wake the MCU from certain low
power modes.
The AGT timer functions are used by the Timer Interface in SSP to provide timer services.
11.6.2. Estimated Memory Requirements
Table 59
Memory Usage for Asynchronous General Purpose Timer (AGT) GCC Compiler
HAL Component
r_agt
Table 60
Flash (Bytes)
2,920
Memory Usage for Asynchronous General Purpose Timer (AGT) IAR Compiler
HAL Component
r_agt
11.7.
SRAM (Bytes)
24
Flash (Bytes)
3,026
SRAM (Bytes)
32
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Datasheet
polynomials. CRC calculations can be performed by sending data to the block using the CPU or by snooping on read or
write activity on one of 10 SCI channels.
The CRC module supports the following functions:
Memory Usage for Cyclic Redundancy Check calculator (CRC) GCC Compiler
HAL Component
r_crc
Table 62
Flash (Bytes)
784
Memory Usage for Cyclic Redundancy Check calculator (CRC) IAR Compiler
HAL Component
r_crc
11.8.
SRAM (Bytes)
0
Flash (Bytes)
900
SRAM (Bytes)
0
The measurement clock is monitored using a reference clock. The reference clock may be an external clock, supplied on the
CACREF input pin, or one of the following internal clocks:
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A completed measurement may be identified by making API calls to poll the driver, or by establishing callback functions
which are capable of triggering on any of the following conditions:
Memory Usage for Clock Frequency Accuracy Measurement (CAC) GCC Compiler
HAL Component
r_cac
Table 64
Flash (Bytes)
916
Memory Usage for Clock Frequency Accuracy Measurement (CAC) IAR Compiler
HAL Component
r_cac
11.9.
SRAM (Bytes)
9
Flash (Bytes)
876
SRAM (Bytes)
15
I2C (RIIC)
Transfer aborted
Transmit complete
Receive complete
The callback structure provides the number of bytes that were sent or received.
SCI_I2C and I2C HAL drivers implements the I2C interface in SSP.
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Table 66
Flash (Bytes)
7,980
SRAM (Bytes)
136
Flash (Bytes)
4,012
SRAM (Bytes)
136
Component Introduction
The SPI HAL driver supports the SPI interface in Synergy MCUs and implements the SPI protocol.
The SPI driver configures SPI peripheral in master mode and supports the following functions:
The Interface also provides support for callbacks. The callback functions are called with the following events:
Transfer aborted
Transfer complete
Mode fault
Error events
The SPI HAL Interface is implemented by the SCI_SPI and SPI HAL driver modules in SSP.
11.10.2.
Table 67
Table 68
Flash (Bytes)
2,968
SRAM (Bytes)
84
Flash (Bytes)
4,046
SRAM (Bytes)
84
Component Introduction
The QSPI HAL driver supports the Quad-SPI (QSPI) peripheral in Synergy microcontroller which functions as a memory
controller for connecting a serial ROM (non-volatile memory such as a serial flash memory, serial EEPROM, or serial
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Datasheet
FeRAM) with an SPI-compatible interface. The driver is used for erasing and programming the contents of a QSPI flash
device connected to the microcontroller over the Quad SPI interface.
The QSPI driver supports the following functions:
Table 70
Flash (Bytes)
796
SRAM (Bytes)
0
Flash (Bytes)
848
SRAM (Bytes)
0
Component Introduction
The RTC HAL driver controls the Realtime Clock. The driver supports the RTC peripheral available on the Synergy
microcontroller hardware.
The RTC driver supports the following functions of the Real-Time Clock:
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Flash (Bytes)
2,592
SRAM (Bytes)
20
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Table 72
Datasheet
Flash (Bytes)
2,754
SRAM (Bytes)
20
Component Introduction
The Segment LCD HAL driver controls the Segment LCD Display. The driver supports the SLCD peripheral available on
the Synergy microcontroller hardware.
The driver uses the Segment LCD controller (SLCDC) to display data on a Segment LCD. The driver initializes the LCD
for displaying data and configures the drive voltage generator, the display waveform, number of time slices, and the bias
methods to drive the LCD. This module provides functions to display data to a specified set of segments, to update existing
segment data, to enable and disable display, to set the display area, and to adjust the contrast.
Module supports selecting the following features:
Internal voltage boosting for the LCD driver voltage generator: Select the capacitor split method or the external
resistance division.
Display bias: Select the 1/2 bias method, 1/3 bias method, or 1/4 bias method.
Time slice of the display: Select static, 2-time slice, 3-time slice, 4-time slice, or 8-time slice.
Display waveform: Select waveform A or waveform B.
Display data area: Select A-pattern, B-pattern, or blinking. You can switch the display data area.
Use the RTC periodic interrupt (PRD) to generate a blinking display with A-pattern and B-pattern.
Adjust the reference voltage, which is generated when operating the voltage boost circuit, in 16 steps (contrast
adjustment).
Table 74
Flash (Bytes)
1,568
SRAM (Bytes)
0
Flash (Bytes)
1,852
SRAM (Bytes)
0
Component Introduction
The SCI_UART driver enables serial communication using the UART protocol over the SCI peripheral in Synergy MCUs.
The UART Interface supports the generic UART protocol.
The UART Interface used with the SCI peripheral in UART mode (UART on SCI) supports multiple features in addition to
the standard UART protocol.
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11.14.2.
Table 75
Memory Usage for Serial Communication Interface UART (SCI_UART) GCC Compiler
HAL Component
r_sci_uart
Table 76
Flash (Bytes)
5,324
SRAM (Bytes)
0
Memory Usage for Serial Communication Interface UART (SCI_UART) IAR Compiler
HAL Component
r_sci_uart
Flash (Bytes)
6,212
SRAM (Bytes)
40
Component Introduction
The SCI_I2C driver supports the SCI peripheral in Synergy MCUs. The driver supports the I2C protocol for communicating
in master mode and provides following capabilities:
Transfer aborted
Transmit complete
Receive complete
The callback structure provides the number of bytes that were sent or received.
The I2C on SCI driver implements the I2C interface in SSP.
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11.15.2.
Table 77
Table 78
Datasheet
Flash (Bytes)
3,960
SRAM (Bytes)
400
Memory Usage for Serial Communication Interface I2C (SCI_I2C) IAR Compiler
HAL Component
r_sci_i2c
Flash (Bytes)
4,164
SRAM (Bytes)
400
Component Introduction
SCI_SPI HAL driver module supports SPI serial communication using the microcontroller's SCI peripheral. The module
implements the SPI Interface.
The SPI Interface configures SPI communication in master mode. The Interface allows:
The Interface also provides support for callbacks. The callback functions are called with the following events:
Transfer aborted
Transfer complete
Mode fault
Error events
Selecting a SPI Module
SCI_SPI module support 8-bit data transfer and GPIO pins configured as chip selects.
The SPI HAL Interface is implemented by the SCI_SPI HAL driver modules in SSP.
11.16.2.
Table 79
Table 80
Flash (Bytes)
3,188
SRAM (Bytes)
360
Memory Usage for Serial Communication Interface SPI (SCI_SPI) IAR Compiler
HAL Component
r_sci_spi
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Flash (Bytes)
3,176
SRAM (Bytes)
360
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Datasheet
Component Introduction
The on-chip JPEG engine performs high-speed image data compression and decoding of JPEG image data. The JPEG
Decoder conforms to the JPEG baseline decompression standard, JPEG Part 2, ISO-IEC10918-2. The JPEG Codec HAL
driver module supports the JPEG hardware peripheral in Synergy MCUs.
Specifications and Features:
Supports JPEG decompression for applications to convert a JPEG image into bitmap data suitable for display
frame buffer.
Supports polling mode that allows an application to wait for JPEG decoder to complete.
Supports Interrupt mode with user-supplied callback functions.
Provides interfaces for applications to specify parameters such as:
o Horizontal and vertical subsample values
o Horizontal stride
o Decoded pixel format
o Input and output data format
o Color space.
Obtains the size of image prior to the decoding step.
Supports putting encoded data in an input buffer and an output buffer to store the decoded image frame.
Streams encoded data input into JPEG Decoder module. This feature allows an application to read encoded JPEG
image from a file or from network while decoding it, without the necessity to buffer the entire image.
Supports streaming coded data into JPEG Decoder module. This feature allows an application to read coded JPEG
image from a file or from network without buffering the entire image
Configures the number of image lines to decode. This feature enables the application to process the decoded image
on the fly without buffering the entire frame.
Supports the input decoded formats YCbCr444, YCbCr422, YCbCr420, YCbCr411.
Supports the output decoded formats ARGB8888 and RGB565.
Returns error when JPEG images size height and width do not match the specified input values.
The JPEG Codec HAL module implements the JPEG Decode interface in SSP.
11.17.2.
Table 81
Table 82
Flash (Bytes)
2,616
SRAM (Bytes)
4
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Flash (Bytes)
3,184
SRAM (Bytes)
4
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Component Introduction
The S7 Series microcontrollers support up to 4 MB high-speed Code flash for user applications and 64 KB of highspeed Data Flash for storing data. The Flash Memory-High Performance HAL driver supports the High
Performance Flash memory block on S7 Series MCU and enables an application to read, write and erase both the
Data and ROM flash areas that reside within the MCU. The amount of flash memory available varies across MCU
parts, but the functionality available through the module is listed below: Blocking erasing, reading, writing and
blank checking of ROM flash.
Both blocking and non-blocking erasing, reading, writing and blank checking of Data and Code flash.
Callback functions for completion of non-blocking data flash operations.
Access window (write protection) for Rom flash allowing only specified areas of code flash to be erased or written.
Swap area for boot block swapping which allows safe re-writing of the startup program without first erasing it.
The driver makes the process of programming and erasing on-chip flash areas easy. The module can be used to perform
blocking erase and program operations for both code and data flash, with BGO operation available for data flash operations
only. When a code flash operation is on-going, you cannot access that code flash area. If theres and attempt to access the
code flash area while a code Flash operation is in progress, the flash control unit will transition into an error state.
The FLASH_HP Modules implements the Flash Interface in SSP.
11.18.2.
Table 83
Table 84
Flash (Bytes)
2,872
SRAM (Bytes)
34
Flash (Bytes)
2,700
SRAM (Bytes)
102
Component Introduction
The S3 Series microcontrollers support up to 1 MB low-power Code flash memory for user applications and 16 KB of low
power Data Flash memory for storing data. The Flash Memory-Low Power HAL driver supports the Low Power Flash
memory block on S3A7 MCU and enables an application to read, write and erase both the Data and ROM flash areas that
reside within the MCU. The amount of flash memory available varies across MCU parts, but the functionality available
through the module is listed below:
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Swap area for boot block swapping which allows safe re-writing of the startup program without first erasing it.
The driver makes the process of programming and erasing on-chip flash areas easy. The module can be used to perform
blocking erase and program operations for both code and data flash, with BGO operation available for data flash operations
only. When a code flash operation is on-going, you cannot access that code flash area. If theres an attempt to access the
code flash area while a code Flash operation is in progress, the flash control unit will transition into an error state.
The FFLASH_LP Modules implements the Flash Interface in SSP.
11.19.2.
Table 85
Table 86
Flash (Bytes)
2,892
SRAM (Bytes)
34
Flash (Bytes)
2,804
SRAM (Bytes)
102
Component Introduction
Data Transfer Controller (DTC) driver supports the DTC peripheral that is used to transfer data between memory and
peripherals, or between two peripherals without CPU intervention (background data transfer).The DTC driver moves data
from a user specified source to a user specified destination when an interrupt or event occurs. The DTC module uses a RAM
based vector table, with slots for every interrupt in the system. When the DTC transfer completes, the activation source
interrupt is called. The activation source interrupt must be enabled to use the DTC. The activation source interrupt is
generally muted by the DTC until the transfer completes, unless TRANSFER_IRQ_EACH is specified in the configuration.
The DTC also allows chained transfers, meaning that more than one transfer can occur after a single activation source
interrupt. This feature is supported by the driver but must be configured outside the e2 studio IDE.
The Data Transfer Controller allows data transfers to occur in place of or in addition to any interrupt. It does not support
data transfers using software start.
The DTC module supports following transfer modes:
Normal Mode - A single transfer is triggered each time an activation source event occurs. A single transfer is 1 byte, 2
bytes, or 4 bytes depending on the selected settings. Total length (size) of data to be transferred is configurable.
Repeat Mode In addition to the length (size) of data block that needs to be transferred, Repeat Mode provides additional
provision for specifying number of time transfer should be repeated with the same length of data. In this mode if the repeat
area is set to source, the same source location is used for each transfer iteration. Alternatively, if the repeat area is set to
destination, the same destination location is used for each transfer iteration.
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Block Mode The block mode transfer operates similar to the Repeat mode, but is triggered by a source event, the entire
transfer length is transferred each time an activation source event occurs. For example, if a transfer is configured in block
mode with timer as the activation source, a 2 byte size, and a 12 byte length, 24 bytes are transferred each time the
activation source event occurs. Similar to Block Mode if the repeat area is set to source, the source register is reloaded with
its initial value when the transfer restarts.
Address Mode The Address mode transfer operates similar to the Normal Mode, but after each transfer the source pointer
and destination pointer is incremented by the length of transfer
Chained Transfer Mode - Chained transfers are only supported by DTC, in this mode successive transfers are linked by
creating an array of Transfer Info structures and setting the mode TRANSFER_CHAIN_MODE_ENABLED for all
transfers except the last transfer. The module is configured to point to the base of the first structure in the array to indicate
the first transfer source and destination location.
The HAL Transfer Interface is a generic interface for Transfer applications and is implemented by two data transfer
modules in SSP, DMAC and DTC.
11.20.2.
Table 87
Table 88
Flash (Bytes)
1,920
SRAM (Bytes)
1,041
Flash (Bytes)
1,922
SRAM (Bytes)
103
Component Introduction
The Data Operation Circuit (DOC) peripheral performs 16-bit addition, subtraction, and comparison without CPU
intervention, The DOC driver provided with SSP supports the DOC peripheral available on the Synergy microcontroller
hardware and controls the peripheral according to user configuration.
The driver can detect the following events:
When the configured event occurs and a callback is available (with interrupts enabled), the driver invokes the callback with
the supplied arguments, which in-turn indicates the occurrence of the event to application. If interrupts are not enabled, the
API supports checking the DOC status to poll the status of the comparison, addition or subtraction operation.
The DOC driver implements the DOC interface in SSP.
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11.21.2.
Table 89
Table 90
Datasheet
Flash (Bytes)
804
SRAM (Bytes)
4
Flash (Bytes)
868
SRAM (Bytes)
4
Component Introduction
The Direct Memory Access Controller (DMAC) driver supports the DMAC peripheral that is used to transfer data between
memory and peripherals, or between two peripherals without CPU intervention (background data transfer).The DMAC
driver moves data from a user specified source to a user specified destination when an interrupt or event occurs. The DMAC
module uses DMAC peripheral registers, so the number of transfers in the system is limited to number of available DMAC
channels on the device. The activation source does not have to be enabled to use the DMAC. When the DMAC transfer
completes, a DMAC interrupt is called. If the activation source interrupt is enabled, it fires at the same time the transfer is
triggered. If the DMAC interrupt is enabled, it fires after all transfers are complete. The DMAC does not support chained
transfers.
The DMAC module supports following transfer modes:
Normal Mode A single transfer is triggered each time an activation source event occurs. A single transfer is 1 byte, 2
bytes, or 4 bytes depending on the selected settings. Total length (size) of data to be transferred is configurable.
Repeat Mode In addition to the length (size) of data block that needs to be transferred, Repeat Mode provides additional
provision for specifying number of time transfer should be repeated with the same length of data. In this mode if the repeat
area is set to source, the same source location is used for each transfer iteration. Alternatively, if the repeat area is set to
destination, the same destination location is used for each transfer iteration.
Block Mode The block mode transfer operates similar to the Repeat mode, but is triggered by a source event, the entire
transfer length is transferred each time an activation source event occurs. For example, if a transfer is configured in block
mode with timer as the activation source, a 2 byte size, and a 12 byte length, 24 bytes are transferred each time the
activation source event occurs. Similar to Block Mode if the repeat area is set to source, the source register is reloaded with
its initial value when the transfer restarts.
Address Mode The Address mode transfer operates similar to the Normal Mode, but after each transfer the source pointer
and destination pointer is incremented by the length of transfer
The HAL Transfer Interface is a generic interface for Transfer applications and is implemented by two data transfer
modules in SSP, DMAC and DTC.
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11.22.2.
Table 91
Table 92
Datasheet
Flash (Bytes)
2,080
SRAM (Bytes)
64
Memory Usage for Direct Memory Access Controller (DMAC) IAR Compiler
HAL Component
r_dmac
Flash (Bytes)
2,532
SRAM (Bytes)
72
Component Introduction
The External IRQ HAL driver supports the Interrupt Controller Unit (ICU) on Synergy Microcontroller hardware for
external pin interrupts used by push-button devices and other applications using external interrupts.
The external IRQ HAL driver supports external inputs, for example input from pins or capacitive touch buttons. When an
input trigger is detected, a user provided callback function will be called. The driver configures the external IRQ inputs in
the ICU (Interrupt Controller Unit). The driver supports the following features of the external IRQ inputs:
The ICU driver module implements the External IRQ interface in SSP.
11.23.2.
Table 93
Table 94
Flash (Bytes)
1,740
SRAM (Bytes)
64
Flash (Bytes)
1,744
SRAM (Bytes)
80
Component Introduction
The Event Link Controller (ELC) peripheral enables direct interaction between different peripherals without CPU
intervention.
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Datasheet
11.24.2.
Table 95
Table 96
Flash (Bytes)
328
SRAM (Bytes)
0
Flash (Bytes)
372
SRAM (Bytes)
0
Component Introduction
The GPT driver module supports the GPT peripheral in Synergy Microcontroller. The driver configures a 32 bit timer to a
user specified period, when the period elapses, the GPT module can call a user callback and toggle a port pin.
The GPT driver provides standard timer functionality including periodic mode, one-shot mode, and free-running timer
mode. After each timer cycle (overflow or underflow), an interrupt can be triggered. The driver configures a timer to a user
specified period. When the period elapses, any of the following user configured events can be triggered:
Interrupt the CPU, which will call a user callback function if provided.
Toggle a port pin.
Transfer data using DMAC/DTC if configured with Transfer Interface.
Start another peripheral if configured with ELC Interface.
The driver also provides an output compare extension to output the timer signal to the GTIOC pin.
The HAL Timer Interface in SSP is a generic interface for timer applications and is implemented by the AGT and GPT
driver modules.
11.25.2.
Table 97
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Flash (Bytes)
4,288
SRAM (Bytes)
60
Page 56 of 71
Table 98
Datasheet
Flash (Bytes)
3,808
SRAM (Bytes)
60
Component Introduction
The IOPORT module supports the I/O Ports peripheral available on the Synergy microcontroller hardware. The driver
configures one or more I/O pins. The direction of the pin or pins can be configured along with following options:
Pull-up
NMOS/PMOS
Drive strength
Event edge trigger (falling, rising or both)
Whether the pin is to be used as an IRQ pin
Whether the pin is to be used as an analog pin
Whether the pin is to be used as a peripheral pin and which peripheral
The IOPORT HAL drivers provide ability to access the I/O Ports of a device at both bit and port level. Port and pin
direction can be changed. In addition a number of configuration APIs are provided to change the functionality of individual
pins.
The IOPRT driver implements the IOPORT interface in SSP.
11.26.2.
Table 99
Table 100
Flash (Bytes)
976
SRAM (Bytes)
0
Memory Usage for General Purpose I/O Port (GPIO / IOPORT) IAR Compiler
HAL Component
r_ioport
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Flash (Bytes)
904
SRAM (Bytes)
0
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Datasheet
Component Introduction
The Keyboard interrupt interface supports the Key Interrupt Function peripheral available on the Synergy microcontroller
hardware. The Key input driver can be used for one to eight channels or in a matrix format. This module implements the
Key Matrix Interface in SSP
The Key Interrupt (KINT) deriver detects rising or falling edges on any of the KINT channels. When such an event is
detected on any of the configured pins, the module generates an interrupt. The interrupt then calls the user callback that
specifies the channel(s) on which the edge was detected via a bitmask. Even though detection of an edge on any one channel
generates the interrupt, the callback returns a bit-mask of all the pins that were triggered at that time if any other pins also
detected an edge. Thus an interrupt is not necessarily generated for edge detection on each pin if an edge was detected on
another pin also before the callback was called. If a new edge is detected after the callback was called, then the interrupt is
triggered again resulting in a new callback.
This module can be used to implement a matrix keypad with edges on any two channels indicating the actual key that was
pressed. Alternatively, the module can be used as a single input to detect an edge on an input pin.
11.27.2.
Table 101
Table 102
Flash (Bytes)
808
SRAM (Bytes)
9
Flash (Bytes)
836
SRAM (Bytes)
9
Component Introduction
The microcontroller features a highly configurable, integrated Graphics LCD Controller that can be used to drive a variety
of color TFT LCD screens. The GLCD controller reads image data from system memory, displays it on an LCD panel
connected to GLCD interface, and frees up the CPU for other processing tasks.
GLCD controller provides standard display functionality:
Supports LCD panels with RGB interface (up to 24bits) and sync signals (HSYNC, VSYNC and Data Enable)
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Datasheet
Supports various color formats for input graphics planes (RGB888, ARGB888, RGB565, ARGB1555,
ARGB4444, CLUT8, CLUT4, CLUT1).
Supports CLUT (Color Look-Up Table) usage for input graphics planes with 512 words (32bits/word).
Supports various color formats for output (RGB888, RGB666, RGB565, Serial RGB).
Can input two graphics planes on top of the background plane and blend them on the screen.
Generates a dot clock to the panel. The clock source is selectable from internal or external (LCD_EXTCLK).
Supports brightness adjustment, contrast adjustment and gamma correction.
Supports GLCDC interrupts to handle frame buffer switching or underflow detection.
The figure below shows an overview of the graphics data flow using the GLCDC driver module. The driver supports
reading graphics frame image data from memory (up to two frames) and blending those images on top of the monochrome
background screen. The driver supports CLUT memory and specifies the graphic frame format for the CLUT.
Figure 27
The GLCD Controller drivers implements the HAL Display interface in SSP.
11.28.2.
Table 103
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Flash (Bytes)
6,756
SRAM (Bytes)
16
Page 59 of 71
Table 104
Datasheet
Flash (Bytes)
8,612
SRAM (Bytes)
68
Component Introduction
This driver configures the Watchdog Timer (WDT) Interface and when the WDT underflows or is refreshed outside of the
permitted refresh window, one of the following events will occur based on the configuration:
WDT driver provides the ability to configure the operation of WDT (when used in register start mode), refresh the
watchdog, read the timer value and read and clear status flags.
The WDT and IWDT drivers implements the WDT HAL interface in SSP.
11.29.2.
Table 105
Table 106
Flash (Bytes)
928
SRAM (Bytes)
4
Flash (Bytes)
954
SRAM (Bytes)
4
Component Introduction
The Independent Watchdog Timer (IWDT) peripheral in Synergy MCUs consists of a 14-bit down counter that must be
serviced periodically to prevent counter underflow. The IWDT driver supports the IWDT peripheral on Synergy MCUs.
This driver configures the Watchdog Timer (WDT) Interface and when the WDT underflows or is refreshed outside of the
permitted refresh window, one of the following events will occur based on the configuration:
The IWDT driver provides ability to refresh the independent watchdog, read the timer value and read and clear status flags.
When used in NMI output mode the callback to be called by the NMI ISR can be registered.
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Datasheet
The WDT and IWDT drivers implements the WDT HAL interface in SSP.
11.30.2.
Table 107
Table 108
Flash (Bytes)
828
SRAM (Bytes)
4
Flash (Bytes)
858
SRAM (Bytes)
4
Component Introduction
The HAL driver supports ADC12 and ADC14 peripherals available on the Synergy microcontroller hardware. .
The ADC driver controls the ADC on a Synergy microcontroller according to the user configuration, it can access both
ADC units on the MCU and configure them for single scan, continuous scan, and group scan modes. When a scan is
complete and a callback is available (with interrupts enabled), the driver invokes the callback function.
If interrupts are not enabled, the driver checks the scan status to poll if the scan is complete and provides a function to read
the converted ADC result.
Group Mode Operation
The driver also supports group mode operation. In this mode, channels can be assigned to one of two groups: group-A or
group-B. A trigger is assigned for each group to start the scan. In group mode, only hardware triggers can be used, as
opposed to normal mode, where software triggers or an external trigger can be used.
The ADC Driver implements the ADC HAL interface in SSP.
11.31.2.
Table 109
Table 110
Flash (Bytes)
1,464
SRAM (Bytes)
40
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Flash (Bytes)
1,648
SRAM (Bytes)
40
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Datasheet
Component Introduction
The FMI driver reads the FMIFRT (Factory MCU Information Flash Root Table) on a Synergy microcontroller for the
address of the start of the table in flash. It sets the callers pointer the Product Information record from the table.
The FMI Driver implements the FMI HAL interface in SSP.
11.32.2.
Table 111
Table 112
Flash (Bytes)
124
SRAM (Bytes)
0
Flash (Bytes)
136
SRAM (Bytes)
0
Component Introduction
The LPM driver provides access and configuration of MCU operating power control modes using the Low Power Mode
hardware peripheral.
The LPM driver supports following operating power control modes:
Low-voltage mode
Low-speed mode
Middle-speed mode
High-speed mode
Subosc-speed mode
The LPM driver supports reducing power consumption when in deep stand-by mode via internal power supply control and
resetting the states of IO ports. The LPM driver supports disabling and enabling of the MCUs other hardware peripherals.
Additional functionality supported: Enable/disable of hardware peripheral for additional power reduction.
The LPM Driver implements the LPM HAL interface in SSP.
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11.33.2.
Datasheet
Table 113
Table 114
Flash (Bytes)
1,908
SRAM (Bytes)
0
Flash (Bytes)
2,124
12.
12.1.
Component Introduction
SRAM (Bytes)
0
The SSP includes BSPs for DK-S7G2, PE-HMI1, and SK-S7G2 kits. The BSP is responsible for getting the MCU from
reset to the users application (the main() function). Before reaching the users application, the BSP sets up the stacks,
heap, clocks, interrupts, and C runtime environment. The BSP also configures and sets up the port I/O pins and performs
any board specific initializations. The key features of the BSPs provided with SSP are:
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Datasheet
Application Program
SSP
X-WareTM
GUIXTM
USBXTM
ThreadX
NetXTM
Application
Framework
Shared I/F
FileX
HAL
BSP
Synergy
MCU
Figure 28
Table 116
Flash (Bytes)
18,344
16,608
5,397
5,369
13.
SRAM (Bytes)
Flash (Bytes)
SRAM (Bytes)
DK-S7G2
12,644
5,402
DK-S3A7
11,530
5,394
This section describes the SSP system performance measurements and the environment in which they were measured for
the SSP running on specified Synergy hardware, typically a Synergy Development Kit. There are two portions to some of
the stated benchmarking and performance test results sections as they appear in this performance section 13 of the
datasheet:
Measured results that are warranted by Renesas under the SSP warranty policy.
Measured results that are NOT covered by the SSP warranty policy but are typical characterizations. These results
are useful indicators of performance to help you plan your system design.
Individual benchmarking and performance characterization depends on the version and configuration of the test
environment. For each individual test, the test environment is be specified.
For SSP warranty claims, the claimant must identify which particular test (by particular section number within this
performance portion of the datasheet). The claimant must reproduce the suspected errant SSP behavior while operating
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Page 64 of 71
Datasheet
within the specified environment that is described for the particular test. If the errant SSP behavior is reproduced within the
specified environment, a SSP warranty claim can be made on the Synergy Gallery at https://synergygallery.renesas.com by
selecting the Support tab and then selecting Warranty Information area. The claimant must hold a valid SSP
Development/Production license to make a SSP warranty claim. The claimant will receive an acknowledgment of receipt of
the warranty claim from Renesas within 24 hours, and the claimant will be notified of the resolution status of the warranty
claim within seven days of receipt.
NOTE: Renesas warranties these performance characteristics to within 5% of reported scores or specifications.
The specified test environment, per individual test, will include but may be not limited to these elements:
SSP release version upon which the test software was built
Test software release version
Compiler version and optimization settings used to build the test software
Development environment tool version and configuration used to build the test software
Hardware kit type typically a Synergy Development Kit with exact kit version number, on which the test
software was executed
o The kit, by default, also indicates the Synergy MCU type with CPU core type and clock speed
Other configurations that may vary from one test to another depending on the test
o Memory access such as
CPU instruction execution out of on-chip Flash memory or SRAM, external XIP Flash memory
or SDRAM, etc.
Source of data - USB-flash drive for file system, SD card, QSPI Flash memory, etc.
o Execution with or without ThreadX RTOS (RTOS or bare metal)
Individual benchmark and performance tests selected for SSP datasheet testing include those that represent real-world use
cases for embedded MCU applications as well as industry-standard benchmark tests. Some of the benchmark test software
used in SSP testing is widely available as open source, or it is easily licensed.
13.1.
Test software
e2 studio ISDE tool
Compiler
GCC Compiler
Compiler Optimization
GCC_4.8_2014q3
-O3
GCC Assembler
GCC Linker
GCC_4.8_2014q3
CC_4.8_2014q3
Linker (GCC)
C_4.8_2014q3
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Datasheet
CoreMark Score
377
675
1.58
2.81
EEMBC CoreMark
Renesas Synegy DK-S7G2
377
GCC -03
IAR High, Speed, no size
constraints
675
0
Figure 29
R01DS0272EU0100 Rev.1.00
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200
400
600
800
EEMBC CoreMark
Page 66 of 71
13.2.
Datasheet
Test software
e2 studio ISDE tool
Compiler
GCC_4.8_2014q3
Optimize more (-O2)
GCC Assembler
GCC Linker
GCC_4.8_2014q3
CC_4.8_2014q3
Linker (GCC)
C_4.8_2014q3
Message Processing: This test consists of a thread sending a 16 byte message to a queue and retrieving the same 16 byte
message from the queue. After the send/receive sequence is complete, the thread increments its run counter.
NOTE: In Thread-Metric, the significant figure of merit is clock cycles. Smaller is better.
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Table 120
Datasheet
GCC O2
IAR OH Balanced
Message Processing
177
IAR OH Balanced
263
238
GCC O2
0
100
200
293
300
Figure 30
IAR OH Balanced
11,463
GCC O2
0
5,000
10,000
15,000
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13.3.
Datasheet
Test software
e2 studio ISDE tool
jPerf 2.0.2.7
V4.2.0.012
Compiler
Compiler Optimization Setting
GCC_4.8_2014q3
Optimize more (-O2)
GCC Assembler
GCC Linker
GCC_4.8_2014q3
CC_4.8_2014q3
Table 122
Table 123
GCC O2
83
28
94
91
GCC O2
33
NOTE: In the two tables above, larger is faster for throughput tests, smaller is better for ping test.
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13.4.
Datasheet
Test software
e2 studio ISDE tool
Compiler
GCC_4.8_2014q3
Optimize more (-O2)
GCC Assembler
GCC Linker
GCC_4.8_2014q3
CC_4.8_2014q3
GCC O2
44 seconds
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Revision History
Rev.
0.8
0.81
Date
October
2015
October
2015
0.90
December
2015
1.00
January
2016
Datasheet
Page
Description
Summary
All
64-66
All
All
All
R01DS0272EU0100 Rev.1.00
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Page 71 of 71
Datasheet
Notice
1.
2.
3.
4.
5.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the
operation of semiconductor products and application examples. You are fully responsible for the incorporation of
these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no
responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or
information.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas
Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability
whatsoever for any damages incurred by you resulting from errors in or omissions from the information included
herein.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual
property rights of third parties by or arising from the use of Renesas Electronics products or technical information
described in this document. No license, express, implied or otherwise, is granted hereby under any patents,
copyrights or other intellectual property rights of Renesas Electronics or others.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in
whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties
arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.
Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High
Quality". The recommended applications for each Renesas Electronics product depends on the product's quality
grade, as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment;
audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment;
and industrial robots etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; antidisaster systems; anti-crime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a
direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or
may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check
the quality grade of each Renesas Electronics product before using it in a particular application. You may not use
any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be
in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas
Electronics product for which the product is not intended by Renesas Electronics.
6.
7.
8.
9.
You should use the Renesas Electronics products described in this document within the range specified by Renesas
Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power
voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics
shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond
such specified ranges.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor
products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under
certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please
be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and
software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment
for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone
is very difficult, please evaluate the safety of the final products or systems manufactured by you.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental
compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all
applicable laws and regulations that regulate the inclusion or use of controlled substances, including without
limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a
result of your noncompliance with applicable laws and regulations.
Renesas Electronics products and technology may not be used for or incorporated into any products or systems
whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You
should not use Renesas Electronics products or technology described in this document for any purpose relating to
All trademarks and registered trademarks are the property of their respective owners.
Datasheet
military applications or use by the military, including but not limited to the development of weapons of mass
destruction. When exporting the Renesas Electronics products or technology described in this document, you
should comply with the applicable export control laws and regulations and follow the procedures required by such
laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or
otherwise places the product with a third party, to notify such third party in advance of the contents and conditions
set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third
parties as a result of unauthorized use of Renesas Electronics products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent
of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in
this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes
its majority-owned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas
Electronics.
All trademarks and registered trademarks are the property of their respective owners.
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use
of these circuits, software, or information.
2.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
3.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
4.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or
third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.
5.
Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on
the product's quality grade, as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; and industrial robots etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical
implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it
in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses
incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
6.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or systems manufactured by you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
9.
Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or
regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the
development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the
contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics
products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2801 Scott Boulevard Santa Clara, CA 95050-2549, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3
Tel: +1-905-237-2004
Renesas Electronics Europe Limited
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Tel: +44-1628-585-100, Fax: +44-1628-585-900
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Tel: +49-211-6503-0, Fax: +49-211-6503-1327
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Room 1709, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100191, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
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Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai, P. R. China 200333
Tel: +86-21-2226-0888, Fax: +86-21-2226-0999
Renesas Electronics Hong Kong Limited
Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2265-6688, Fax: +852 2886-9022
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit 1207, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics India Pvt. Ltd.
No.777C, 100 Feet Road, HALII Stage, Indiranagar, Bangalore, India
Tel: +91-80-67208700, Fax: +91-80-67208777
Renesas Electronics Korea Co., Ltd.
12F., 234 Teheran-ro, Gangnam-Gu, Seoul, 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141