Using Signaltap Ii Embedded Logic Analyzers in Sopc Builder Systems
Using Signaltap Ii Embedded Logic Analyzers in Sopc Builder Systems
Using Signaltap Ii Embedded Logic Analyzers in Sopc Builder Systems
Introduction
Objective
This application note explains how to use a SignalTap II ELA to monitor
signals located inside a system module generated by the SOPC Builder.
The examples described in this document use the standard hardware and
count binary software. A simplified version of a block diagram of the
system is shown in Figure 1. This system contains a Nios II processor, an
on-chip memory, and an interface to external DDR SDRAM memory,
among other things. The count binary program counts from 0 to 0FF
repeatedly. Output of the counting process is displayed on the LEDs, the
seven segment display, and the LCD. Four push buttons are used to
control output to these devices.
Figure 1. An Example SOPC Builder System
LCD
Module
LCD Controller
CPU
DDR
SDRAM Controller
System
Interconnect
Fabric
PIOs (2)
(3)
(1)
DDR
SDRAM
Buttons
On-Chip Memory
Notes to Figure 1:
(1)
(2)
(3)
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AN-323-1.1
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This document does not discuss the contents of the standard design
example, but you can explore the design in SOPC Builder and refer to the
readme.txt in the design directory to gain a better understanding.
System Requirements
To complete the steps in this document, you need the following:
Design Files
The design files that accompany this application note are included in the
examples directory installed with the Nios II Embedded Design Suite.
The default location is:
<Altera tools install dir>\<version>\nios2eds\examples
Designing with
SignalTap II and
SOPC Builder
Systems
The following steps guide you through opening a Quartus II project that
includes an SOPC Builder-generated system module, and creating a
SignalTap II ELA to analyze signals in the system.
Copy the entire folder for the Nios II standard example design for
your particular board to a location where it can be edited. This
folder is located in the following path:
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2.
3.
4.
5.
6.
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If you are using VHDL as your primary HDL: <Altera tools install
dir>/<version>/nios2eds/examples/vhdl/<your-nios2-boardtype>/standard
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7.
Click OK.
8.
In the Quartus II software, open the Tools menu and select SOPC
Builder. The SOPC Builder software opens as shown in Figure 3.
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9.
Click on the System Generation tab inside the SOPC Builder and
then click Generate, which is the button located at the bottom of the
screen. (This may take a few minutes to complete.)
11. Go to the Processing menu, point to Start and select Start Analysis
& Elaboration to compile the design.
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Before you can connect the ELA to signals in your design, you
must first compile the design to build the node database. For this
step, you do not need to fit the design completely. The Start
Analysis & Elaboration command builds the node database,
but stops before the fitting step.
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2.
Open the File menu, point to New and click Project to create a new
project.
3.
4.
Select Count Binary from the Select Project Template list as shown
in Figure 4.
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5.
2.
3.
4.
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5.
Click OK.
6.
2.
3.
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a.
b.
c.
d.
e.
f.
g.
h.
Click OK.
Specify 256 for the Data Sample depth as shown in Figure 6. Leave
the other settings at their default values.
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In steps 4-11, you specify the signals you wish to monitor by searching in
the Node Finder and adding signals to the Selected Nodes list. The
signals to be monitored in this tutorial are selected from three major
entities within the system: the interfacing signals for DDR SDRAM,
signals within internal registers of PIO, and the signals for on-chip RAM.
Steps 4 - 8 describe how to add DDR SDRAM interfacing signals to your
SignalTap II file by searching through the Node Finder and adding the
appropriate signals to the Selected Nodes list.
4.
5.
Bring up the Select Hierarchy Level dialog box and search for the
entity named ddr_sdram_0:the_ddr_sdram 0.
6.
7.
8.
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d. ddr_cke
e. ddr_cs_n
f. ddr_ras_n
g. ddr_we_n
h. local_rdata (bus node only)
i. local_rdata_valid
j. local_read_req
k. local_wdata (bus node only)
l. local_write_req
Figure 7. DDR SDRAM I/O Pins Selected in the Node Finder
Step 9 explains how to add PIO internal register signals to your SignalTap
II file by searching in the Node Finder for appropriate signals, then
adding them to the Selected Nodes list.
9.
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Steps 10-11 describe how to add on-chip RAM signals to your SignalTap
II file by searching in the Node Finder for appropriate signals, then
adding them to the Selected Nodes list.
10. Repeat steps 4-8, this time searching for the
onchip_ram:the_onchip_ram entity and selecting the following
nodes as shown in Figure 9.
a.
b. write
c. writedata (bus node only)
Figure 9. On-Chip Memory Signals Selected in the Node Finder
11. Next, set the ELA trigger condition. Right-click on the row
NiosII_<board name>_standard_sopc:NiosII_<board
name>_standard_sopc_instance|ddr_sdram_0:the_ddr_sdram_0|
local_read_req in the Trigger Conditions column. Select
Rising Edge as shown in Figure 10.
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For more information about using SignalTap II, see the Design Debugging
Using the SignalTap II Embedded Logic Analyzer chapter in volume 3 of the
Quartus II Handbook.
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1.
On the File menu, click Save in order to save your SignalTap II file.
2.
Click Yes when a dialog box asks you if you want to enable the
SignalTap II ELA for the current project.
3.
4.
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a.
b.
b.
c.
Click Close.
Click the ... button next to the SOF Manager field in the JTAG
Chain Configuration area, select the file Nios II_<board
name>_standard.sof as shown in Figure 11.
Click the Program Device button next to the SOF Manager field to
download the .sof configuration file.
When the .sof finishes downloading, the Instance Manager field displays
Ready to acquire as shown in Figure 12.
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2.
Click the Run Analysis button to arm the ELA. The Instance
Manager field should change to Acquisition in progress as shown
in Figure 13.
At this point, the ELA is armed and waiting for the trigger condition to
occur.
3.
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4.
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After the program starts running, it triggers the ELA to capture data
when there is read operation from the DDR SDRAM memory. In our
example, the read operation is performed when the Nios II
processor begins executing from DDR SDRAM. The Data tab in the
SignalTap II window displays the captured waveforms as shown in
Figure 15.
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5.
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Take some time to view the signals. You can left-click the waveforms
to zoom in or right-click to zoom out. Figure 16 shows the zoomed
in version of the waveform shown in Figure 15. For Figure 16, the
read operation can be summarized as follows:
a.
b.
c.
d.
For more information about the operation of this controller, refer to the
DDR and DDR2 SDRAM Controller Compiler User Guide.
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To look at the interrupt operation, select the Setup tab and change the
previous trigger condition to Dont Care. Next, set the
Trigger Conditions to be Falling Edge of NiosII_<board name>
_standard_sopc:NiosII_<board name>_standard_sopc_instance
|button_pio:the_button_pio|in_port[0] as shown in Figure 17.
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Figure 17. Changing the Trigger Condition for Monitoring Interrupt Operation
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For more information about the internal registers of a PIO core, see the
PIO Core chapter in volume 5 of the Quartus II 7.2 Handbook.
Helpful Hints
for Using
SignalTap II
Effectively
The following helpful tips will improve your efficiency when you use the
SignalTap II Embedded Logic Analyzer in SOPC Builder systems.
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force the Quartus II software to preserve these signals by adding the keep
or preserve attribute in the source HDL to the signals you want to
monitor.
The keep attribute is used for a wire or net node. For example:
In Verilog:
wire my_wire /* synthesis keep = 1 */:
In VHDL:
signal my_signal: bit;
attribute syn_keep : boolean;
attribute syn_keep of my_signal: signal is true;
The preserve attribute is used for a register. For example:
In Verilog:
reg my_reg /* synthesis preserve = 1 */:
In VHDL:
signal my_reg: stdlogic;
attribute preserve : boolean;
attribute preserve of my_signal: signal is true;
Documents
Referenced
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Revision History
Revision History
Table 1. Document Revision History
Date and Document
Version
November 2007 v1.1
Changes Made
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Initial Release
Summary of Changes
Major content
additions and updates
throughout the bulk of
the document.
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